JPH0783278B2 - Frame data creation circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame data creation circuit for creating frame data in digital code transmission, and more particularly to a double error correction coding technique for transmission information.

(Background of the Invention) As is well known, in digital code transmission, a plurality of types of information are transmitted in frame units. However, these pieces of transmission information are regarded as one piece of transmission information, and error correction encoding (that is, 1
It is customary to perform double error correction coding). But,
For example, as in the case of FM multiplex broadcasting, it may be necessary to perform double error correction coding on specific information in one frame depending on the application.

FIG. 1 shows an example of frame data used in digital code transmission of information to be broadcast in addition to main broadcast of FM broadcast. This example is digitized voice (voice data 13)
In the case where a certain type of information (data 14) other than the voice information is transmitted in one frame, the data 14 is subjected to double error correction coding.

In FIG. 1, 11 is a frame synchronization signal (frame code: FC), which has a predetermined pattern of 18 bits, for example. Reference numeral 12 is a mode control, which is a control signal for designating the content of subsequent transmission information. Therefore, this mode control 12 may be unnecessary depending on the application.

The voice data 13 is, for example, a 32 kbps data signal quantized by ADPCM (adaptive differential pulse code modulation). This signal data 13 is transmitted, for example, 182 × 34 = 6188 bits per frame.

The data 14 is transmitted, for example, 190 bits per frame. The parity B15 is composed of 82 parity bits obtained by encoding the data 14 with the (272,190) code. The final parity A16 is the voice data 13, the data 14 and the parity B15 which are laterally encoded by the (272,190) code to obtain 82 × 34 = 278.
It consists of 8 parity bits.

A circuit for creating frame data having such a structure may be configured as shown in FIG. 4, for example. Fourth
In the figure, 41, 44 and 46 are memories, 43 and 45 are parity bit adding circuits, and 42 and 47 are selectors.

This circuit is constructed along the flow of signals and operates roughly as follows. The timing control and the like are performed by a control circuit (not shown).

One frame of the 6188-bit / frame audio data 13 is stored in the memory 41.

FIG. 5 shows a write operation to the memory 41. The audio data 13 is sequentially written in the unit of 4 bits in the vertical direction, and is similarly written in the unit of 2 bits at the final column.

On the other hand, one frame of 190-bit / frame data 14 is input to the parity bit adding circuit 43, where (27
2,190) encoding is performed and the result is stored in memory 4
Stored in 4. As shown in FIG.
A bit data 14 and a parity B15 consisting of 82 parity bits are vertically written and stored in 8-bit units.

Next, the memory 41 and the memory 44 are alternately selected row by row by the selection operation of the selector 42, and the stored contents of the nth row are read out in the horizontal direction addressed to 1 bit, which is stored in the parity bit addition circuit 45 ( 272,190) code and is sequentially written in the memory 46 in the horizontal direction (7th
Figure (a)).

Then, by the selection operation of the selector 47, first, the respective signals of the frame code and the mode control are sequentially transmitted in a bit serial manner, and then the contents of the memory 46 are transmitted in a bit serial manner. That is, the selector 47 outputs the frame data having the structure shown in FIG. Note that the read control of the memory 46 is performed by an interleave method in which one bit is obliquely read as shown in FIG. 7 (b).

(Problems to be Solved by the Invention) By the way, as shown in FIG. 4, when the frame data generation circuit is configured along the flow of signals, there is an advantage that timing control, memory control, etc. become easy. , Two parity bit adding circuits are required. Although three memories are shown in the figure, there is a problem that the number of components tends to increase and the circuit scale increases because the required number of memories cannot be increased at the same time because reading and writing cannot be performed at the same time.

The present invention has been made in view of such a problem, and an object thereof is to create frame data having double error correction coding for a part of transmission information in one transmission frame. In this case, when the double error correction coding is performed with the same code, the first error correction coding applied to only one of the plurality of transmission information can be performed at least within the frame synchronization signal transmission period. Accordingly, it is to provide a frame data creation circuit having a simple configuration and capable of reducing the circuit scale.

(Means for Solving the Problems) In order to achieve the above object, the frame data creation circuit of the present invention has the following configuration.

That is, in the frame data generation circuit of the present invention, one transmission frame includes attribute information including at least the frame synchronization signal of the frame synchronization signal and the control signal that specifies the content of the subsequent transmission information, a plurality of transmission information, and Frame data including parity to be added to transmission information, error correction coding processing is performed on the entire plurality of transmission information, and one designated transmission information of the plurality of transmission information is A frame data creation circuit for creating frame data in the case of performing double error correction coding in which individual error correction coding processing is performed with the same code prior to error correction coding processing for the whole; One transmission information consists of data obtained by individually performing the first error correction coding and the remaining transmission information. First and second storage means having different first and second storage areas for alternately storing frame data for each transmission frame, and a second error correction code for the entire subframe data A third storage area having different third and fourth storage areas different from the first and second storage areas for alternately storing the framed data for each successive frame data
And a fourth storage means; one input is the attribute information and the other input is the frame data alternately read from the third and fourth storage areas.
A first selector which sends the output as an output consisting of successive data strings of the attribute information and the frame data while switching the input; one input is the one transmission information, and the other input is the first and second memories A second selector that outputs the sub-frame data alternately read from the area while switching the respective sub-frame data; receives the one transmission information or the sub-frame data output from the second selector, An error correction coding circuit for performing the second error correction coding process or the second error correction coding process and transmitting the sub frame data or the frame data; one input of the remaining transmission information of the other The input is the output of the error correction coding circuit, the residual transmission information and the first error correction coding process Are stored alternately in the first allocation areas pre-allocated in the first and second storage areas, respectively, and those subjected to the second error correction coding processing are respectively stored in the third and fourth storage areas. A third selector for alternately switching to a storage area and outputting; a read control for alternately reading the contents alternately stored in either one of the third or fourth memory for each successive frame; Control for transmitting the frame data subsequent to the attribute information while performing switching control for one selector, first to fourth storage means, first to third selectors, and error correction coding circuit And an address counter for initializing the start position of each transmission frame by a reset signal received from an external system. During the period, switching control of the second and third selectors is performed, the one transmission information is input to the error correction coding circuit, the first error correction coding process is performed, and its output is the frame data. Control for alternately writing to the first allocation area included in the first and second memories with a clock faster than the transmission clock of the first and second transmissions of the frame data by the first selector. Switching control of the selector and the first of the first and second storage areas
Write control for alternately writing to the second allocation area excluding the allocation area is performed, and the first or second of the remaining transmission information is controlled.
Writing to the area and switching control of the second selector and alternate reading control of the stored contents alternately stored in either the first or second storage area during the writing and the synchronization. And a control circuit for controlling the sub-frame data to be input to the error correction coding circuit for use in the second error correction coding process.

(Operation) Next, the operation of the frame data creation circuit of the present invention configured as described above will be described.

At each transmission frame transmission timing, the first selector is switching-controlled to alternately read the frame data stored in each of the third storage means and the fourth storage means, and at least the frame of the frame synchronization signal and the control signal. The attribute information including the synchronization signal is sent in advance. For example, when the attribute signal and the frame data read from the third storage means are sequentially sent in the nth transmission frame sending period, During the information transmission period, the second and third selectors are switch-controlled to input one piece of transmission information to be subjected to double error correction encoding of the transmission information to the error correction encoding circuit, and to output the output, for example. High-speed writing is performed in the first storage means. In the frame data transmission period, the switching control of the third selector and the writing control of the first storage means are performed to write the remaining transmission information of the transmission information that is not subjected to the double error correction coding. At the same time, the sub-frame data including the transmission information that has been subjected to error correction coding processing and the remaining transmission information is input to the error correction coding circuit by the switching control of the second selector and the reading control of the second storage means. The output is written as frame data by the switching control of the third selector and the writing control of the fourth storage means to prepare for the next frame data transmission.

As is clear from the above description, reading and writing are alternately performed in the first and second storage means for each transmission frame sending period, and the same applies to the third and fourth storage means, and the same. There is no conflict between read and write for the storage means. That is, one storage device can be used.

In short, according to the frame data generation circuit of the present invention, when the double error correction coding is performed with the same code, the first error correction coding for one specific transmission information of the plurality of transmission information is performed. Since it is performed during the transmission period of the frame synchronization signal or the attribute information including this and the control signal, during the frame data transmission period, the error correction coded frame data for the entire multiple transmission information is processed. Can be created. Here, this circuit is 1
One error correction coding circuit and four storage means can be mainly configured, and since the four storage means cannot be read and written at the same time, the storage area of one storage device is made to correspond to each of four sections. be able to.
That is, there is an effect that the configuration can be simplified and the circuit scale can be reduced.

(Examples) Examples of the present invention will be described below with reference to the drawings.

In the frame data generation circuit of the present invention, one transmission frame is composed of a frame synchronization signal and frame data, or a frame synchronization signal, a control signal and frame data, and the frame data is composed of a double number of transmission information, and an error correction code is provided for the whole. It is being processed and 1 of them
For one piece of transmission information, the frame data is created in the case of performing double error correction coding in which error correction coding processing is performed twice with the same code prior to error correction coding processing for the entire transmission information. As such a transmission frame, for example, there is one shown in FIG. Although FIG. 1 has been described above, the description thereof will be omitted, but the circuit for creating the frame data in this transmission frame is configured as shown in FIG. 2, for example.

In FIG. 2, 1 is a (third) selector, 2 is a RAM,
3 is a (first) selector, 4 is a (second) selector, 5
Is a parity bit addition circuit as an error correction coding circuit, and 6 is a control circuit for controlling the operation timing of each of the above elements.

The control circuit 6 generates, for example, a ROM in which a predetermined control program such as the operation timing of each element is set, and a read address of this ROM, and the start position of each transmission frame is initialized by a reset signal. An address counter is basically provided, and predetermined signals (a, b, c, d, e) are output from this ROM to each element.

As shown in FIG. 3, the RAM2 is divided into four storage areas, of which the storage areas (I) and (II) are the first and second storage areas of the first and second storage means. The storage areas (III) and (IV) function as the third and fourth storage areas of the third and fourth storage means, respectively.

Writing to and reading from these storage areas are performed based on a signal b from the control circuit 6.

The parity bit adding circuit 5 is for performing error correction coding by the (272,190) code, like the parity bit adding circuits 43 and 45 shown in FIG. The first and second error correction encodings are performed based on the signal e from the control circuit 6.

Upon receiving the signal c from the control circuit 6, the selector 3 first sequentially outputs the frame code (FC) 11 and the mode control (MC) 12, which are attribute information, in bit series, and then RA
The contents of the storage area (III) or MIV (IV) of M3 are alternately output for each transmission frame.

The selector 4 receives the signal d from the control circuit 6 and outputs the RAM2
Of either the storage area (I) or the storage area (II) (alternate for each transmission frame) and the data 14 are output to the validity bit addition circuit 5.

The selector 1 receives the signal a from the control circuit 6 and outputs either the audio data 13 or the output of the parity bit adding circuit 5 to write one into the four storage areas of the RAM 2. .

In the above configuration, during each transmission frame transmission period, the selector 3 interleaves the 18-bit frame code (FC) 11, the 16-bit mode control (MC) 12, and the storage area (III) or the same (IV). The 9248-bit frame data read by the method is sequentially output, and the frame data is created as follows.

First, during the transmission period of the frame code (FC) 11 and the mode control (MC) 12, the data 14 is taken into the parity bit addition circuit 5 at a clock which is eight times as fast as the transmission clock (for example, 48 KHz) and the 190-bit data is transferred. And the 82-bit parity B is used for the first error correction coding process, and the processing result is stored in the storage area (I) during the n-th transmission frame transmission period,
The data is written in the storage area (II) during the + 1st transmission frame transmission period. That is, it is written alternately in each transmission period of each transmission frame.

Then, in the next 9248-bit frame data transmission period, the operation clock is divided into four and the following various operations are performed in parallel. That is, in the n-th transmission frame transmission period,
The 6188-bit audio data 13 is written in a predetermined area of the storage area (I) by using the divided clock to form subframe data as shown in FIG. 3 (a). This write operation is 18
It takes in two clocks and pauses for 90 clocks, which is repeated 34 times. Further, since the same operation is performed on the memory area (II) at the (n-1) th time, subframe data is read from the memory area (II) using the second divided clock (FIG. 3 (b)). It is input to the parity bit adding circuit 5 and its output is written in, for example, the storage area (III) by using the third divided clock to form frame data as shown in FIG. 3 (c). Further, with respect to the storage area (IV), the same operation was performed at the (n-1) th time, so
The frame data is read from the storage area (IV) by the interleave method using the divided clock (FIG. 3 (d)).

In addition, although the frame data including the voice data has been described in the present embodiment, the same applies to the frame data format in which the double error correction encoding is performed on one of the plurality of transmission information that does not include the voice data. Of course you can.

(Effects of the Invention) As described in detail above, according to the frame data generation circuit of the present invention, when the double error correction coding is performed with the same code, the first error correction coding is the frame synchronization signal or Since this is performed within the transmission period of the control signal, the frame data subjected to the second error correction coding (the first transmission for the remaining transmission information) in the frame data transmission period can be created. Here, the present circuit can be configured mainly with one error correction coding circuit and four storage means, and since the four storage means cannot be read and written at the same time, the storage area of one storage device is 4 It can correspond to each divided. That is, there is an effect that the configuration can be simplified and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a structural example of a transmission frame targeted by the present invention, FIG. 2 is a structural block diagram of a frame data creating circuit according to an embodiment of the present invention, and FIG. 3 is a structural example of RAM 2 and write / read control. FIG. 4 is an explanatory diagram of the operation, FIG. 4 is a block diagram showing the configuration when the frame data shown in FIG. 1 is created along the signal flow, and FIGS. 5 to 7 are the memories shown in FIG. FIG. 7 is an explanatory diagram of a configuration example of and a read / write control operation. 1,3,4 ... Selector, 2 ... RAM, 5 ... Parity bit addition circuit, 6 ... Control circuit.

Claims (1)

[Claims] 1. A transmission frame includes attribute information including at least a frame synchronization signal of a frame synchronization signal and a control signal designating contents of subsequent transmission information, a plurality of transmission information and a parity added to this transmission information. Error correction code for all of the plurality of pieces of transmission information, and for one designated piece of transmission information of the plurality of pieces of transmission information, an error correction code for the whole piece of transmission information. A frame data creation circuit for creating frame data when performing double error correction coding in which individual error correction coding processing is performed with the same code prior to the coding processing;
Subframe data composed of data obtained by individually performing first error correction coding on one transmission information and residual transmission information are alternately stored for each transmission frame.
And first and second storage means having a second storage area, and the frame data that has been subjected to the second error correction coding for the entire subframe data, alternately for each successive frame data. Third and fourth storage means having different third and fourth storage areas different from the first and second storage areas to be stored; one input being the attribute information and the other input Is the frame data alternately read from the third and fourth storage areas, and is a first selector which sends the output as an output consisting of successive data strings of the attribute information and the frame data while switching these two inputs. And; one input is the above 1
A second selector that outputs the other one of the transmission information, which is the sub-frame data that is alternately read from the first and second storage areas and that switches and outputs the sub-frame data;
The one sub-frame obtained by receiving the one transmission information or the sub-frame data output from the second selector and performing the first error correction coding process or the second error correction coding process on the sub-frame An error correction coding circuit for transmitting data or the frame data; one input is the residual transmission information, and the other input is the output of the error correction coding circuit, and the residual transmission information and the first error Those subjected to the correction coding processing are alternately stored in the first allocation areas pre-allocated to the first and second storage areas, respectively, and those subjected to the second error correction coding processing are processed to the third storage area. And a third selector for alternately switching to and outputting to the fourth storage area; and for successively outputting the contents alternately stored in either one of the third and fourth storages. Control for sending the frame data subsequent to the attribute information while performing read control for alternately reading for each frame and switching control for the first selector, and the first to fourth storage means and the fourth storage means. 1 to 3
Of the attribute information, which has a program for controlling the operation of the selector and the error correction encoding circuit and which has an address counter for initializing the start position of each transmission frame by a reset signal received from an external system. , The switching control of the second and third selectors is performed, the one transmission information is input to the error correction coding circuit, the first error correction coding process is performed, and the output is output of the frame data. Control for alternately writing to the first allocation area included in the first and second memories with a clock faster than the sending clock;
Switching control of the third selector during the transmission period of the frame data by the first selector and the first and second selectors.
Writing control for alternately writing to the second allocation area excluding the first allocation area of the storage area of the storage area, and writing the remaining transmission information to the first or second area During the same period, the switching control of the second selector and the alternating read control of the storage contents alternately stored in any of the first and second storage areas are performed to execute the subframe data to the subframe data. And a control circuit that controls the input to the error correction coding circuit for the second error correction coding process.