JPH0782452B2 - Processor - Google Patents

Description

The present invention relates to digital arithmetic processing, and particularly to an arithmetic processing device suitable for data processing for accessing a large amount of memory, as represented by drawing processing in a bitmap display. Regarding

[Conventional technology]

The drawing process in the bitmap display is basically a data calculation between rectangular areas on the bitmap memory, which is called a raster calculation. If this raster calculation is to be realized by a program, the processing is as shown in FIG.
This is realized by the processing shown in. In the figure, destination data means destination data. The number of times the process shown in the figure is repeated is proportional to the area of the rectangular region, and may be in the order of 10 ⁵ to 10 ⁶ . 1 more
It can be said that the memory access instruction is three instructions out of the five instructions of the one processing, and the processing time of the raster operation is determined by the memory access time. In order to increase the speed of the raster calculation, the read-modify-write is realized by using the hardware of the raster calculation so that it can be executed by three instructions as shown in FIG. 4 (b). Among these, the repeated judgment instruction is unrelated to the memory access, and when the memory write access and the repeated judgment instruction are executed in parallel, if the memory access is slower than the instruction execution, the judgment instruction is the memory access. Included in access time. The processing time of this result diagram is determined only by the memory access time, and the execution time of the judgment instruction can be ignored, which realizes high speed. To execute the memory write access and the arithmetic processing in parallel, the write address and A method in which the write data is latched in the register and the arithmetic processing unit executes the next instruction without waiting for the completion of the write access can be considered. An example of a system using this idea is an example of a system based on Am29116 manufactured by Advanced Micro Devices.

[Problems to be solved by the invention]

The above-mentioned conventional technique can realize parallel operation with data operation at the time of writing to the memory, but does not consider parallel operation at the time of reading from the memory and cannot speed up in more complicated data processing. was there.

An object of the present invention is to provide an arithmetic processing unit that executes efficient parallel operation even when reading a memory.

[Means for solving problems]

The above-mentioned object is to provide a means for controlling the read data input timing at the time of memory read access by a program, and to make the read data input timing from the memory and the read data input timing on the program independent, so that the memory is also read High-speed processing is achieved by realizing parallel operation of access and arithmetic processing.

The circuit configuration is such that at least one read data storage register is provided, a register to be input at the time of memory read access is designated, and the process of inputting to the designated register and other arithmetic processes are executed in parallel.

In a processor that does not execute normal memory access and operation in parallel, wait until data is input to the register specified at the time of memory read, and execute the next instruction after the input is completed to execute operation on the data in memory. set to target. on the other hand,
In the method of designating the register to be input at the time of a read request and making the contents of that register an arithmetic target after the input, the memory access is started by the read request, but the processor does not enter the waiting state and executes the next instruction. After the memory access is completed, the input data can be calculated normally as in the case of the processor, so by exchanging the instruction unrelated to the memory data operation and the memory data operation instruction, the operation can be executed during the memory access. In comparison with a normal processing device, high-speed processing can be performed as long as the waiting state is eliminated.

[Action]

To control the read data input timing from the program, when the program controls the read data input timing after the memory read access request, if the data has already been input from the memory, the data is used and the input from the memory is performed. If not, the wait state is entered, and after the input from the memory is completed, the data is used to continue the operation. As a result, the arithmetic processing unit can realize the parallel operation of the memory read access and the arithmetic processing by placing the instruction that does not require the read data after the read access request before the instruction that requires the read data. Further, by causing the instruction requiring the read data to control the read data input timing, correct data can be received even when the memory access is slow.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of the arithmetic processing unit of the embodiment. 1 is an instruction register (IR), 2 is a control circuit (CNTL), 3 is an operation data selector (SEL), 4 is a data operation unit (ALU), 5
Is a general-purpose register (GR), 6 is a read data storage register (IDR), 7 is a read data work register (MR), 8 is a write data register (ODR), 9 is a memory address register (MAR), and F is a fetch signal. , W is a wait signal, L is a data latch signal to the read data storage register 6, A is a memory address signal, D is a memory data signal, and AK is a memory acknowledge signal. The specific configuration of the control circuit 2 will be described later.

FIG. 2 shows the operation timing of the control circuit 2 of FIG.
In the figure, CLK is a clock of the arithmetic processing unit, IL is a load signal to the instruction register 1, IRD is data of the instruction register 1, M
A is a signal indicating that IRD is a memory access instruction, FA
Is a signal indicating a fetch instruction, and MM is a signal indicating that a memory is being accessed. FIG. 3 shows the instruction format of the arithmetic processing unit of this embodiment. M is a field indicating a memory access, FF is a field corresponding to the fetch signal F, OP is a calculation field, and OPR is a calculation data field.

Next, the operation of the arithmetic processing unit of the embodiment shown in FIG. 1 will be described. For register-to-register operations, general-purpose register 5
Data from the data processor 4 via the selector 3
And is stored in the general-purpose register 5. The selector 3 has a configuration for selecting two of the data from the three input terminals. In the case of memory write, the address data from the general-purpose register 5 is output to the address bus via the memory address register (MAR) 9, and the write data from the general-purpose register (GR) 5 is output to the selector 3 and the data calculator 4. As described above, the data is output to the data bus via the write data register (ODR) 8. The memory write ends when the data is stored in the memory address register (MAR) 9 and the write data register (ODR) 8, and the execution shifts to the next instruction before the actual memory write access is completed.

The memory read is divided into a memory read request and a read data input. In the memory read request, the address data of the general-purpose register 5 is output to the address bus via the memory address register (MAR) 9, and the memory read request ends when the address data is stored in the memory address register (MAR) 9. Read data input is executed by setting FF to 1 in the instruction format shown in FIG. Since the fields other than FF are irrelevant, all the instructions whose FF of the arithmetic processing unit is not 0 can be executed.

The read data input operation will be described with reference to FIG. Second
In the figure, the instruction data I1 of the instruction data IRD is a memory read request, I2 is an instruction other than memory access, and I3 is an instruction whose FF is 1. The instruction I1 is input to the instruction register 1 by the instruction register load signal IL, and the memory read is started. The instruction I2 is loaded at the next clock, but I2 executes normally because it is not a memory access. At the next clock,
Instruction I3 is loaded. Since the FF of the instruction I3 is 1, the wait signal W becomes 1 by the MM signal indicating that the memory access is being executed. When the wait signal W becomes 1, the instruction load signal IL is suppressed and the update of the instruction address is also suppressed, so that the wait state is entered. By inputting the AK signal indicating completion of memory read, the signal MM indicating that memory access is being executed becomes 0, and the read data is stored in the read data work register 7. After that, at the next clock, the wait signal W returns to 0 because MM is 0, and the data latch signal L
Is output, the output of the read data work register 7, that is, the memory read data is stored in the read data storage register 6, and the read data input is completed. Since the wait signal W has returned to 0 at the next clock, the next instruction is loaded into the instruction register and the instructions are sequentially executed.

In Fig. 2, control circuit 2 when FF is 1 and weight is applied
However, it is clear that W is 0 when memory access is fast and no wait is applied. Since the read data is stored in the read data storage register 6 at the end of the instruction I3, the instructions I2 and I3 are
Refers to the contents of the read data storage register 6,
The memory data before the execution of the read request by the instruction I1 will be referred to, and the contents of the read data storage register 6 will be the previous read access data or the current read access data only by the control of the FF field by the program without depending on the memory access time. Read access data can be determined.

As described above, in the present embodiment, the memory access and the parallel operation of the arithmetic processing can be easily performed by the program. Further, since the read operation is completed before the read data is actually calculated, the restoration process when the read data has an error is easy. In this embodiment, all instructions are FF
Although there is a field, even if it is limited to a specific instruction,
Alternatively, it is obvious that the method may be controlled by the decoded result of a plurality of fields. Further, although the read data storage register 6 is one in the present embodiment, it is obvious that a plurality of read data storage registers 6 may be used or a general-purpose register may be substituted.

Next, as a second embodiment of the present invention, a circuit configuration and an operation description in the case where a plurality of read data storage registers are provided will be described with reference to FIGS. FIG. 5 is a block diagram of the arithmetic processing unit of the second embodiment. In the figure, 6-1 and 6-2 are the first and second read data storage registers (IDR0,1), and 3-1 and 3-2 are the first and second operation data selectors (SEL1,2). ) Is shown, and the others are the same as in the embodiment of FIG. In the signals, M is a memory read signal, ID is an input register instruction signal, IL is an instruction latch signal, L0 and L1 are latch signals to the read data storage registers 6-1, 6-2, and IRD 'is instruction data. Others are the same as the embodiment of FIG.
FIG. 6 shows the operation timing of the control circuit 2. A concrete example of the control circuit 2 will be described later with reference to FIG. MA is a signal indicating that the instruction data is a memory read, FA is an instruction signal for transferring data from the input work register 7 to the read data storage registers 6-1, 6-2, and MM is indicating that the memory is being accessed. The signal is the same as in the previous embodiment. FIG. 7 shows the instruction format of the processing device of this embodiment. OP is the operation field, OPR is the operation data field, M is the memory access field, and FF is the field corresponding to the fetch signal F as in the previous embodiment, and the ID is unique to this embodiment. Of the read data storage register number.

The operation of the arithmetic processing unit of this embodiment will be described below. When the instruction of the arithmetic processing unit is an operation between registers, the data from the general-purpose register 5 passes through the selector 3-1 and the data in the read data storage register 6-1 or 6-2 is the selectors 3-2 and 3-. Via 1 to arithmetic unit 4
Is calculated and stored in the general-purpose register 5. When the instruction is a memory write access, the address data from the general-purpose register 5 is latched in the memory address register 9,
The write data from the general-purpose register 5 is latched in the output register 8 via the arithmetic unit 4, and the data necessary for the memory write operation that starts the memory access is held by the latch, so that the processing device writes the data. The execution of the next instruction is started without waiting for the completion of access.

If the instruction is a memory read access, the processor simply instructs the start of the read access. That is, the address data from the general-purpose register 5 is latched in the memory address register 9, the input data register number is designated by the ID signal, and the memory read access is started. After instructing to start the access, the processing device starts executing the next instruction and does not enter the waiting state. The read data of the memory is input by setting the F field of the processing device to 1.

The operation including this portion will be described with reference to the operation timing of the control circuit 2 in FIG. IRD 'in the figure is the instruction data of the processing device, and only the fetch portion of the read access is necessary for the explanation, so the instruction contents are not written for other instruction portions. First, the memory read signal MA is set to 1 by a read instruction (described by I ₁ , I _2, etc.), and the memory access signal MM is set to 1 at the trailing edge of MA. Thereby, the memory read access is started, and the value of the ID described together with the read instruction as shown in FIG. 7 is latched. When the ID signal is 0, the read data storage register 6-1 and the read data storage register 6-2 are designated. In FIG. 6, the latched ID signal is shown as IDD. The processor executes the read instruction after executing the next instruction I ₁ . At the time of execution of this instruction, the acknowledge signal AK from the memory has not been received, and therefore the state of waiting is entered.
The signal W indicating the wait state is generated by latching the memory access signal MM with the fetch signal FA. After that, when the acknowledge signal AK is input, the read data is latched in the input work register 7 and the waiting state is released, so that a new memory access is started. Latch signal to the read data storage register 6-1 at the end of this instruction
L0 is output and the memory data latched in the input work register 7 is input. Further, since the ID signal is 1 in this command, IDD also becomes 1. Although the I ₃ instruction is not a memory access, since the fetch signal F is a fetch instruction of 1, the latch signal L1 to the read data storage register 6-2 is output. While entering a wait state for in similar memory access and before the read command of the I _3, the fetch I _7, the waiting does not occur for later access completion. Latch signal L0 to the read data storage registers 6-1, 6-2,
L1 does not indicate the fetch instruction I ₃ or I ₇ , but is determined by the IDD signal set by the ID of the read instruction executed before that.

As described above, in this embodiment, the instruction of the read data storage register to be input at the time of the memory read request is performed,
All that is required is to issue a fetch instruction when inputting data. As a result, since it is not necessary to use the OPR in the operation data field for the instruction of the read data storage register, a normal operation can be performed even with the fetch instruction, and the fetch instruction need not be a dedicated instruction. As a result, the parallel operation of the memory access and the arithmetic processing can be realized by the same instruction as that of the normal processing device, so that the speedup can be achieved. In addition, since it is possible to write a program similar to that of a normal processing device just by instructing fetch before the instruction to operate the memory read data, it is possible to process the memory access and the arithmetic processing in parallel. No problem occurs.

FIG. 8 shows an example of the program description. Figure 8 (a)
Is an example of a normal processing apparatus, and FIG. 7B is an example of this embodiment. (R0) means that the address data is output from the register of R0. In (a) and (b), part of the register names and read data storage register names (IDR0, I
It is the same except that it is DR1) and that F that instructs fetch is attached to the instruction. In this way, since parallel operations of memory access are realized by describing almost the same instruction, it is easy to realize high-speed processing. Although the read data storage register is separately provided in the present embodiment, the general purpose register may be provided with means for storing the operation result and the memory data in the same instruction, and the read data storage register may be replaced with the general purpose register. The good is clear.

FIG. 9 is a specific circuit diagram of the control circuit 2 shown in FIG. G1 to 6 are AND gates, I1 to 3 are inverters, F1 to 3 are D flip-flops, and OSC is a clock generator of the processor. MA, FA, M with gates G1, 2 and flip-flops F1, 2
Generates M, W signals, gates G3, G5, G6, inverters I1, I3
The flip-flop F3 generates the signals L0 and L1, and the inverter I2 and the gate G4 generate the signal IL. The operation timing of this circuit is shown in FIG. 6 described above. In this circuit configuration, the timing of the completion of the fetch operation is the same as the timing of the completion of the instruction instructing the fetch, as is clear from the time chart of FIG. This means that when the read data storage registers IDR0 and IDR1 are referenced by the instruction instructing the fetch, the value before the fetch is executed is referenced. Another example of the timing of fetch operation completion is
In this method, the fetch operation is executed at the beginning of the instruction instructing the fetch, and the instruction instructing the fetch is executed after completion. In this case, if the read data storage registers IDR0, 1 are referenced by the fetch instruction instruction, the updated value after the fetch is referenced. Although the former is described in this embodiment, it is obvious that the latter is also within the scope of the present invention.

〔The invention's effect〕

According to the present invention, since parallel operations of memory access and arithmetic processing can be controlled by a program, arithmetic processing can be executed during memory access in data processing with many memory accesses, and processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram of an arithmetic processing unit according to an embodiment of the present invention,
2 is an operation waveform diagram of the embodiment of FIG. 1, FIG. 3 is a diagram showing an example of an instruction format used in the embodiment of FIG. 1, and FIG. 4 is a process for realizing a raster operation by a program. Flow, FIG. 5 is a block diagram of the arithmetic processing unit of the second embodiment of the present invention, FIG. 6 is an operation waveform diagram of the embodiment of FIG. 5, and FIG. 7 is used in the embodiment of FIG. FIG. 8 is a diagram showing an example of an instruction format, FIG. 8 is a diagram for explaining a program description in the present invention, and FIG. 9 is a concrete configuration diagram of the control circuit 2 in FIG. 1 …… Instruction register, 2 …… Control circuit, 3,3-1,3-2 ……
Operation data selector, 4 ... Data operation unit, 5 ... General-purpose register, 6,6-1, 6-2 ... Read data storage register, 7 ...
… Read data work register, 8 …… Write data register, 9 …… Memory address register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Fujikami, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Microelectronics Equipment Development Laboratory

Claims (18)

[Claims] 1. A data operation means for executing data operation and a logical operation, an operand data storage means connected to the data operation means for temporarily storing the data operated by the data operation means, and the operand data storage means. A data interface means disposed between the data storage device and the data storage device, an instruction interface means for temporarily storing an instruction to be executed, and an instruction interface for executing the instruction, and executing the instruction to connect the arithmetic means and the instruction interface means, When the memory read instruction is executed by the control means and a memory access operation for transferring data from the data storage device to the data interface means is performed, the memory access operation is performed by the control means for controlling the operand storage means. Continued to execute memory read instruction Data is transferred from the data interface means to the operand data storage device as one of the arithmetic processing, which is executed in parallel with the arithmetic processing of the executed instruction. An arithmetic processing unit, characterized in that a field is provided for performing the memory access operation for obtaining data from the data storage unit and the arithmetic process in parallel. 2. The data interface means includes memory data register means for storing the data read from the data storage device.
The arithmetic processing unit according to the item. 3. The arithmetic processing unit according to claim 1, wherein the operand data storage means includes at least one input data storage register means, and the memory read instruction includes at least one input. An arithmetic processing unit, characterized in that another field for indicating one of the data storage register means is included. 4. An instruction holding means for holding an instruction, a control means for executing an instruction from the instruction holding means and generating a control signal by executing the instruction, a data storage device for storing data, and a memory read instruction. Memory data storage means for holding transfer data from the data storage device by a memory access operation performed by the control means in response to a control signal output from the control means; and data transferred by the control signal from the control means. Each instruction is composed of arithmetic means for executing arithmetic or logical operation processing, and at least one input data storage means arranged between the memory data storage means and the arithmetic means for holding the read data. Perform arithmetic processing including data transfer from the memory data storage means to the input data storage means Memory access operation and arithmetic processing that includes first information and obtains data by performing the memory access operation in parallel with arithmetic processing of an instruction that is executed subsequent to execution of the memory read instruction. An arithmetic processing unit that executes the processes in parallel. 5. The arithmetic processing unit according to claim 4, wherein each of the instructions selects at least one of the input data storage means for holding the data transferred from the memory data storage means. An arithmetic processing device, comprising: 6. The arithmetic processing unit according to claim 4, wherein the data in the field of the instruction is the first
An arithmetic processing unit that is compatible with the information of. 7. An arithmetic processing unit according to claim 4, wherein said memory read instruction connected to said data storage device via an address bus and held in said instruction holding means executes said data An arithmetic processing unit comprising a memory address register for temporarily storing an address. 8. The arithmetic processing unit according to claim 7, wherein the memory data storage is performed by the first information of another instruction which is one of the instructions continuously retained by the instruction retaining means. An arithmetic processing unit provided with the second information for instructing one of the input data storage means to store the data read from the means and the memory read command. 9. A memory address register for accessing the connected data memory means, a memory data register means for receiving data from the connected data memory means,
Input data register means for storing data fetched from the connected memory data register means, general purpose register means for storing other data input for arithmetic processing from other than the data memory means, and the input data register, By means of arithmetic means for receiving data from the general-purpose register means as operand data input and performing arithmetic operation or logical arithmetic processing of the operand data input, and for controlling the memory address, memory data, input data and general-purpose register means and the arithmetic means. And an access address corresponding to the data to the memory address register, which is connected to an instruction storing means for storing the instruction and a data memory for storing the data. The decision is One of the memory access request instructions is executed to start the memory access to the data memory means, and the accessed data is independent and parallel to the execution of the instruction subsequent to the execution of the memory access request instruction. Stored in the memory data register means, the data fetch from the memory data register means to the input data register means is instructed by information contained in one of the subsequent instructions executed in parallel with the memory access, Thereby, the memory access is performed in parallel with the execution of the subsequent instruction, and the memory access and the instruction execution are performed in parallel. 10. The arithmetic processing unit according to claim 9, wherein the information for instructing that the fetching can be performed simultaneously with the execution of the subsequent instruction is included in a field of the one instruction. An arithmetic processing unit. 11. The arithmetic processing unit according to claim 9, wherein the input data register further comprises a plurality of input data registers, and the field of the memory access request instruction is one of the input data registers. An arithmetic processing device comprising information for instructing. 12. A memory address register means for accessing the connected data memory means, a memory data register means for receiving data from the connected data memory means, and an input data register for loading data from the connected memory register means. Means, arithmetic means for receiving data from the input data register means as operand data input, and performing arithmetic processing of the operand data input, and the instruction by controlling the memory address, memory data and input data register means and the arithmetic means. And a data storage device for storing data, the memory access request command being one of the above-mentioned commands. Data from executing An arithmetic processing unit for performing memory access and instruction execution by performing data access to data stored in a memory means at the same time as another instruction that is performed subsequent to the execution of the memory access request instruction. . 13. The arithmetic processing according to claim 12, wherein said loading from said memory data register means to said input data register means is instructed by information contained in another instruction. apparatus. 14. The input data register means comprises a plurality of input data registers, and each of the instructions has one field for selectively recognizing one of the input data registers. 13. The arithmetic processing unit according to claim 12, wherein the data stored in is loaded. 15. The memory address register means holds the address of the data memory means during execution of the memory access request instruction.
The arithmetic processing unit according to item 12. 16. A data calculation means for calculating data, an operand data storage means connected to the data calculation means for temporarily storing data processed by the data calculation means, the operand data storage means and the data. Data interface means arranged between storage devices, instruction interface means for temporarily storing instructions,
And a control means which is connected to the instruction interface means, executes the instruction from the instruction interface, and controls the data operation means and the operand data storage means by executing the instruction, and executes the memory access request instruction. The reading of data from the data storage device to the data interface means performed by the control means in accordance with data corresponding to the data in the field of another instruction that is executed subsequent to the execution of the memory access request instruction. It is performed independently of the arithmetic processing including the data transfer from the data interface means to the operand data storage means performed by the control means, and the transfer processing is performed while the arithmetic processing of the other instruction is being executed. To obtain data from the data storage device. An arithmetic processing device, characterized in that it executes a memory access operation and an arithmetic processing independently of each other. 17. An instruction holding means for holding an instruction, a control means for executing an instruction from the instruction holding means and generating a control signal by executing the instruction, a data storage device for storing data, and an execution of a memory access instruction. A memory data storage means for storing the data read by the control means from the data storage device according to a control signal from the control means output as a result, and an arithmetic operation or a logical operation processing of the read data according to the control signal from the control means. And at least one input data storage means for holding the read data, which is arranged between the storage means and the calculation means, and each of the instructions includes the memory data storage means First instruction to transfer data to input data storage means
Information is included, the memory access for reading data from the data storage device is performed by the execution of the memory access instruction independently of the arithmetic processing for transferring the data to the input data storage means, and the transfer is performed by the memory. An arithmetic processing unit characterized by performing memory access operation of data and arithmetic processing independently of each other by being performed during arithmetic processing execution of an instruction subsequent to an access instruction. 18. A memory address register means for accessing the connected data memory means, a memory data register means for receiving data from the connected data memory means, and an input for storing fetched data from the connected memory data register means. Data register means, general-purpose register means for storing other data used for arithmetic processing other than the data memory means, operand data input from the input data register means and general-purpose register means, and operation or logic of the operand data input Comprising arithmetic means for performing arithmetic operation, memory address, memory data, input data and general-purpose register means, and control means for controlling instruction execution of the instruction by controlling the arithmetic means. The access address corresponding to the data to the stage is determined by executing the memory access request instruction, which is one of the instructions, to start the memory access to the data memory means, and the memory of the accessed data. The data is stored in the data register means independently of the instruction executed subsequent to the execution of the memory access request instruction after the end of the memory access, and the data from the memory data register means to the input data register means is stored. When the fetch is instructed by the information included in one of the upper subsequent instructions executed by the control means, the memory access and the instruction execution connected to the instruction storage means for storing the instruction and the data memory means for storing the data An arithmetic processing unit characterized by performing and independently of each other.