JPS6115453B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control device having a plurality of levels, and particularly to a microprogram control circuit that realizes high-speed processing.

Conventionally, when controlling a certain device using a microprogram method, due to the simplification of the program and restrictions on the amount of hardware, the microprogram processing was performed sequentially at one level. There is. However, processing using a microprogram is slower than when the same function is implemented using wire logic, so particularly high-speed processing is required. When used in computers or peripheral devices, there are problems in terms of processing performance.

In addition, recently, LSIs with interrupt level control functions suitable for multilevel processing of microprograms have been developed.
etc. have been developed, but in these interrupt handling methods, first, an interrupt occurs in a microprogram that is being executed, and when the interrupt is accepted, the currently executing program is temporarily suspended, and the cause of the interrupt is After that, the corresponding jump destination is determined, and the process proceeds to the corresponding interrupt processing. With this method, each time an interrupt occurs, determining the cause and determining the jump destination takes the equivalent of two steps in program processing, so if high-speed processing is required, There is a problem with processing speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-level, microprogram interrupt control circuit with high processing speed.

The main point of the present invention is to add a level control circuit to the address control section, use the microprogram execution timing as it is for the interrupt processing timing, and execute interrupt acceptance determination and level conversion. This realizes level transitions without interrupting processing. A detailed explanation will be given below using examples.

FIG. 1 is a block diagram showing an example of a microprogram control device to which the present invention is applied. The contents are read from the microprogram memory (ROM) 2 according to the address given from the address control unit (ROMAR) 4 and set in the program register (PR) 3. The output of RP3 appears on the control bus (CTL BUS), and the register address, data,
Alternatively, μ via the instruction decoder (DEC) 5
-Given to P1. Furthermore, although not shown in the figure, the CTL BUS controls equipment that includes this control device. Used to specify the setting and clearing of various flip-flops and registers.

The contents of the external source register are placed on the IN BUS, and μ-P1 uses this to process the data. The processing result of μ-P1 is output to OUT BUS and given to an external destination and register. Also, ROMAR4 normally updates the built-in program counter by 1, but when executing a jump instruction etc., CTL BUS or
Capture and use the contents of OUT BUS.

The microprogram control system has lower processing efficiency than wire logic, so one step and the next step are executed simultaneously.
In FIG. 1, execution of one step starts from the beginning of the clock. In other words, at the rising edge of the clock, ROM2, which had been read up to that point,
The contents of PR3 are set to PR3, output on CTL BUS, and execution of one step starts. On the other hand, as the clock rises, ROMAR 4 updates the address and then starts reading the contents of the step from ROM2. The interrupt control circuit of the present invention is ROMAR
4. Of these, the circuit diagram of the level control section is shown in FIG.

Various external interrupts are entered into the interrupt register 6, which is triggered by the clock TP2 shown in FIG. Here, when a certain interrupt occurs, the output of register 6 goes to the priority encoder (PE) at the rising edge of TP2.
7 is given. The output of PE7 is given to the jump address register dedicated to interrupts, and ROMAR
It is used to determine the output of 4 and is also applied to the level division circuit 15. This dividing circuit can be constructed only from gates, and selects whether to set both two output bits to 1 or to set only the lower bit to 1 in response to various interrupts. On the other hand, the program level that has been executed up to that point is indicated by the lower two bits of the register (LEVEL) 10, and the comparator (COMP) 8 determines whether or not the interrupt is accepted. For example, if the currently executing program level is (0,0) and the interrupt level is (0,1), then
The output of COMP8 becomes "1", the flip-flop (F/F) 11 is set at the next rising edge of TP1, and the register 10 is triggered by the gates 13 and 14 at the rising edge of TP3. On the other hand, the 4-bit selector (SEL) 9 outputs the A side input when the S input is "0", and outputs the B side input when the S input is "1". Since this is set, the lower 2 bits of LEVEL10 are used as the upper 2 bits, and the interrupt level is used as the lower 2 bits, which are applied to the input of LEVEL10. Therefore, after inputting TP3, the output of LEVEL10 has the upper 2 bits (0, 0) and the lower 2 bits (0, 1).
Therefore, the execution level is from (0,0) to (0,
This means that we have moved on to 1).

On the other hand, although not shown in this figure, for ROMAR4, when F/F11 is set,
By controlling the contents of the jump address register to be selected as the ROMAR output, it is possible to jump to the interrupt destination.

Next, when a return instruction is issued in the interrupt processing microprogram, a trigger input is input to LEVEL 10 via gates 13 and 14 as before. On the other hand, in this case, F/F11 is cleared, so SEL9 selects the A side input, that is, the upper 2 bits are (0, 0) and the lower 2 bits are the previously saved level (0, 0). And give it to the input of LEVEL10. Therefore, when the RETURN command is issued, all outputs of LEVEL10 become 0, and the program level returns to (0, 0).

If level (1, 1) interrupts during level (0, 1) execution, exactly the same operation is performed. The time chart is shown in Figure 4.

As mentioned above, in conventional circuits, registers,
By simply adding a selector, a comparator, and a flip-flop, an interrupt control circuit that can automatically change the level of a microprogram can be realized. According to the present invention, in a high-speed microprogram control device using interrupts, it is possible to completely eliminate overhead in interrupt processing.
The processing efficiency of the device can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of a microprogram control device to which the present invention is applied, FIG. 2 is a circuit diagram of a main part showing an embodiment of an interrupt control circuit according to the present invention, FIG. 3 is a diagram showing clock pulses, and FIG. The figure is a time chart showing the level transition operation in FIG. 2. 6... Interrupt register, 7... Priority encoder, 8... Comparator, 9... 4-bit selector, 10
...4-bit register, 15...level division circuit.

Claims (1)

[Claims] 1. A program memory that stores a microprogram, an address control unit that controls the read address of this memory, a register that latches a 1-step instruction to be executed, and an operation that performs an operation according to the contents of the program. When an interrupt occurs in a microprogram control circuit that has a circuit and a clock generation circuit for program control, it is possible to determine the level of the program in parallel with the currently executing microprogram and accept the interrupt. A microprogram interrupt control circuit is provided with a control circuit that stores a level being executed and shifts the execution level to an interrupt level, thereby making a program level transition without interrupting program execution. 2. In the microprogram control circuit according to claim 1, when a return instruction is issued in the interrupt processing program, the level stored during the interrupt processing is read, and this level is used as the execution level for subsequent microprograms. A microprogram interrupt control circuit equipped with a control circuit that executes.