JPH0781153A - Printing device - Google Patents

Abstract

PURPOSE:To provide a printer which can simplify a control section of a printer, lower the cost and also increase the printing throughput. CONSTITUTION:A device comprises a transfer means constituted of a personal computer 81 and a printer 82 connected together through a Centronix interface 83 and transferring printer output data signals IF DATA for respective words from the computer 81 to the printer 82, a write control circuit 92 for issuing write control signals W-N based on data of bits selected out of all respective transfer printer output data signals IF DATA and a memory into which data for remaining bits of all respective printer output data signals IF DATA is written. The remaining bit data can be written into the memory without transmitting strobo pulse signals and the like from a personal computer 81 into the printer 82, and the transfer speed of the personal computer 81 can be set higher than the consumption speed of the printer 82.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printing apparatus which transfers print data from a personal computer to a non-impact printer and prints it.

[0002]

2. Description of the Related Art Conventionally, in a non-impact printer, 8-bit parallel interface (hereinafter referred to as "Centronics interface") is used for printing data developed by a personal computer into a raster image dot pattern.
Say. ) To the printer via.

In this case, the maximum value of the transfer speed of the print data is determined by the print data output program of the personal computer as the host device, but the hardware specifications of the Centronics interface are also the decisive factor. FIG. 2 is a block diagram of a personal computer in a conventional printing apparatus. As shown in the figure, a local bus 11, an external bus 13 and an internal bus 16 are provided inside the personal computer for sending various signals. The local bus 11 is provided with a CPU 12, the external bus 13 is provided with an I / O channel slot 14 for expanding the functions of the personal computer, and the internal bus 16 is provided with various basic functions LS constituting the personal computer.
I is connected.

An address buffer 18 and a data buffer 19 are provided between the local bus 11 and the external bus 13.
An address buffer 21 and a data buffer 22 are provided between the external bus 13 and the internal bus 16, and various signals are sent via the address buffers 18 and 21 and the data buffers 19 and 22. 23 is a RAM for storing print data, 24 is a ROM for storing the program of the CPU 12, 25 is an interrupt controller for controlling an interrupt signal for interrupting the CPU 12, and 26 is a printer (not shown). It is an I / O port that forms a Centronics interface between them. In addition, 31 is a clock, 32 is a numerical processor, 34
Is a DMA controller, 35 is an address latch, 36 is a page register, 37 is a memory data buffer, 39 is a slave CPU, 40 is a keyboard, 41 is a timer, 4
2 is a speaker, 43 is a real time clock, and 44 is a battery.

FIG. 3 is a block diagram of a Centronics interface on the personal computer side in a conventional printing apparatus.
In the figure, 16 is an internal bus, 46 is an I / O channel,
Reference numeral 48 is a Centronics interface connector for connecting a printer (not shown) to the personal computer, 49 is a data latch register used as an output port when transferring print data from the personal computer to the printer as a printer output data signal IF DATA, and 50 is from the personal computer. A printer control register used as an output port when sending a strobe pulse signal STROBE-N, an auto line signal AUTO FEED, a printer initialization signal INIT-N, a printer select signal SLCT IN and an interrupt enable signal IRQ Enable to the printer, 51 Is a printer select status signal SLCT from the printer, a printer busy signal BUSY-N, a paper out detection signal PE, an acknowledge signal ACK-N and a printer error signal Error-. A printer status register used as an input port when receiving N.

Various data are written in the data latch register 49, the printer control register 50, and the printer status register 51 by the CPU 12 (FIG. 2), and an I / O address for reading the written data is given. It FIG. 4 is an explanatory diagram of a register of the Centronics interface on the personal computer side in the conventional printing apparatus. In the figure, (a) is a data latch register 49, (b) is a printer control register 50, and (c) is a printer status register 51.

In the figure, the names of the data and signals of the Centronics interface, which are associated with the bit numbers of the internal bus 16 (FIG. 2), are shown. The data latch register 49, the printer control register 5
0 and the I / O address values of the printer status register 51 are "378H", "37AH", and "37", respectively.
It is represented by a hexadecimal number of 9H ".

IF DATA is a printer output data signal, STROBE-N is a strobe pulse signal, A
UTO FEED is an auto line signal, INIT-N is a printer initialization signal, SLCT IN is a printer select signal, IRQ Enable is a printer interrupt enable signal (not shown), Error-N is a printer error signal, and SLCT is a printer select status signal. PE is a paper-free detection signal, ACK-N is an acknowledge signal, BUS
Y-N is a printer busy signal.

FIG. 5 is a timing chart when transferring 1-byte print data from a personal computer to a printer in a conventional printing apparatus. In the parentheses below each signal in the figure, PC indicates the personal computer side, PR indicates the printer side,
The arrows indicate the transmission direction of each signal. The personal computer uses the acknowledge signal ACK-N and the printer busy signal BUSY.
When -N is received from the printer, the print data is output as an 8-bit printer output data signal IF DATA,
It is transferred to the printer by the strobe pulse signal STROBE-N.

That is, when the printer is ready to receive the transferred 1-byte print data (hereinafter referred to as "ready state"), an acknowledge signal ACK is sent.
-N is set to the low level for the time _TWA to notify the personal computer of the ready state. This acknowledge signal A
CK-N is input to the interrupt controller 25 (FIG. 2),
The CPU 12 activates the interrupt processing program and starts transfer of print data to the printer.

In this case, the CPU 12 reads the data of the printer status register 51 assigned to the I / O address and waits for the printer busy signal BUSY-N sent from the printer to go to the low level. Next, when the printer busy signal BUSY-N becomes low level, 1-byte print data to be transferred to the printer is written in the data latch register 49 assigned to the I / O address, and the 8-bit printer output data signal IF DATA is output. Transfer to the printer by the IF DATA signal line.

Subsequently, the CPU 12 sets the setup time T
_After waiting for _s , the strobe pulse signal STROBE-N is written in the printer control register 50 assigned to the I / O address, and the strobe pulse signal STROBE-N is set to the low level for the time T _WS . Note that the time T _H is the strobe pulse signal STROB.
Printer output data signal IFD at the rising edge of E-N
It is for holding ATA.

Next, the internal structure of the CPU 12 will be described. Fig. 6 shows the CP of a personal computer in a conventional printing device.
It is a figure which shows the register in U. In the figure, (a) shows a general-purpose register string, (b) shows a segment register string, and (c) shows a status control register string. In the figure, 55 is a general-purpose register string, 56 is a segment register string, and the segment register string 56 is combined with the general-purpose register string 55 to form a RAM 23 (FIG. 2), ROM 24, data latch register 49 (FIG. 3), It is used for designating addresses of the printer control register 50, printer status register 51, and the like. 57 is a status control register string.

Then, AX, DX, CX, BX, BP,
SI, DI, SP are registers forming the general-purpose register train 55, CS, DS, SS, ES are registers forming the segment register train 56, F, IP, MSW are registers forming the status control register train 57, The registers SI and DI are used as index registers, and the register SP is used as a stack point. The registers AX, DX, CX, and BX are all 16-bit registers, and a pair of 8-bit registers AH and AL, registers DH and DL, and register C.
H, CL, and registers BH, BL. Then, for example, the upper 8-bit data of the 16-bit data is stored in the register AX, and the lower 8-bit data is stored in the register AL.

The operation when the CPU 12 writes print data in the data latch register 49 will be described. First, the I / O address of the data latch register 49 is written in the register DX. Next, the 8-bit print data to be transferred to a printer not shown is registered in the register AX.
Write to the register AL of. Further, the port output instruction is executed to output the print data to the data latch register 49. In this way, the data latch register 4
When writing the print data in 9, the CPU 12 executes the instructions of the three steps.

FIG. 7 is a flowchart showing the operation of the CPU in the conventional printing apparatus. When the CPU 12 (FIG. 2) of the personal computer (not shown) transfers 1-byte print data to the printer (not shown), the printer inputs an acknowledge signal ACK− to the interrupt controller 25 of the personal computer.
N is set to low level by an interrupt program, and an interrupt is generated in the CPU 12 of the personal computer.

Next, in order to determine whether or not the busy signal BUSY-N has become low level, the data in the printer status register 51 (FIG. 3) is read. Then, when it is found that the printer is ready, the CPU 1
2 writes 1-byte print data in the data latch register 49. Subsequently, the CPU 12 causes the printer control register 50 to output the strobe pulse signal STROBE-.
N is sent to generate a strobe pulse. Step S1 The I / O address of the printer status register 51 is written in the register DX (FIG. 6) and the printer status register 51 is selected. In step S2, the data stored in the I / O address of the selected printer status register 51 is read. Step S3 Printer busy signal BUSY of the printer
Test the read data by masking bits other than the bit corresponding to -N. In step S4, it is determined whether the printer is busy. If not busy, go to step S5
If it is busy, the process returns to step S2. Step S5: Registers SI and D indicating the address of the RAM 23 storing the print data to be transferred to the printer
I is used to read the print data from the RAM 23 and write it in the register AL of the register AX. Step S6 The data latch register 4 is added to the register DX.
9 I / O address is written and the data latch register 49 is selected. In step S7, the print data is written in the I / O address of the selected data latch register 49. In step S8, the I / O address of the printer control register 50 is written in the register DX and the printer control register 50 is selected. Step S9 Strobe pulse signal STROBE-N
The data for making the low level is written in the register AL of the register AX. Step S10 The data of the register AL is written in the I / O address of the selected printer control register 50. Step S11 Strobe pulse signal STROBE-
Data for making N high level is written in the register AL of the register AX. In step S12, the data of the register AL is written in the I / O address of the selected printer control register 50.

As described above, in order to transfer the print data from the personal computer to the printer using the Centronics interface (not shown), the CPU 12 needs to execute each of the instructions of steps S1 to S12, and therefore, about 14 bytes per byte. [Μs] is required. Next, a printing device using an LED printer as a printer will be described.

FIG. 8 is a block diagram of a printer in a conventional printing apparatus. In the figure, the printer is a control unit 61.
And a printer engine unit 62, both of which constitute a video interface, a video signal line 63, a command
The status signal line 64 and the operation panel signal line 67 are connected to each other. The control unit 61 is controlled by the CPU 65, and a control program therefor is stored in the ROM 66. Further, 68 is an interface unit for connecting a personal computer (not shown) to the printer, and 69 is a printer interface for outputting print data as a video signal to the printer engine unit 62.

Reference numeral 71 is a large-capacity RAM for storing print data transferred as a printer output data signal IF DATA of a raster image for printing. In the personal computer, the print data is expanded into a raster image, transferred to the printer as a printer output data signal IF DATA, received by the interface unit 68, and before the printing is started, the large capacity RAM 7
Written to 1.

On the other hand, the printer engine section 62 includes a paper cassette 73, an electrophotographic process unit 74, a paper stacker 75, a paper transport unit 76, a DC power supply 77,
Operation panel 78 and electrophotographic process unit 74
And a mechanical control board 79 for controlling the paper transport unit 76. The electrophotographic process unit 74 includes the drum unit 381 and the LED head 38.
2, developing device 383, transfer charger 384, and thermal fixing device 85
And the drum unit 381 includes a primary charger 38.
6, photoconductor drum 387 and cleaning unit 38
It consists of eight.

The CPU 65 of the control unit 61 transmits various signals to and from the printer engine unit 62, receives the status sent from the printer engine unit 62, and sends the status to the operation panel 78. The LED lamp (not shown) is turned on or off. When the operator of the printer depresses a push button switch (not shown) on the operation panel 78 to change the setting function of the printer, the CPU 65 reads the information and sends the command to the printer engine unit 62 as a command / status signal.

Next, the operation of the video interface will be described. FIG. 9 is a timing chart of a video interface in a conventional printing apparatus. In the parentheses below each signal in the figure, the CU indicates the control unit 61 side and PU
Indicates the printer engine unit 62 side, and the arrows indicate the transmission direction of each signal. In the figure, PRINT-N is the control unit 6
1 is a signal for instructing the printer engine unit 62 to start printing, PRDY-N is a signal indicating whether or not the printer engine unit 62 can start printing, and FSYN
C-N is a sub-scanning synchronizing signal, LSYNC-N is a main-scanning synchronizing signal, WDATA-N is a video data signal indicating the presence or absence of print dots, and LGATE-N is the video data signal WD.
Gate signal indicating the valid range of ATA-N, WCLK-
N is a video clock signal.

The resolution of the printer (not shown) is 3
00 [DPI] and the number of dots in the main scanning direction is 256.
The numerical values of the timing of each signal when it is 0 are as follows. That is, the cycle of printing one line is 1600.
[Μs], and the amount of print data for one line is 2560/8 = 320 [bytes]. Therefore, 1 of the print data in the printer
The average value of the processing time per byte is 1600 [μs] / 320 [bytes] = 5 [μs / byte].

On the other hand, since the processing time per byte for transferring the print data to the printer by the personal computer (not shown) via the Centronics interface (not shown) is at least about 14 [μs] as described above, the print data by the printer is The consumption speed of is higher than the transfer speed of the print data by the personal computer. Therefore, large capacity RAM7
1 (FIG. 8) has a capacity corresponding to one page of paper (not shown), most of the transferred print data is stored in the large capacity RAM 71 before printing is started, and during printing. The overrun is prevented.

Next, the connection between the control unit 61 and the printer engine unit 62 in the printer of the conventional printing apparatus will be described. FIG. 10 is a connection state diagram of a signal line between a control unit and a printer engine unit in a printer of a conventional printing apparatus, and FIG. 11 is a command and status time between the control unit and the printer engine unit in a printer of the conventional printing apparatus. It is a chart. In the parentheses of each signal in FIG. 11, CU indicates the control unit 61 side, PU indicates the printer engine unit 62 side, and arrows indicate the transmission direction of each signal.

In FIG. 10, 62 is a printer engine section, 63 is a video signal line, 64 is a command / status signal line, 67 is an operation panel signal line, 69 is a printer interface, 78 is an operation panel, 78a is an operation panel circuit, Reference numeral 79 is a mechanical control board, 79a is an electrophotographic process unit control circuit, and 79b is a command / status transmission / reception control circuit.

The video signal line 63 is a video interface for transferring print data, and the command / status signal line 64 is that the control section 61 (FIG. 8) sends a command to the printer engine section 62, and the printer engine section 62. Command for sending status to control unit 61.
The status interface, and the operation panel signal line 67 constitutes an operation panel interface for controlling lighting and extinction of an LED lamp (not shown) of the operation panel 78 and reading of switch information.

Here, the signal CPRDY becomes high level when the control section 61 becomes communicable, and the signal PPRDY becomes high level when the printer engine section 62 becomes communicable. In this state, when the control unit 61 sends a command to the printer engine unit 62, the control unit 6
1 sets the signal CBSY-N to low level. On the other hand, the printer engine unit 62 generates an 8-pulse clock signal SCLK-N and sends it to the control unit 61, and serializes the command as a command / status signal SC-N in synchronization with the clock signal SCLK-N. To receive.

On the other hand, when the control section 61 finishes transmitting the command / status signal SC-N, it outputs the signal CBSY-.
Set N to high level. When the printer engine section 62 receives the command / status signal SC-N, the printer engine section 62 sends a signal S for sending the status for the command to the control section 61.
BSY-N is set to a low level, an 8-pulse clock signal SCLK-N is generated and sent to the control unit 61, and the status is commanded in synchronization with the clock signal SCLK-N.
It is sent serially as a status signal SC-N.

On the other hand, the printer engine section 62 sets the signal SBSY-N to the high level again when the transmission of the command / status signal SC-N is completed.

[0032]

However, in the above-mentioned conventional printing apparatus, the printer must be provided with a large capacity RAM 71 having a capacity equivalent to about one page of paper, resulting in high cost. I will end up. Further, when printing one page of paper, the printer cannot start printing until print data having a capacity corresponding to almost one page of paper is transferred from the personal computer. Therefore, the time required to print one page of paper is the time required to perform the original printing by the printer, and the time when the print data of a capacity equivalent to about one page of paper is transferred from the personal computer. Will be added, and the print throughput will be low.

Further, the printer has a CPU 1 of a personal computer.
2, CPU 23 independent of RAM 23, ROM 24, etc.
5, ROM 66, large-capacity RAM 71, etc. must be provided, which increases the cost. That is, in order to directly control the printer engine unit 62 of the printer by the personal computer, it is necessary to synchronize the timing specifications of the video interface, the command / status interface, the operation panel interface, etc., and the number of signal lines for that is the standard of the personal computer. The number of signal lines included in the Centronics interface is larger than the number of signal lines. Therefore, the printer's CPU12 and RAM of the personal computer
23, ROM 24, etc. independent CPU 65, ROM 6
6. A large-capacity RAM 71 and the like are provided to control the printer engine unit 62. Therefore, the cost becomes high.

The present invention solves the problems of the conventional printing apparatus, and provides a printing apparatus which can simplify the control unit of the printer to reduce the cost and increase the printing throughput. With the goal.

[0035]

To this end, the printing apparatus of the present invention comprises a personal computer and a printer connected via a Centronics interface, and transfer means for transferring a printer output data signal from the personal computer to the printer for each word. A write control circuit for generating a write control signal based on selected bit data of the transferred printer output data signals, and the rest of the printer output data signals by the write control signal. And a memory into which the data of the bits are written.

Then, it has a read control circuit for generating a read control signal asynchronous with the write control signal to read data from the memory, and means for transferring the read data to the printer engine section. Further, in another printing apparatus of the present invention, it comprises a personal computer and a printer connected via a Centronics interface, and a transfer means for block-transferring a plurality of words of printer output data signals from the personal computer to the printer, and a block transfer. A write control circuit for generating a write control signal based on the selected bit data of each printer output data signal, and the remaining bit data of each printer output data signal according to the write control signal. And a memory in which is written.

Then, a read control circuit for generating a read control signal asynchronous with the write control signal to read the data from the memory, a means for transferring the read data to the printer engine section, and a memory for storing the read data in the memory. And a means for sending a data amount instruction signal indicating the amount of the generated data to the transfer means. In this case, the transfer means performs block transfer of the printer output data signal in response to the data amount instruction signal.

Further, in still another printing apparatus of the present invention, it comprises a personal computer and a printer connected via a Centronics interface, and a transfer means for block-transferring a plurality of words of printer output data signals from the personal computer to the printer. , A write control circuit for generating a write control signal based on a printer control signal sent from a personal computer, and a memory for receiving each printer output data signal.

Then, a read control circuit for generating a read control signal asynchronous with the write control signal and reading data from the memory, a means for transferring the read data to the printer engine unit, and a memory for storing in the memory. And a means for sending a data amount instruction signal indicating the amount of the generated data to the transfer means. In this case, the transfer means performs block transfer of the printer output data signal in response to the data amount instruction signal.

Further, another printing apparatus of the present invention also has a command / status control circuit for serially transmitting the command / status interface signal and the operation panel interface signal between the personal computer and the printer.

[0041]

According to the present invention, as described above, the printing apparatus comprises the personal computer and the printer connected via the Centronics interface, and the transfer means for transferring the printer output data signal for each word from the personal computer to the printer. A write control circuit for generating a write control signal based on the selected bit data of each transferred printer output data signal, and the remaining bits of each printer output data signal according to the write control signal. And a memory in which the data of

Therefore, when the printer output data signal is transferred word by word from the personal computer to the printer, the write control signal is generated based on the selected bit data of the transferred printer output data signals. Therefore, the remaining bit data can be written in the memory without sending another signal such as a strobe pulse signal from the personal computer to the printer.

Then, it has a read control circuit for generating a read control signal asynchronous with the write control signal to read data from the memory, and means for transferring the read data to the printer engine section. The printer engine unit prints according to the transferred data. Further, in another printing apparatus of the present invention, it comprises a personal computer and a printer connected via a Centronics interface, and a transfer means for block-transferring a plurality of words of printer output data signals from the personal computer to the printer, and a block transfer. A write control circuit for generating a write control signal based on the selected bit data of each printer output data signal, and the remaining bit data of each printer output data signal according to the write control signal. And a memory in which is written.

In this case, since the printer output data signal for a plurality of words is block-transferred from the personal computer to the printer, it is not necessary to transfer it for each word. Further, since the write control signal is generated based on the selected bit data of the transferred printer output data signals, it is possible to send other signals such as strobe pulse signals from the personal computer to the printer. The remaining bits of data can be written to memory.

Then, a read control circuit for generating a read control signal asynchronous with the write control signal to read data from the memory, a means for transferring the read data to the printer engine section, and a storage for storing in the memory. And a means for sending a data amount instruction signal indicating the amount of the generated data to the transfer means. In this case, the transfer means performs block transfer of the printer output data signal in response to the data amount instruction signal.

Therefore, when the data stored in the memory is read out and the data amount becomes small, the data amount instruction signal is sent to the transfer means, and the transfer means corresponds to the data amount instruction signal and outputs a plurality of words. Block transfer of the printer output data signal of from the personal computer to the printer. Also,
In still another printing apparatus of the present invention, it comprises a personal computer and a printer connected through a Centronics interface, and a transfer means for transferring the printer output data signals for a plurality of words from the personal computer to the printer in a block manner, and a transfer means for transmitting from the personal computer. And a write control circuit for generating a write control signal based on the printer control signal, and a memory for receiving each printer output data signal.

In this case, since the printer output data signal for a plurality of words is block-transferred from the personal computer to the printer, it is not necessary to transfer it for each word. A read control circuit for generating a read control signal asynchronous with the write control signal to read data from the memory; and means for transferring the read data to the printer engine unit.
And a means for sending a data amount instruction signal indicating the amount of data stored in the memory to the transfer means. in this case,
The transfer means performs block transfer of the printer output data signal in response to the data amount instruction signal.

Therefore, when the data stored in the memory is read and the data amount becomes small, the data amount instruction signal is sent to the transfer means, and the transfer means responds to the data amount instruction signal by a plurality of words. Block transfer of the printer output data signal of from the personal computer to the printer. Also,
Still another printing apparatus of the present invention also has a command / status control circuit for serially transmitting the command / status interface signal and the operation panel interface signal between the personal computer and the printer.

In this case, since the processing time for transferring the printer output data signal can be shortened, the time can be used for transmitting the command / status interface signal and the operation panel interface signal. Therefore, the printer engine unit can be directly controlled by the personal computer. Moreover, since the command / status interface signal and the operation panel interface signal are transmitted serially, it is not necessary to increase the number of signal lines of the Centronics interface.

[0050]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a block diagram of a printing apparatus showing a first embodiment of the present invention. In the figure, 81 is a personal computer, 82 is a printer, and 83 is a Centronics interface for connecting the personal computer 81 and the printer 82. Since the structure of the personal computer 81 is the same as the conventional one, the description thereof will be omitted with reference to FIG.

The 1-byte print data transferred from the personal computer 81 to the printer 82 via the Centronics interface 83 is input to the buffer circuit 84 as an 8-bit printer output data signal IF DATA,
7-bit data among them is signals DATA6 to DATA
0 is written in the first-in first-out memory (hereinafter referred to as “FIFO memory”) 86.
The 7-bit data read from the FIFO memory 86 is sent to the shift register circuit 88 as signals DATA6 to DATA0, and the shift register circuit 88
Is converted into serial data and is transferred to the printer engine unit 62 as a video data signal WDATA-N via a flip-flop circuit (not shown).

Reference numerals 89 and 90 transmit various signals between the buffer circuit, the personal computer 81 and the printer engine unit 62 via the Centronics interface 83.
Then, 92 receives 1-bit data from the buffer circuit 84 as a signal DATA7, and the FIFO memory 86 receives 7-bit data.
A write control circuit for generating a write control signal W-N for writing bit data, 91 is the printer engine unit 6
2 is a read control circuit for receiving a signal sent from the memory 2 and generating a read control signal RN for reading 7-bit data of the FIFO memory 86. In addition, HF-N is a half full signal as a data amount instruction signal, and RS-N is a reset signal.

As described above, in the conventional printing apparatus, when 1 byte of print data is transferred from the personal computer 81 to the printer 82, the printer output data signal IF D
After transferring ATA, strobe pulse signal STRO
It is necessary to send BE-N, and the CPU 12 of the personal computer 81
There are many instructions by. On the other hand, in this embodiment, when 1 byte of print data is transferred from the personal computer 81 to the printer 82, the printer output data signal IFD
7-bit data of ATA is converted to signals DATA6 to D
ATA0 is sent to the shift register circuit 88 and 1-bit data is sent to the write control circuit 92 as the signal DATA7 to generate the write control signal W-N. Therefore, the signals DATA6 to DATA0 can be written in the FIFO memory 86 by using the write control signal W-N. In this case, the CPU of the personal computer 81
Since 12 only needs to transfer the printer output data signal IF DATA, the number of instructions can be reduced.

FIG. 12 shows F in the first embodiment of the present invention.
It is an internal block diagram of an IFO memory. In the figure, 8
6 is a FIFO memory, 93 is a memory cell array composed of RAM, and the memory cell array 93 is a signal DATA.
It has a capacity capable of storing 7192 bits of data per word input as 6 to DATA0 for 8192 words. Further, 94 is a write pointer that generates an address of the memory cell array 93 when writing 7-bit data, and 95 is a read pointer that generates an address of the memory cell array 93 when reading 7-bit data.

Further, 97 is a write control device for receiving the write control signal W-N and controlling the write pointer 94, 9
The read pointer 9 receives the read control signal RN.
5, a read control device for controlling 5 and 99 a flag signal circuit. The flag signal circuit 99 determines the amount of data stored in the memory cell array 93, that is, the write pointer 94.
And a value of the read pointer 95 is more than half of 8192 (4096 or more), a half full signal HF-N is generated.

Further, 101 is a buffer circuit which comprises 7 three-state buffers and outputs 7-bit data, and 102 is a write pointer 94, a read pointer 95 and a flag signal circuit 99 inside the FIFO memory 86.
Is a reset logic circuit for initializing. The reset logic circuit 102 generates a reset signal RS-N.

FIG. 13 shows F in the first embodiment of the present invention.
It is a figure which shows an IFO memory and a shift register circuit.
In the figure, 86 is a FIFO memory, and 88 is a 7-bit shift register circuit. The shift register circuit 88
Is a terminal D ₆ to which signals DATA ₆ to DATA 0 are input.
D ₀ , a terminal Q for converting the input signals DATA 6 to DATA ₀ into serial data and outputting the data, a shift register circuit 8
Terminal S / for switching the operation by loading or shifting the signals DATA6 to DATA0 sent to
L, and a terminal CLR for resetting an internal flip-flop circuit (not shown).

Further, 105 is a flip-flop circuit, 1
Reference numeral 06 is an inverter circuit. W-N is a write control signal sent from the write control circuit 92 (FIG. 1), RN
Is a read control signal sent from the read control circuit 91, RS-
N is a reset signal of the FIFO memory 86, and the reset signal RS-N is the Centronics interface 83.
From the buffer circuit 89. The half-full signal HF-N is input to the buffer circuit 90 of the Centronics interface 83 as shown in FIG.
The half-full signal HF-N can be directly read on the No. 1 side.

Further, the flip-flop circuit 105
Delays the serial data of the shift register circuit 88 by half a clock and transfers it to the printer engine unit 62 as a video data signal WDATA-N. In addition, LSYNC
-N is a main scanning synchronization signal, and WCLK-N is a video clock signal. FIG. 14 is a block diagram of a write control circuit according to the first embodiment of the present invention.

In the figure, 92 is a write control circuit, and 110
Is a flip-flop circuit that operates as a shift register, and 111 is an EX-OR circuit. The 1-bit signal DATA7 among the 8-bit signals DATA7 to DATA0 input to the printer 82 via the Centronics interface 83 (FIG. 1) is input to the flip-flop circuit 110 through the buffer circuit 84. The input terminal of the EX-OR circuit 111 is connected to the second and third stages of the flip-flop circuit 110, and the write control signal W-N is output from the output terminal. The write control signal W-N generates a negative logic pulse each time the signal DATA7 changes between a high level and a low level.

CLK is a clock signal, which is sent from a clock oscillation circuit (not shown). FIG. 15 is a block diagram of a read control circuit according to the first embodiment of the present invention. In the figure, 91 is a read control circuit, 115 is a 4-bit count circuit, and the count circuit 115 has 4-bit data input terminals A to D, a load terminal LD, a count operation enable input terminal T, and a carry signal output. It has a terminal CY. Further, 116 is a flip-flop circuit, 117 and 118 are inverter circuits, and 120 is an AND.
Circuit, 121 is an OR circuit, and HL is a high-level signal.

The count circuit 115 has a main scanning synchronizing signal LSY sent from the printer engine unit 62 (FIG. 1).
After the initial data is loaded by NC-N, the count operation is performed in synchronization with the video clock signal WCLK-N while the gate signal LGATE-N is at the low level. The count value of the count circuit 115 is expressed in hexadecimal notation FH, 9H, AH, BH, CH, DH, EH, F.
H, 9H, AH, ..., and the video clock signal WC
A carry signal is generated every 7 clocks of LK-N. This carry signal is applied to the flip-flop circuit 116.
The read control signal RN is generated by delaying by 1 clock at. Note that FSYNC-N is a sub-scanning synchronization signal.

FIG. 16 is a timing chart of the write control circuit according to the first embodiment of the present invention. The printer output data signal IF DATA (FIG. 1) is sent to the printer 82 via the Centronics interface 83, becomes signals DATA6 to DATA0 via the buffer circuit 84, and is sent to the FIFO memory 86. The 7-bit signals DATA6 to DATA0 set the 7-bit data a, b, c, ... And the remaining 1-bit signal DA.
TA7 sets 1-bit data which is alternately inverted such as "1", "0", "1", .... And
The write control circuit 92 generates a write control signal W-N based on the signal DATA7, and the data a, b, c, ... Are written in the FIFO memory 86 by the write control signal W-N.

Numerals 1Q to 3Q are outputs of the terminals 1Q, 2Q and 3Q of the respective stages of the flip-flop circuit 110 (FIG. 14), and 3Q-N are inverted outputs of the terminal 3Q. On the other hand, the read control circuit 91 operates asynchronously with the write control circuit 92, and stores the data a, b, and the data stored in the FIFO memory 86.
c, ... Are read in order. That is, the read control circuit 91 reads the data a, loads it in parallel to the shift register circuit 88, serializes it in order from MSB, and transfers it to the printer engine unit 62. Then, when the LSB is transferred to the printer engine unit 62, the next data b is
It is read from the IFO memory 86 and processed in the same manner. CLK is a clock signal.

FIG. 17 is a timing chart of the half-full signal in the first embodiment of the present invention. As described above, the capacity of the FIFO memory 86 (FIG. 1) is 8192 words. Here, the data a,
.. (FIG. 16) are written and the amount of stored data a, b, c, ... Exceeds 4096 words, the half full signal HF-N becomes low level. At this time, F
The amount of data a, b, c, ... Stored in the IFO memory 86 is 4097 words.

On the other hand, data a from the FIFO memory 86,
When b, c, ... Are read and the amount of data a, b, c, ... Stored in the FIFO memory 86 becomes 4096 words or less, the half full signal HF-N becomes high level. Since the signal line of the Centronics interface 83 can send the half-full signal HF-N, the CPU 12 (see FIG. 2) of the personal computer 81 reads the half-full signal HF-N to the printer 82. It is possible to determine whether or not the print data can be transferred.

Therefore, when the CPU 12 of the personal computer 81 finds that the half-full signal HF-N is at the high level, it outputs the 8-bit print data to the Centronics interface 83 in a burst form for 4096 bytes at a time, and sends it to the Centronics interface 83. It can be transferred to the printer 82 via the interface 83. On the other hand, when the half-full signal HF-N is low level, the CPU 12 of the personal computer 81 waits until the half-full signal HF-N becomes high level.

As described above, since the personal computer 81 does not need to write the print data to the data latch register 49 (see FIG. 3) every time one byte of print data is transferred, the number of commands can be reduced. Note that W-N is a write control signal and RN is a read control signal. FIG. 18 is a flow chart when the print data is block-transferred in the first embodiment of the present invention.

In this case, the CPU of the personal computer 81 (FIG. 1)
12 (see FIG. 2) writes the print data to be transferred to the printer 82 in the RAM 23. At this time, data corresponding to the signals DATA6 to DATA0 is stored in 7 bits of the 1-byte memory, and "0" is stored in the remaining 1 bit.
Data that is alternately inverted, such as "1", "0", "1", ... Is stored. In step S21, the upper address of the 4096-byte memory block of the RAM 23 is acquired by the upper program. In step S22, the start address is written in the register SI (see FIG. 6). In step S23, the I / O address of the data latch register 49 (see FIG. 3) is written in the register DX. In step S24, the number of bytes of print data to be transferred in blocks (initial value: 4096) is written in the register CX. Step S25A RAM 23 indicated by register SI
Print data is written in the data latch register 49 indicated by the register DX. Step S25B The head address of the register SI is incremented and the byte number of the register CX is decremented. Step S25C: It is judged whether or not the number of bytes of the register CX becomes 0. If the number of bytes has become 0, the process is terminated, and if the number of bytes has not become 0, the process returns to step S25A.

The CPU 12 executes steps S25A to S25C.
Is executed in one step as a string transfer instruction provided in the firmware (not shown) and does not involve instruction fetch. Therefore, the processing time for transferring print data is short, and it takes about 1.2 bytes per byte.
[Μs]. Here, the transfer speed of the print data by the personal computer 81 and the consumption speed of the print data by the printer 82 are compared.

The transfer rate of the print data of the personal computer 81 is (7/8) [byte] /1.2 [μs] ≈0.73 [byte / μs] ≈5.8 [bit / μs], while As for the consumption rate of print data by the printer 82, the print cycle of one line in the printer engine unit 62 is 1600 [μs], the number of print dots per line is 2560 dots, and the data amount is 320 bytes. Therefore, 320 [bytes] / 1600 [μs] = 0.2 [bytes / μs] = 1.6 [bits / μs].

Therefore, since the transfer rate of the print data by the personal computer 81 is sufficiently higher than the consumption rate of the print data by the printer 82, only the FIFO memory 86 is required as the internal memory of the printer 82 and the large capacity RAM is provided. No need. Next, a second embodiment of the present invention will be described. FIG. 19 is a block diagram of a printing apparatus showing a second embodiment of the present invention.

In the figure, 81 is a personal computer, 82 is a printer, and 83 is a Centronics interface for connecting the personal computer 81 and the printer 82. PC 81 via the Centronics interface 83
The 1-byte print data transferred from the printer 82 to the printer 82 is input to the buffer circuit 84 as an 8-bit printer output data signal IF DATA, and the buffer circuit 8
The 8-bit data output from 4 is signal DATA7-
It is written to the FIFO memory 186 as DATA0. Then, the 8-bit data read from the FIFO memory 186 is sent to the shift register circuit 188 as signals DATA7 to DATA0, converted into serial data in the shift register circuit 188, and converted into video data via a flip-flop circuit (not shown). Signal WDA
It is transferred to the printer engine unit 62 as TA-N.

Reference numerals 89 and 90 are buffer circuits,
Various signals are transmitted between the personal computer 81 and the printer engine unit 62 via the Centronics interface 83. Then, 192 receives a strobe pulse signal STROBE-N as a printer control signal from the personal computer 81 via the Centronics interface 83 and the buffer circuit 89, and a write control signal W-N for writing 8-bit data in the FIFO memory 186. 191 is a write control circuit for receiving the signal sent from the printer engine unit 62,
Read control signal R for reading 6-bit 8-bit data
It is a read control circuit for generating -N. In addition, HF-N
Is a half-full signal as a data amount instruction signal, RS-N
Is a reset signal.

FIG. 20 shows F in the second embodiment of the present invention.
It is an internal block diagram of an IFO memory. In the figure, 1
86 is a FIFO memory, 193 is a memory cell array composed of RAM, and the memory cell array 193 is a signal D.
It has a capacity capable of storing 8192 words of 8-bit data per word input as ATA7 to DATA0. Further, 94 is a write pointer for generating an address of the memory cell array 193 when writing 8-bit data, and 95 is a read pointer for generating an address of the memory cell array 193 when reading 8-bit data.

Further, 97 is a write control device for receiving the write control signal W-N and controlling the write pointer 94, 9
The read pointer 9 receives the read control signal RN.
5, a read control device for controlling 5 and 99 a flag signal circuit. The flag signal circuit 99 determines the amount of data stored in the memory cell array 193, that is, the write pointer 9
A half full signal HF-N indicating whether or not the difference between the value of 4 and the value of the read pointer 95 is half of 8192 or more (4096 or more) is generated.

Further, 101 is a buffer circuit which comprises eight three-state buffers and outputs 8-bit data, and 102 is a write pointer 94, a read pointer 95 and a flag signal circuit 9 inside the FIFO memory 186.
9 is a reset logic circuit for initializing 9. The reset logic circuit 102 generates a reset signal RS-N.

FIG. 21 shows F in the second embodiment of the present invention.
It is a figure which shows an IFO memory and a shift register circuit.
In the figure, 186 is a FIFO memory and 188 is an 8-bit shift register circuit. The shift register circuit 188 has terminals D _{7 to} D ₀ to which signals DATA 7 to DATA ₀ are input, a terminal Q for converting the input signals DATA 7 to DATA ₀ into serial data, and outputs the signals DATA 7 to DATA _{0 to} the shift register circuit 188. Is provided with a terminal S / L for switching the operation by loading or shifting, and a terminal CLR for resetting an internal flip-flop circuit (not shown).

Further, 105 is a flip-flop circuit, 1
Reference numeral 06 is an inverter circuit. W-N is a write control signal sent from the write control circuit 192 (FIG. 19), R
-N is a read control signal sent from the read control circuit 191;
RS-N is a reset signal of the FIFO memory 186, and the reset signal RS-N is sent from the buffer circuit 89 of the Centronics interface 83. Further, the half-full signal HF-N is input to the buffer circuit 90 of the Centronics interface 83 as shown in FIG. 19, and the half-full signal HF-N can be directly read by the personal computer 81 side.

Further, the flip-flop circuit 105
Delays the serial data of the shift register circuit 188 by half a clock and transfers it to the printer engine unit 62 as a video data signal WDATA-N. In addition, LSYN
C-N is a main scanning synchronization signal, and WCLK-N is a video clock signal. FIG. 22 is a block diagram of a write control circuit according to the second embodiment of the present invention.

In the figure, 192 is a write control circuit, and 11
Reference numeral 10 is a flip-flop circuit that operates as a shift register, and 111 is an EX-OR circuit. Printer 8 via the Centronics interface 83 (FIG. 19)
2 input strobe pulse signal STROBE-N
Is the flip-flop circuit 1 via the buffer circuit 89.
Sent to 110. Then, the EX-OR circuit 111
Is connected to the second and third stages of the flip-flop circuit 1110, and the write control signal W-N is output from the output terminal.
Is output. The write control signal W-N generates a negative logic pulse each time the strobe pulse signal STROBE-N changes between high level and low level.

CLK is a clock signal, which is sent from a clock oscillation circuit (not shown). FIG. 23 is a block diagram of a read control circuit according to the second embodiment of the present invention. In the figure, 191 is a read control circuit and 1115 is 4
A bit counting circuit, and the counting circuit 1115
Is a 4-bit data input terminal A to D, a load terminal LD,
It has an enable input terminal T for counting operation and a carry signal output terminal CY. Further, 116 is a flip-flop circuit, 117 and 118 are inverter circuits, 120 is an AND circuit, 121 is an OR circuit, and HL is a high level signal.

The count circuit 1115 has a main scanning synchronizing signal L sent from the printer engine unit 62 (FIG. 19).
After the initial data is loaded by SYNC-N, while the gate signal LGATE-N is at low level, the counting operation is performed in synchronization with the video clock signal WCLK-N. The count value of the count circuit 1115 is expressed in hexadecimal notation as 8H, 9H, AH, BH, CH, DH,
A transition is made to EH, FH, 8H, 9H, ... And a carry signal is generated every eight clocks of the video clock signal WCLK-N. By delaying this carry signal by one clock in flip-flop circuit 116, read control signal RN is generated. In addition, FSYN
C-N is a sub-scanning synchronization signal.

FIG. 24 is a timing chart of the write control circuit according to the second embodiment of the present invention. The printer output data signal IF DATA (FIG. 19) is sent to the printer 82 via the Centronics interface 83, becomes signals DATA7 to DATA0 via the buffer circuit 84, and is sent to the FIFO memory 186. 8-bit data a, b, c, ... Is set by the 8-bit signals DATA7 to DATA0. And each data a,
Strobe pulse signal STRO corresponding to b, c, ...
BE-N sets 1-bit data that is alternately inverted such as "1", "0", "1", .... Then, the write control circuit 192 generates the write control signal W-N based on the strobe pulse signal STROBE-N,
The data a, b, c, ... Are written in the FIFO memory 186 by the write control signal W-N.

1Q to 3Q are terminals 1Q, 2Q, 3Q of the respective stages of the flip-flop circuit 1110 (FIG. 22).
3Q-N is an inverted output of the terminal 3Q. on the other hand,
The read control circuit 191 operates asynchronously with the write control circuit 192, and sequentially reads the data a, b, c, ... Stored in the FIFO memory 186. That is, the read control circuit 191 reads out the data a and shifts the shift register circuit 1
The data is loaded into 88 in parallel, serialized from the MSB, and transferred to the printer engine unit 62. Then, when the LSB is transferred to the printer engine unit 62, the next data b is read from the FIFO memory 186 and processed in the same manner.

By the way, as described above, the capacity of the FIFO memory 186 is 8192 words. Where FI
Write the data a, b, c, ... In the FO memory 186,
When the amount of the stored data a, b, c, ... Exceeds 4096 words, as shown in FIG.
-N goes low. At this time, the FIFO memory 18
The amount of data a, b, c, ... Stored in 6 is 4097 words.

On the other hand, when the data a, b, c, ... Are read from the FIFO memory 186 and the amount of the data a, b, c, ... Stored in the FIFO memory 186 becomes 4096 words or less, the half full signal HF-N is output. Become high level. Since the signal line of the Centronics interface 83 can send the half-full signal HF-N, the CPU 12 (see FIG. 2) of the personal computer 81 reads the half-full signal HF-N to the printer 82. It is possible to determine whether or not the print data can be transferred.

Therefore, when the CPU 12 of the personal computer 81 finds that the half-full signal HF-N is at a high level, it outputs batch print data of 8 bits to the Centronics interface 83 in a burst form for 4096 bytes, and sends the data to the Centronics interface. It can be transferred to the interface 83. On the other hand, the half full signal HF
-N is low level, the half full signal HF-N
The CPU 12 of the personal computer 81 waits until the signal goes high.

As described above, since the personal computer 81 does not have to write the print data to the data latch register 49 (see FIG. 3) every time one byte of print data is transferred, the number of instructions can be reduced. FIG. 25 is a flow chart for block-transferring print data in the second embodiment of the present invention. In step S31, the start address of the 4096-byte memory block in the RAM 23 (see FIG. 2) is acquired by the upper program. In step S32, the start address is written in the register SI (see FIG. 6). Step S33 The I / O address of the data latch register 49 (see FIG. 3) is written in the register DX. Step S34 Centronics interface 83
I / O of the printer control register 50 for controlling the strobe pulse signal line (not shown) of FIG. 19
Write the address to register BX. Step S35 Strobe pulse signal STROBE-
Data for setting high level to N is stored in register AH
And one of the registers AL, and the data for setting the strobe pulse signal STROBE-N to the low level is written to the other. Step S36-i (i = 1, 2, ..., 4096) Transfers 1-byte print data to the printer 82. This is repeated 4096 times continuously.

FIG. 26 is a flow chart for transferring 1-byte print data during block transfer in the second embodiment of the present invention. Step S36-i-1A Register SI (see FIG. 6)
The print data of the RAM 23 (see FIG. 2) indicated by is written in the data latch register 49 (see FIG. 3) indicated by the register DX. Step S36-i-1B The start address of the register SI is incremented for the next access.

Incidentally, steps S36-i-1A and S36
-I-1B is executed as a string transfer instruction of the CPU 12 in one step. Step S36-i-2 The data in the register DX and the data in the register BX are exchanged. As a result, the I / O address of the printer control register 50 is set to the register D.
Since it is written in X, the strobe pulse signal line (not shown) can be controlled. Step S36-i-3 The data of the register AL is written in the printer control register 50. Step S36-i-4 Strobe pulse signal STR
The data in the register AH and the data in the register AL are exchanged to change the high level setting and the low level setting of the OBE-N. Step S36-i-5 The data of the register DX and the data of the register BX are exchanged.

Incidentally, steps S36-i-4 to S36-
i-5 is for preparing to transfer the next 1-byte print data. Steps S36-i-1A to S3
The processing time for transferring 1-byte print data in 6-i-5 is about 3 [μs] per byte. Here, the transfer speed of the print data by the personal computer 81 and the consumption speed of the print data by the printer 82 are compared.

The transfer speed of the print data of the personal computer 81 is 1 [byte] / 3 [μs] ≈0.33 [byte / μs]
≈2.66 [bits / μs], while the print data consumption speed by the printer 82 is such that the printing cycle of one line in the printer engine unit 62 is 1600 [μs] and the number of print dots per line. Since there are 2560 dots and the amount of data is 320 bytes, 320 [bytes] / 1600 [μs] = 0.2 [bytes / μs] = 1.6 [bits / μs].

Therefore, since the transfer rate of the print data by the personal computer 81 is sufficiently higher than the consumption rate of the print data by the printer 82, only the FIFO memory 86 is required as the memory inside the printer 82, and the large capacity RAM is provided. No need. Next, a third embodiment of the present invention will be described. FIG. 27 is a block diagram of a printing apparatus showing a third embodiment of the present invention.

In the figure, 81 is a personal computer, 82 is a printer, and 83 is a Centronics interface for connecting the personal computer 81 and the printer 82. PC 81 via the Centronics interface 83
The 1-byte print data transferred from the printer 82 to the printer 82 is input to the buffer circuit 84 as an 8-bit printer output data signal IF DATA, and the buffer circuit 8
The 8-bit data output from 4 is signal DATA7-
It is written to the FIFO memory 186 as DATA0. Then, the 8-bit data read from the FIFO memory 186 is sent to the shift register circuit 188 as signals DATA7 to DATA0, converted into serial data in the shift register circuit 188, and converted into video data via a flip-flop circuit (not shown). Signal WDA
It is transferred to the printer engine unit 62 as TA-N.

Further, 89 and 90 are buffer circuits,
Various signals are transmitted between the personal computer 81 and the printer engine unit 62 via the Centronics interface 83. A read control circuit 191 receives a signal sent from the printer engine unit 62 and generates a read control signal RN for reading 8-bit data of the FIFO memory 186. A command / status control circuit 201 controls commands and status, and transmits command / status interface signals and operation panel interface signals of the printer engine unit 62 to and from the personal computer 81 via the Centronics interface 83. . Note that W-N is a write control signal, HF-N is a half-full signal as a data amount instruction signal, and RS-N is a reset signal.

Since the structures of the FIFO memory 186, shift register circuit 188 and read control circuit 191 are the same as those in the second embodiment, the description thereof will be omitted by referring to FIGS. FIG. 28 is a timing chart of write control of the FIFO memory according to the third embodiment of the present invention.

Printer output data signal IF DATA
27 (FIG. 27) is sent to the printer 82 via the Centronics interface 83, becomes signals DATA7 to DATA0 via the buffer circuit 84, and the FIFO memory 18
Sent to 6. This 8-bit signal DATA7 to DAT
8-bit data a, b, c, ... Is set by A0. Then, one pulse is input to the strobe pulse signal STROBE-N via the Centronics interface 83 in correspondence with each data a, b, c ,.
The FO memory 186 uses the strobe pulse signal STROBE.
The write control signal W-N is generated based on -N, and the data a, b, c, ... Are written in the FIFO memory 186 by the write control signal W-N.

On the other hand, the read control circuit 191 operates at the timing asynchronous with the timing of the write control signal W-N, and the data a, b, and the data stored in the FIFO memory 186 are stored.
c, ... Are read in order. That is, the read control circuit 191
Reads the data a, loads it in parallel to the shift register circuit 188, serializes it from MSB in order, and transfers it to the printer engine unit 62. And LS
When B is transferred to the printer engine unit 62, the next data b is read from the FIFO memory 186 and processed in the same manner.

By the way, as described above, the capacity of the FIFO memory 186 is 8192 words. Where FI
Write the data a, b, c, ... In the FO memory 186,
When the amount of the stored data a, b, c, ... Exceeds 4096 words, as shown in FIG.
-N goes low. At this time, the FIFO memory 18
The amount of data a, b, c, ... Stored in 6 is 4097 words.

On the other hand, when the data a, b, c, ... Are read from the FIFO memory 186 and the amount of the data a, b, c, ... Stored in the FIFO memory 186 becomes 4096 words or less, the half full signal HF-N is output. Become high level. Since the signal line of the Centronics interface 83 can transfer the half full signal HF-N, the CPU 12 of the personal computer 81 (see FIG. 2).
By referring to the half full signal HF-N, it is possible to determine whether or not the print data can be transferred to the printer 82.

Therefore, when the CPU 12 of the personal computer 81 finds that the half-full signal HF-N is at the high level, it outputs the 8-bit print data to the Centronics interface 83 in a burst form for 4096 bytes at a time. It can be transferred to the printer 82 via the interface 83. On the other hand, when the half-full signal HF-N is low level, the CPU 12 of the personal computer 81 waits until the half-full signal HF-N becomes high level.

As described above, since the personal computer 81 does not have to write the print data to the data latch register 49 (see FIG. 3) every time the print data of 1 byte is transferred, the number of commands can be reduced. FIG. 29 is a block diagram of a command / status control circuit according to the third embodiment of the present invention.

In the figure, reference numerals 270 to 273 denote shift register circuits, and the shift register circuit 272 is supplied with data of a predetermined lower number of bits of the shift register circuit 271, for example. Reference numeral 274 is a flip-flop circuit and 275 is a latch circuit. The latch circuit 275 latches, for example, data of a predetermined upper number of bits of the shift register circuit 271, and the output signal of the latch circuit 275 is sent to the printer engine unit 62 and the LED lamp 278a of the operation panel 278. . 279 is an OR circuit having an open collector output circuit, 280 is an inverter circuit, 278b is an operation panel 2
Reference numeral 78 denotes a switch, and 282 denotes a timing control circuit for generating a timing control signal for each part in the command / status control circuit 201.

Here, the command / status signal SC-
N is transmitted to and from the printer engine unit 62, and other control data signals SERIAL CONTROL DA
TA, status data signal SERIAL STATUS
S DATA, clock signal CONTROL DATA
The CLOCK and the load signal LOAD-N are transmitted to the Centronics interface 83 via the buffer circuits 89 and 90 (FIG. 27).

When the personal computer 81 sends a command to the printer engine unit 62, the control data signal SERIAL CONTR is sent to the shift register circuit 271 of the printer 82 via the Centronics interface 83.
OL DATA is sent serially and the clock signal CONT is sent via the Centronics interface 83.
Send ROL DATA CLOCK. In this case, the data transferred from the personal computer 81 to the printer engine unit 62 as the control data signal SERIAL CONTROL DATA at one time is the control data of the printer engine unit 62, the command data corresponding to the turning on and off of the LED lamp 278a of the operation panel 278. And commands.

Then, the personal computer 81 transfers the control data signal SERIAL CONTROLLDATA, and then sends the load signal LOAD-N via the Centronics interface 83, and the shift register circuit 27.
Control data signal within 1 SERIAL CONTROL
While latching DATA in the latch circuit 275,
The remaining bits are transferred to the shift register circuit 272.

In this case, the command to the printer engine unit 62 is transferred to the shift register circuit 272.
On the other hand, the printer engine unit 62 serially transfers the status to the shift register circuit 273, converts the status into parallel data in the shift register circuit 273, and then transfers the data to the shift register circuit 270. Further, the printer engine unit 62 outputs signals PRDY-N, SBSY-N, PPRD.
Y and the printer error signal Error-N are sent directly to the shift register circuit 270 and the operation panel 278
The switch 278b of the signal switches SW1 to S
W4 is directly sent to the shift register circuit 270.

In this case, when the load signal LOAD-N from the personal computer 81 is input to the shift register circuit 270, the signals PRDY-N, SB of the printer engine unit 62 are output.
SY-N, PPRDY, printer error signal Error
-N, signal SW of switch 278b of operation panel 278
1 to SW4 and the status data of the shift register circuit 273 are loaded into the shift register circuit 270 in parallel, and the clock signal CONTR from the personal computer 81.
The status data signal SERIAL STATUS DATA is transferred to the personal computer 81 in synchronization with the OL DATA CLOCK.

FIG. 30 is a block diagram of a shift register circuit according to the third embodiment of the present invention. In the figure, 2
70 and 273 are shift register circuits 280 and 291 to
294 is an inverter circuit, 296 is a NAND circuit, 29
Reference numeral 7 is an OR circuit and 298 is a flip-flop circuit.
The flip-flop circuit 298 has a data input terminal D, an output terminal Q, an input terminal CLR for asynchronously clearing the flip-flop circuit 298, and an input terminal PR for presetting the flip-flop circuit 298.

Reference numerals 301 and 302 denote shift register circuits of 8 bits, each having eight parallel data input terminals A.
To H, an output terminal Q for outputting data converted into parallel / serial data by the shift register circuits 301 and 302, an input terminal SI for inputting serial data, parallel data loading and shift operation of the shift register circuits 301 and 302 Input terminal S for switching
/ L etc.

LOW is a low level signal, HF
-N is a half-full signal output from the FIFO memory 186 (FIG. 27). Further, the signals PRDY-N, S
BSY-N, PPRDY, printer error signal Erro
The r-N, the command / status signal SC-N, and the clock signal SCLK-N are sent from the printer engine unit 62.

The load signal LOAD-N, the clock signal CONTROL DATA CLOCK, and the status data signal SERIAL STATUS DATA are sent to the personal computer 8 via the Centronics interface 83.
1 sent from the CPU 12 of the personal computer 81 (see FIG. 2)
Can directly set or read the logic level.

SW1 to SW4 are operation panels 278.
This is a signal from the four switches 278b (FIG. 29). In the printing apparatus having the above-mentioned configuration, the CP of the personal computer 81
U12 is a half-full signal HF- inside the printer 82.
N, signals PRDY-N, SBSY-N, PPRDY, S
If you want to know the status of W1-SW4, printer error signal Error-N and printer engine 62,
The load signal LOAD-N is sent to the printer 82 via the Centronics interface 83. Thereby, the half-full signal HF-N, the signals PRDY-N, SBSY.
-N, PPRDY, SW1 to SW4, printer error signal Error-N and status are loaded into shift register circuits 301 and 302 and flip-flop circuit 298. Next, the CPU 12 of the personal computer 81 sends the clock signal CONTROL DATA CLOCK to the printer 82 via the Centronics interface 83 one pulse at a time, and the clock signal CONTROL DAT is sent.
A status data signal SERIAL output to the Centronics interface 83 in synchronization with A CLOCK
Read STATUS DATA. In this way, the signal level inside the printer 82 can be known.

On the other hand, the inverter circuit 292, the NAND circuit 296, the OR circuit 297, and the flip-flop circuit 2
The circuit constituted by 98 is the CPU of the personal computer 81.
When 12 sends the signal LOAD-N to the printer 82 through the Centronics interface 83, the half full signal HF-N is directly output to the signal line of the status data signal SERIAL STATUS DATA. Therefore, even when the CPU 12 tries to read the level of the half full signal HF-N, the clock signal CONTR
No need to send OL DATA CLOCK.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention, and they are not excluded from the scope of the present invention.

[0117]

As described in detail above, according to the present invention, the printing apparatus comprises a personal computer and a printer connected via a Centronics interface,
Transfer means for transferring the printer output data signal from the personal computer to the printer for each word; and a write control circuit for generating a write control signal based on the selected bit data of the transferred printer output data signals. , A memory into which data of the remaining bits of each printer output data signal is written by the write control signal.

Therefore, the remaining bit data can be written in the memory without sending another signal such as a strobe pulse signal from the personal computer to the printer, and the transfer speed of the printer output data signal of the personal computer can be changed to the printer output of the printer. It can be higher than the consumption rate of the data signal. As a result, it is not necessary to equip the printer with a large capacity RAM.

Then, it has a read control circuit for generating a read control signal asynchronous with the write control signal and reading data from the memory, and means for transferring the read data to the printer engine section. The printer engine unit prints according to the transferred data. Therefore, the printer engine unit does not need to wait for the printer output data signal to be transferred from the personal computer and written in the large-capacity RAM, and the printing throughput can be increased.

In addition, in another printing apparatus of the present invention,
It consists of a personal computer and a printer connected through the Centronics interface. Transfer means for block-transferring the printer output data signal of a plurality of words from the personal computer to the printer, and selected one of the block-transferred printer output data signals It has a write control circuit for generating a write control signal based on the bit data, and a memory into which the data of the remaining bits of each printer output data signal is written by the write control signal.

In this case, since the printer output data signal for a plurality of words is block-transferred from the personal computer to the printer, it is not necessary to transfer it for each word. Also, the remaining bit data can be written to the memory without sending other signals such as strobe pulse signals from the personal computer to the printer, and the transfer rate of the personal computer's printer output data signal can be changed to that of the printer's printer output data signal. It can be higher than the consumption rate. As a result, it is not necessary to equip the printer with a large capacity RAM. Then, a read control circuit for generating a read control signal asynchronous with the write control signal to read data from the memory, a unit for transferring the read data to the printer engine unit, and a data stored in the memory And a means for sending a data amount instruction signal indicating the amount to the transfer means. In this case, the transfer means performs block transfer of the printer output data signal in response to the data amount instruction signal.

Therefore, when the data stored in the memory is read and the data amount becomes small, the data amount instruction signal is sent to the transfer means, and the transfer means outputs a plurality of words corresponding to the data amount instruction signal. Block transfer of the printer output data signal of from the personal computer to the printer. In this case, the printer engine unit does not have to wait for the printer output data signal from the personal computer to be transferred and written in the large capacity RAM, and the printing throughput can be increased.

Further, in still another printing apparatus of the present invention, it comprises a personal computer and a printer connected via a Centronics interface, and a transfer means for block-transferring a plurality of words of printer output data signals from the personal computer to the printer. , A write control circuit for generating a write control signal based on a printer control signal sent from a personal computer, and a memory for receiving each printer output data signal.

In this case, since the printer output data signals for a plurality of words are block-transferred from the personal computer to the printer, it is not necessary to transfer each word, and the transfer rate of the printer output data signal of the personal computer is set to the printer output data of the printer. It can be higher than the signal consumption rate. As a result, it is not necessary to equip the printer with a large capacity RAM.

Then, a read control circuit for generating a read control signal asynchronous with the write control signal to read data from the memory, a means for transferring the read data to the printer engine section, and a memory for storing the read data in the memory. And a means for sending a data amount instruction signal indicating the amount of the generated data to the transfer means. In this case, the transfer means performs block transfer of the printer output data signal in response to the data amount instruction signal.

Therefore, when the data stored in the memory is read out and the data amount becomes small, the data amount instruction signal is sent to the transfer means, and the transfer means corresponds to the data amount instruction signal and outputs a plurality of words. Block transfer of the printer output data signal of from the personal computer to the printer. In this case, the printer engine unit does not have to wait for the printer output data signal from the personal computer to be transferred and written in the large capacity RAM, and the printing throughput can be increased.

Further, another printing apparatus of the present invention also has a command / status control circuit for serially transmitting the command / status interface signal and the operation panel interface signal between the personal computer and the printer. In this case, since the processing time for transferring the printer output data signal can be shortened, the time can be used for transmitting the command / status interface signal and the operation panel interface signal. Moreover, since the command / status interface signal and the operation panel interface signal are transmitted serially, it is not necessary to increase the number of signal lines of the Centronics interface.

Further, since it is not necessary to provide the printer with a CPU, a ROM, a large capacity RAM, etc., the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a printing apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a personal computer in a conventional printing apparatus.

FIG. 3 is a block diagram of a Centronics interface on a personal computer side in a conventional printing apparatus.

FIG. 4 is an explanatory diagram of a register of a Centronics interface on a personal computer side in a conventional printing apparatus.

FIG. 5 is a timing chart for transferring 1-byte print data from a personal computer to a printer in a conventional printing device.

FIG. 6 is a diagram showing registers in a CPU of a personal computer in a conventional printing apparatus.

FIG. 7 is a flowchart showing an operation of a CPU in a conventional printing device.

FIG. 8 is a block diagram of a printer in a conventional printing apparatus.

FIG. 9 is a timing chart of a video interface in a conventional printing apparatus.

FIG. 10 is a connection state diagram of signal lines between a control unit and a printer engine unit in a printer of a conventional printing apparatus.

FIG. 11 is a time chart of commands and status between a control unit and a printer engine unit in a printer of a conventional printing apparatus.

FIG. 12 is an internal block diagram of a FIFO memory according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a FIFO memory and a shift register circuit according to the first embodiment of the present invention.

FIG. 14 is a block diagram of a write control circuit according to the first embodiment of the present invention.

FIG. 15 is a block diagram of a read control circuit according to the first embodiment of the present invention.

FIG. 16 is a timing chart of the write control circuit according to the first embodiment of the present invention.

FIG. 17 is a timing chart of a half-full signal according to the first embodiment of the present invention.

FIG. 18 is a flowchart for block-transferring print data in the first embodiment of the present invention.

FIG. 19 is a block diagram of a printing apparatus showing a second embodiment of the present invention.

FIG. 20 is an internal block diagram of a FIFO memory according to a second embodiment of the present invention.

FIG. 21 is a diagram showing a FIFO memory and a shift register circuit according to a second embodiment of the present invention.

FIG. 22 is a block diagram of a write control circuit according to a second embodiment of the present invention.

FIG. 23 is a block diagram of a read control circuit according to a second embodiment of the present invention.

FIG. 24 is a timing chart of the write control circuit according to the second embodiment of the present invention.

FIG. 25 is a flowchart for block-transferring print data in the second embodiment of the present invention.

FIG. 26 is a flowchart for transferring 1-byte print data at the time of block transfer in the second embodiment of the present invention.

FIG. 27 is a block diagram of a printing apparatus showing a third embodiment of the present invention.

FIG. 28 is a timing chart of write control of the FIFO memory according to the third embodiment of the present invention.

FIG. 29 is a block diagram of a command / status control circuit according to the third embodiment of the present invention.

FIG. 30 is a block diagram of a shift register circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 62 printer engine 81 personal computer 82 printer 83 Centronics interface 86,186 FIFO memory 91,191 read control circuit 92,192 write control circuit 201 command / status control circuit IF DATA printer output data signal W-N write control signal R- N Read control signal HF-N Data amount instruction signal

Claims (4)

[Claims] 1. A printing apparatus comprising a personal computer and a printer connected via a Centronics interface, wherein (a) transfer means for transferring a printer output data signal from the personal computer to the printer for each word, and (b) each transferred A write control circuit for generating a write control signal based on the data of a selected bit of the printer output data signal; and (c) the remaining bit of each printer output data signal according to the write control signal. A memory to which data is written; (d) a read control circuit that generates a read control signal asynchronous with the write control signal to read data from the memory; and (e) transfers the read data to the printer engine unit. A printing device comprising: 2. A printing device comprising a personal computer and a printer connected via a Centronics interface, wherein (a) transfer means for block-transferring a plurality of words of printer output data signals from the personal computer to the printer, and (b) a block. A write control circuit for generating a write control signal based on selected bit data of the transferred printer output data signals; and (c) a write control signal for each printer output data signal according to the write control signal. A memory into which the data of the remaining bits are written, (d) a read control circuit for generating a read control signal asynchronous with the write control signal and reading the data from the memory, and (e) a printer for reading the read data. Means for transferring to the engine section, and (f) a data amount instruction signal indicating the amount of data stored in the memory, A printing apparatus comprising: a means for sending to a transfer means, and (g) the transfer means performs block transfer of the printer output data signal in response to the data amount instruction signal. 3. A printing apparatus comprising a personal computer and a printer connected via a Centronics interface, wherein (a) transfer means for block-transferring a plurality of words of printer output data signals from the personal computer to the printer, and (b) a personal computer. A write control circuit for generating a write control signal based on a printer control signal sent from the printer, (c) a memory for receiving each printer output data signal, and (d) a read control signal asynchronous with the write control signal. A read control circuit for reading out data from the memory, (e) means for transferring the read data to the printer engine unit, and (f) a data amount instruction indicating the amount of data stored in the memory. And (g) the transfer means responds to the data amount instruction signal. A printing apparatus, which performs block transfer of the printer output data signal. 4. A printing apparatus according to claim 1, further comprising a command / status control circuit for serially transmitting a command / status interface signal and an operation panel interface signal between a personal computer and a printer. .