JPH0779557B2 - Digital control device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a digital controller suitable for use in capstan control of a video tape recorder.

[Background of the Invention]

In a video tape recorder, speed control and phase control of a capstan motor are performed in order to stabilize the running state of a magnetic tape and obtain good tracking of a reproducing head. This speed control is usually a signal with a frequency proportional to the rotation speed of the capstan motor (ie FG signal).
This FG signal is supplied to the frequency-voltage converter using
A DC voltage of a level corresponding to the frequency of the signal is obtained, and this is used as a speed control signal to keep the rotation speed of the capstan motor constant. On the other hand, the phase control detects the phase difference between the control signal reproduced from the magnetic tape and the reference signal, and controls the rotational phase of the capstan motor according to the phase difference.

By the way, in such a phase control system of the capstan motor, a signal representing the phase difference between the control signal and the reference signal is passed through a phase compensation circuit, and the output signal of this phase compensation circuit is used as a phase control signal to control the phase of the capstan motor. We are trying to improve the response characteristics of the system.

Such a phase compensating circuit is a filter having a first-order lag-lead filter characteristic, and conventionally has an analog structure.

FIG. 9 (a) is a block diagram showing an example of such a filter (hereinafter referred to as a primary lag lead filter), wherein 1 and 2 are resistors, 3 is a capacitor, X is an input signal, and Y is an output signal.

The transfer function G (s) of such a lag-lead filter is 1,2
Let R ₁ and R _{2 be} the resistance values of C and C be the capacitance of the capacitor 3, respectively, and the following can be expressed.

However, T ₁ = C (R ₁ + R ₂ ) T ₂ = CR ₂ The frequency characteristic of this filter is a first-order lag-lead filter characteristic having break points frequencies f _L and f _H as shown in Fig. 9 (b). , The corner frequencies f _L and f _H are expressed as follows, respectively.

f _L = 1 / 2πT ₁ , f _H = 1 / 2πT ₂ By the way, in recent years, electronic circuits have been integrated into integrated circuits (ICs),
There is also a growing demand for ICs in filters. However, in the case of an analog filter as described above, the capacitor 3 needs to be externally attached when it is made into an IC, and the input / output pins of the IC package are The number of circuits is increasing and the circuit configuration is not suitable for IC. Also, this filter
Leakage current is generated from the capacitor 3,
The deterioration of the characteristics was inevitable due to the deterioration of.

Therefore, in order to solve such a problem, a low pass filter having a digital structure, that is, a digital filter having a lag lead filter characteristic has been proposed.

FIG. 10 is a block diagram showing an example of such a conventional digital filter, in which 4,5 are adders, 6, 7, and 8 are multipliers, and 9 is a unit delay element.

This digital filter has a recursive filter configuration having a feedback loop and a feedforward loop, and if the coefficients by which the input signals of the multipliers 6, 7, and 8 are multiplied by a, b, and c, respectively, are in the Z plane. Transfer function G (z) at
Is expressed by the following equation, as is well known.

Now, in order for the characteristics of this digital filter to be equivalent to the characteristics of the low-pass filter in FIG. 9, Expression (2) must equivalently match Expression (1). So z
When the coefficients a, b, and c are obtained by using the difference approximation method which is one of the conversion methods, they are expressed as follows.

As described above, by setting the coefficients a, b, and c, the digital filter shown in FIG. 10 can have characteristics equivalent to those of the analog filter shown in FIG.

This digital filter does not require an input / output pin peculiar to it when it is made into an IC, and its characteristics do not deteriorate.
However, in the case of actually forming this digital filter, a register for holding data is required in the subsequent stage of the adders 4,5 and the multipliers 6, 7, 8 and, moreover, the multipliers 6, 7, For example, assuming that the input data X is 10 bits, the registers in the subsequent stages of 8 must process data of 18 bits or more, respectively, and the register becomes large. Also, the multipliers 6, 7,
Since the coefficients a, b, and c of 8 must be set with extremely high precision, a ROM (read only memory) of 8 to 10 bits must be stored in order to store these coefficients a, b, and c. I need.

As described above, the recursive digital filter requires a large number of registers, especially a large-sized register and a memory, so that the number of elements must be enormous.

Further, as a method for realizing a digital filter having a lag lead filter characteristic, a method using a moving average method is also known. In this method, a plurality of sample data are averaged, and the sample data to be averaged is sequentially shifted by one sampling point. However, the digital filter based on this moving average method depends on the number of sample data for which the corner frequency (cutoff frequency) f _C is averaged, and this digital signal is used in the phase compensation circuit of the phase control system. Since it is necessary to set the corner frequency (cutoff frequency) f _C sufficiently lower than the sampling frequency, the number of sample data to be averaged must be very large. The number will be very large.

As described above, if the first-order lag lead filter is made to have a digital structure and the filter characteristics suitable for the phase compensation circuit are to be provided, the number of elements is inevitably increased and the circuit scale becomes large. Even if you use this primary lag lead filter
Even if it is integrated into an IC, its design is very complicated and extremely high accuracy is required. Therefore, from the viewpoint of cost, it is not realistic to use a digital configuration for the phase compensation circuit. There will be no.

[Object of the Invention]

An object of the present invention is to solve the above problems, to provide a digital control device in which the circuit size of the phase compensation circuit in the phase control system can be reduced to enable digital configuration, and the overall circuit size can be reduced. It is in.

[Outline of Invention]

When the low-pass filter characteristic shown in FIG. 2 (a) and the constant frequency characteristic shown in FIG. 2 (b) are combined, the obtained combined frequency characteristic is the primary lag lead filter characteristic shown in FIG. 2 (c). Becomes

By the way, as described above, the low-pass filter characteristic as shown in FIG. 2 (a) is obtained by moving averaging the input signal.

Therefore, consider moving average of the input signal. If the moving average is performed for b pieces of individual sample data obtained by sampling this input signal, the average value of (b-1) sample data before the nth sample data xn is y _n-1. Then, the average value yn of the b sample data including the (b-1) sample data and the nth sample data xn is expressed as follows.

This is an equation showing the relationship between the input sample data and the output sample data of the filter having the low-pass filter characteristic shown in FIG. 2 (a).

On the other hand, the characteristic shown in FIG. 2 (b) represents that the input signal is uniformly attenuated. If the transfer function of the circuit having such characteristic is 1 / c (where c is constant), Output sample data for input sample data xn is xn / c
Becomes

Therefore, the input sample data of the digital filter having the primary lag lead filter characteristic shown in FIG.
The output sample data yn for xn is Becomes That is, the lag-lead filter having the characteristic shown in FIG. 2C may be configured to perform the arithmetic processing shown in the equation (5), and the sample data of the phase control signal (hereinafter referred to as the phase control data). Will be obtained).

By the way, looking at this equation (5), the first term and the second term on the right side represent the multiplication processing of the input sample data xn, and the third term is the averaging of the input sample data and the coefficient (b-1) / b.
, And the addition process for the entire right side.

Focusing on this point, the present invention configures the phase compensating circuit of the phase control system to enable the arithmetic processing shown in the above equation (5) to reduce the circuit scale. Added to (4) Is performed by the phase compensation circuit, and this sample data can be used as the preset value of the frequency-voltage converter for obtaining the sample data of the speed control signal (hereinafter referred to as speed control data). The control signal and the speed control signal can be added by this frequency-voltage converter.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital controller according to the present invention, in which 10 is a magnetic tape, 11 is a capstan motor, 12 is a frequency generator, 13 is a drive circuit, 14 is a control head, and 15 is a control head. Is a reference phase generator, 16 is a phase controller, 17 is an oscillator, 18 is a clock divider, 19 is a gate circuit, 20 and 21 are AND gates, 22 is ROM (random access memory), 23 is a latch circuit, 24 Is an arithmetic unit, 25 is a phase counter, 26 is a data divider, 27 is a clock divider, 28 is a speed controller, 29 is an AND gate, 30 is an f-V (frequency-voltage) converter, 31 is a pulse width It is a modulator.

In the figure, the reference phase generator 15 and the phase system controller 1
6, clock divider 18, gate circuit 19, AND gate 20, 21,
The ROM 22, the latch circuit 23, the arithmetic unit 24, the phase counter 25, and the data frequency divider 26 constitute a phase control system, and the part except the reference phase generator 15 and the phase system controller 16 is the phase compensation circuit. Are configured. Also a clock divider
27, speed controller 28, AND gate 29 and f-V
Although the converter 30 constitutes a speed control system, it is an fV converter.
The 30 also has a function of adding a phase control signal generated by the phase control system and a speed control signal generated by the speed control system, as will be described later.

Next, the operation of this embodiment will be described. First, the phase control system will be described.

In the figure, the magnetic tape 10 is run by the capstan motor 11, and along with this, the control head 14
The control signal CTLP is reproduced with. The control signal CTLP is supplied to the phase controller 16 and compared with the reference phase signal REF from the reference phase generator 15 to form a difference signal X having a time width corresponding to the phase difference between the two. The output signal CP of the oscillator 17 is frequency-divided by the clock frequency divider 18 to generate a clock of a predetermined frequency, and this clock is supplied to the gate 19, AND gates 20, 21.

When performing phase comparison between the control signal CTLP and the reference phase signal REF, the phase system controller 16 sets the mode switching signal MS that it outputs to "H" (high level). Further, the arithmetic unit 24 and the data divider 26 are composed of a single up / down counter. The upper M ₁ bit part of this up / down counter is the arithmetic unit 24, and the remaining lower M ₂ bit part is the data. The frequency divider 26 is formed. The up / down counter is controlled by the mode switching signal MS output by the phase controller 16. That is, when the mode switching signal MS is "H", the up / down counter is in the up count mode, and the mode switching signal MS is "L".
When it is (low level), the up / down counter is in the down count mode. In FIG. 1, the arithmetic unit 24 and the data frequency divider 26 are shown separately to clarify the operation description thereof. In this case, the arithmetic unit 24 and the data divider 26 are simultaneously in the up-count mode when the mode switching signal MS is “H”, and are simultaneously in the down-count mode when the mode switching signal MS is “L”. The calculation result by these up-counting and down-counting is obtained in the calculator 24.

Therefore, when the mode switching signal MS becomes "H", the phase system controller 16 outputs the difference signal X, and the difference signal X is supplied to the gate circuit 19. The gate circuit 19 is turned on for the time width of the difference signal X and allows the clock output from the clock frequency divider 18 to pass through. Therefore, the signal output from the gate circuit 19 consists of a number of clocks proportional to the time width of the difference signal X, which is the input sample data xn in the above equation (6).

This input sample data xn is converted into A by the data divider 26.
The frequency is divided and supplied to the calculator 24. The arithmetic unit 24 counts up the number of pulses of the sample data xn / A divided by A. Here, when the sample data xn / A is supplied from the data divider 26 to the calculator 24, the calculator 24 has already Is stored. Here, a and b are constants, and y _n-1 is (b-1) before the input sample data xn.
This is the average value of the individual input sample data. Therefore, the calculator 24 counts the value of the sample data xn / A from this data yn '. Therefore, in the computing unit 24, The sample data of the value is obtained.

Here, the division ratio A of the data divider 26 is When set to, It means that the sample data of the value is obtained. This value, which is latched by the latch circuit 23 by the latch pulse RP, is the same as the value of the sample data Yn ′ expressed by the above equation (6). Therefore, the phase compensation circuit has the first-order lag. Since it has a read filter characteristic, the output sample data Yn ′ of the latch circuit 23 is the sum of the phase control data Yn (equation (5)) and the coefficient a. The sample data Yn 'of the latch circuit 23 is supplied to the fV converter 30 as a preset input.

The above arithmetic processing is represented by a series of processing from step 33 to step 38 in the flowchart of FIG.

The above is the outline of the operation of the phase control system. Next, the operation of the speed control system will be described.

A signal having a frequency proportional to the rotation speed of the capstan motor 11 (hereinafter referred to as FG signal) is generated from the frequency generator 12, and the FG signal is supplied to the speed system controller 28.
The speed system controller 28 forms a gate signal VG having a time width corresponding to this cycle for each cycle of the FG signal, and
A preset pulse PS 'is generated for each leading edge of the gate signal, and a latch pulse RP' is generated for each trailing edge of the gate signal.

On the other hand, the output signal CP of the oscillator 17 is supplied to the clock frequency divider 27, and a clock having a frequency necessary for speed control is generated. This clock is AND gated with the gate signal VG.
It is supplied to 29, and as a result, the number of clocks corresponding to this cycle is supplied to the fV converter 30 for each cycle of the FG signal.

In the f-v converter 30, first, the data Yn 'held in the latch circuit 23 is preset by the preset pulse PS' from the speed system controller 28, and then according to the cycle of the FG signal from the AND gate 29. Count a number of clocks. When the counting of this clock is completed, the latch pulse PS 'from the speed system controller 28 causes f
This count value in the −V converter 30 is the pulse width modulator.
Latched to 31. The pulse width modulation circuit 31 further generates a pulse having a time width corresponding to the latched count value and supplies it to the drive circuit 13. The above operation is FG
It is performed every signal cycle.

By the way, since the number of clocks passing through the AND gate 29 by the gate signal VG depends on the cycle of the FG signal, the count number of this clock in the fV converter 30 is a value corresponding to the cycle of the FG signal. Yes, capstan motor
It is a value according to the rotation speed of 11. Therefore, this count number becomes speed control data. The count number latched by the pulse width modulator 31 is the sum of the number of clocks and the data latched by the latch circuit 23.

On the other hand, the data latched by the latch circuit 23 is the sample data Yn 'represented by the above equation (5), and the data Yn represented by the above equation (4) excluding the coefficient a is the input sample data xn. Is output data (that is, phase control data) of the first-order lag-lead filter (that is, a phase compensation circuit).

From the above, the count value latched by the pulse width modulator 31 is the sum of the speed control data value and the phase control data value.

Here, the coefficient a is a unique offset value of the fV converter 30. Now, looking only at the speed control data generating operation in the fV converter 30, the fV converter 30 counts the clocks from the AND gate 29, and when the latch is performed by the latch pulse RP ′, the preset is performed. It must be preset to a constant value by the pulse PS ', and then the clock supplied by the AND gate 29 must be counted from this value. This value is related to the frequency of the clock from the clock frequency divider 27, and when the rotation speed of the capstan motor 11 fluctuates, the control signal formed by the pulse width modulator 31 can eliminate this fluctuation. The speed control data for the required time width is fV converter
Set to get at 30. This value is the coefficient a.

In this embodiment, in the fV converter 30, the offset is not only performed for the offset value a necessary for obtaining the speed control data, but also for the phase control data obtained by the phase control system. , F-V converter
The speed control data is generated at 30 and the speed control data and the phase control data are added together.

Therefore, in this embodiment, the adder for the speed control data and the phase control data, which is conventionally required, becomes unnecessary.

Next, when the control head 14 reproduces the control signal CTLP, the phase system controller 16 generates the next difference signal X, and the input sample data x _{n + 1} is frequency-divided by the data frequency divider 26 to obtain the arithmetic unit 24. The output sample data Y _{n '+ 1 corresponding} to the input sample data x _{n + 1} as shown in the following expression from the above expression (6) is obtained in the latch circuit 23.

However, for this purpose, before the input sample data x _{n + 1} is supplied to the arithmetic unit 24, the arithmetic unit 24 is calculated from the above equation (7). Must be stored.

The calculation process for obtaining the data y _{n ′ +1} is performed in steps 38 to 39, 40, ... In the flowchart of FIG.
..., which corresponds to the processing up to step 33, and AND gates 20, 21, ROM 22, and phase counter 25 are further used to perform this processing.

That is, as described below, the input sample data xn
The output sample data Yn ′ of the phase compensation circuit for is calculated from the above equations (4) and (6) by Is stored in the arithmetic unit 24. Therefore, the third
Referring to the drawing, xn / c and a are subtracted from the output sample data Yn '(steps 39 and 40) to obtain data yn. This data yn is multiplied by a coefficient (b-1) / b. Therefore, as in steps 42, 43, and 44, the data yn
Is multiplied by a coefficient 1 / b to obtain yn / b, and yn / b is subtracted from the data yn. By further adding the coefficient a to this (step 45), the necessary data y _{n + 1} (equation (8)) is obtained.

The data subtraction and addition processing is performed by the arithmetic unit 24, and the multiplication processing is performed by the data divider 26.
In this case, such subtraction and addition are sequentially performed on the data Yn 'stored in the arithmetic unit 24, and the data to be sequentially added to or subtracted from this data Yn' is the phase counter.
Set at 25.

Next, the arithmetic processing operation for obtaining the data y _{n ′ +1} shown in the equation (8) will be specifically described with reference to FIGS. 4 to 6.

FIG. 4 is a block diagram showing the phase compensation circuit of FIG. 1 more specifically, in which 19 ₁ and 19 ₂ are AND gates and 26
_1, 26 ₂ are divider, the parts corresponding to Figure 1 are given the same reference numerals. Further, FIGS. 5 and 6 are signal waveform diagrams showing the signals of the respective parts of FIG.

In FIG. 4, the clock divider 18 includes an oscillator 17 (first
The output signal CP shown in the figure) is divided and two clocks CP ₁ and CP ₂ having different phases are output as shown in FIG. These clocks CP ₁ and CP ₂ are separately supplied to AND gates 19 ₁ and 19 ₂ .

Therefore, the mode switching signal MS is “H”, the arithmetic unit 24 and the data divider 26 are in the up-count mode, and the phase system controller 16 is the reference phase signal REF and the control signal CTL.
When the phase comparison with P is performed, the "H" gate pulses G ₁ and G ₂ with a time width Tx corresponding to these phase differences are detected by the phase controller.
It is supplied from 16 to AND gates 19 ₁ and 19 ₂ , respectively. This is the difference signal X above. Therefore, the AND gates 19 ₁ and 19 ₂ are turned on for the period Tx, respectively, and the number of clocks CP ′ ₁ according to the length of the period Tx is transferred from the AND gate 19 ₁ to the frequency divider 26 ₁ and to the period Tx. The number of clocks CP ' ₂ according to the length is supplied from the AND gate 19 ₂ to the frequency divider 26 ₂ . These AND gates 19 _1, 19 ₂ from the resulting clock CP _'1, CP' ₂
Is the previous input sample data xn.

Here, the frequency division ratio of the frequency divider 26 ₁ is set to c, and the frequency division ratio of the frequency divider 26 ₂ is set to b / c. Clock CP _'1 from the AND gate 19 ₁ is divided by the frequency divider 26 _1. This clock CP 'pulses of ₁ becomes 1 / c, therefore, from the frequency divider 26 _one clock CP from the AND gate 19 _1' data xn / c by ₁ is obtained. The clock CP _'2 from the AND gate 19 ₂ is divided into c / b times in the frequency divider 26 _2, further, the output signal of the frequency divider 26 ₂ is supplied to the divider 26 ₁ 1 /
divided by c. Therefore, data xn / b (= xn × (c / b) × 1 / c) is formed from the input sample data xn from the AND gate 19 ₂ by the frequency dividers 26 ₂ and 26 ₁ .

These data xn / c and xn / b are supplied to the calculator 24. In the arithmetic unit 24, by up-counting the number of pulses of the data xn / c, xn / b, these data are added to the already stored data yn ′ (equation (7)), and the data is obtained by this addition. The data Yn ′ (equation (6)) is latched in the latch circuit 23 by the latch pulse RP.

The above is the operation when generating the output sample data Yn ′ which has already been described.

On the other hand, the phase system controller 16 is, as shown in FIG.
The period Tx of the generated difference signal X and the mode switching signal MS ′ are set to “H”
Then, the phase counter 25 including an up-down counter is set to the up-count mode. At the same time, the phase controller 16 also supplies to the AND gate 21 a gate pulse G ₃ of "H" having a time width equal to the period Tx of the difference signal X, and turns the AND gate 21 on. As a result, the clock CP ₃ is supplied from the clock divider 18 to the phase counter 25 via the AND gate 21. The frequency of the clock CP ₃ is set equal to the frequencies of the clocks CP ₁ and CP ₂ , and therefore the phase counter 25 outputs the same number of pulses as the clocks CP ′ ₁ and CP ′ ₂ from the AND gates 19 ₁ and 19 _2. As a result, the counter 25 receives the input sample data xn
Is retained.

The time when the above operation is completed is t ₀ in FIG.
The data Yn 'is stored in 24, and the input sample data xn is stored in the phase counter 25.

Next, during the period I from time t _{1 to} t _{2 in} FIG. 6, the subtraction process of step 39 in FIG. 3 is performed.

Since the input sample data xn is stored, the output data Σ of the phase counter 25 becomes “L”, but the mode switching signals MS, MS ′ from the phase system controller 16 become “L” and the calculator 24, When the data divider 26 and the phase counter 25 enter the down count mode, at time t ₁ , the phase controller 16 outputs the gate pulses G ₁ and G ₃ because the output data Σ of the phase counter 25 is “L”. H ".

Therefore, the clock CP ₃ output from the clock divider 18
Is supplied to the phase counter 25 via the AND gate 21, and the phase counter 25 counts down this clock CP ₃ . At the same time, the clock CP ₁ output from the clock divider 18 is divided by the AND gate 19 ₁ into the divider 26.
_It is supplied to ₁ , is divided into 1 / c, and is supplied to the calculator 24.
As a result, the calculator 24 counts down the data xn / c.

When the phase counter 25 counts down by xn, the output data Σ becomes “H”, which causes the phase controller 16 to set the gate pulses G ₁ and G ₃ to “L” and the AND gates 19 ₁ and 21 to the off state. Become. Where clocks CP ₃ and CP ₁
Since the frequencies are equal, the input sample data xn is obtained from the AND gate 19 ₁ during the period in which the phase counter 25 counts down by xn.
24 means that only xn / c has been subtracted during this period.
The data stored in 24 is as follows.

On the other hand, the above-mentioned coefficient a is stored in the ROM 22 and, under the control of the phase controller, it is between the times t ₂ and T ₃ (the sixth coefficient).
This coefficient a is read out from the ROM 22 in the figure) and preset in the phase counter 25. This allows the phase counter
The output data Σ of 25 becomes “L”. Next, during the period II from time t ₃ to time t ₄ , the subtraction process of step 40 in FIG. 3 is performed.

That is, the phase system controller 16 at time t ₃ is set to the gate pulse _{G 3, G 4 "H"} , the AND gate 21 and 20 to the ON state. Therefore, the clock CP output by the clock divider 18
₃ to the phase counter 25 via the AND gate 21, and also
It is supplied to the computing unit 24 via the AND gate 20, respectively. Here, the phase counter 25 and the arithmetic unit 24 are both in the down-count mode, and respectively down-count the same clock CP ₃ .

When the phase counter 25 down-counts by the value of the coefficient a, the output data Σ of this phase counter 25 becomes “H”, and accordingly, the phase system controller 16 sets the gate pulses G ₃ and G ₄ to “L” and AND gate. Turn off 21,20. As a result, the arithmetic unit 24 has subtracted only the value of the coefficient a, so that the data stored in the arithmetic unit 24 becomes yn.

Next, the period III between time t ₅ and time t ₆ in FIG.
Then, the processing of steps 42, 43 and 44 shown in FIG. 3 is performed. This processing is to multiply the data yn by the coefficient b / 1) / b. Therefore, the data yn is multiplied by the coefficient 1 / b (step 4
3), subtract data yn / b from data yn (step 4
4) It is something.

Therefore, first, the value of the data yn stored in the calculator 24 is preset in the phase counter 25 between the time t ₄ and the time t ₅ immediately before the period III. This allows the phase counter 25
Output data Σ becomes “L”.

Then, at time t ₅ , the phase system controller 16 sets the gate pulses G ₂ and G ₃ to “H” because the output data Σ of the phase counter 25 is “L”, and turns on the AND gates 19 ₂ and 21. To For this purpose, the clock CP ₃ is supplied from the clock divider 18 to the phase counter 25 via the AND gate 21, and the clock CP ₃ is supplied from the clock divider 18 to the divider 26 ₂ via the AND gate 19 _{2. 2} is supplied. Here, the phase counter 25, the data divider 26, and the calculator 24 are in the down-count mode, and the phase counter 25 has the clock CP ₃
To count down.

When the phase counter 25 counts down the clock CP ₃ by the value of the data yn, the phase system controller 16 sets the gate pulses G ₂ and G ₃ to “L”, and turns off the AND gates 19 ₂ and 21.

Therefore, the AND gate 19 ₂ outputs a number of clocks equal to the data yn, and this clock is divided by the frequency dividers 26 ₂ , 2 2.
Is divided by 6 ₁ yn / b becomes data is obtained. The arithmetic unit 24 counts down from the data yn by the data yn / b. Therefore, the data stored in the calculator 24 is Becomes

Next, the addition process of step 45 shown in FIG. 3 is performed in the period IV from time t ₇ to time t _{8 in} FIG.

First, under the control of the phase controller 16, time t ₆ ,
The coefficient a is read from the ROM 22 between t ₇ and the phase counter 25
Is preset to. As a result, the output data Σ of the phase counter 25 becomes “L”.

Then, at time t ₇ , the phase controller 16 sets the gate pulses G ₃ and G ₄ to “H” to turn on the AND gates 21 and 20, and sets the mode switching signal MS to “H” to make the calculator 2
4. Switch the data divider 26 to the up-count mode.
The phase counter 25 is kept in the down count mode as it is.

Therefore, the clock CP ₃ from the clock divider 18 is sent to the calculator 24 via the AND gate 20 and also to the AND gate 21.
Are supplied to the phase counter 25 via the. The calculator 24 counts up the clock CP ₃ , but the phase counter 25
Counts down this clock CP ₃ . When the phase counter 25 counts down the number of coefficients a, the output data Σ of the phase counter 25 becomes “H”.
And turning off the AND gate 20 and 21 to "L" to G _4, G _3.

As a result, the arithmetic unit 24 counts up by the value of the coefficient a, and the data stored in the arithmetic unit 24 is Becomes This data is the data y shown in the above equation (8).
equal to _{n '+ 1} , which is the next input sample data x _{n + 1}
On the other hand, it is the data that should be previously stored in the arithmetic unit 24.

As described above, in the phase compensation circuit, the input sample data
Each time xn is supplied, the series of arithmetic processing shown in FIG. 3 is sequentially performed, and as a result, 1 as shown in FIG.
The next lag lead filter characteristic is obtained.

In this phase compensation circuit, the break point frequency f _L of the first-order lag-lead filter characteristic shown in FIG.
It is determined by the corner frequency f _L of the low-pass filter characteristic of FIG. 7A, which is determined by the coefficient b of the equation (4). Therefore, it is determined by the frequency dividers 26 ₁ and 26 ₂ of FIG. It can be set arbitrarily by changing the circumference ratios c and b / c. Further, the break frequency f _H of the characteristic shown in FIG. 2 (c) can be similarly selected by the frequency division ratio c of the frequency divider 26 ₁ .

By the way, when the phase control system is activated, the arithmetic unit 24 does not have the data shown in the above equation (8). For this reason, ROM22 also stores the data at the time of startup corresponding to equation (8), and this data is stored at the time of startup.
The data is read from the ROM 22 and preset in the phase counter 25, and then this data is stored in the arithmetic unit 24 in the same manner as the operation in the period IV in FIG. Then, the phase controller 16 starts comparing the reference phase signal REF with the control signal CTLP, and the above-described operation is performed.

Here, the above-mentioned data at the time of startup stored in the ROM 22 corresponds to the above equation (8), and yn is input sample data obtained when the phase difference between the reference phase signal REF and the control signal CTLP is correct, for example. The average value of b is calculated by multiplying this yn by a coefficient (b-1) / b and further adding a coefficient a. Of course, this data yn is stored in the ROM 22, this data yn is preset in the phase counter 25, and the operation in the period III of FIG. 6 is performed, and the data (b-1) yn / b is supplied to the arithmetic unit 24. After storing, the operation from time t ₆ to time t _{8 in} FIG.
May be added.

FIG. 7 is a block diagram showing a specific example of the clock divider 18 of FIG. 4, in which 47 is an input terminal, 48 is an inverter, and 49 is a T-type flip-flop circuit (hereinafter referred to as T-FF circuit). , 50 and 51 are AND gates, and 52 and 53 are output terminals.

Further, FIG. 8 is a waveform diagram showing the signals of the respective parts in FIG. 7, and the signals corresponding to those in FIG. 7 are designated by the same reference numerals.

In FIG. 7 and FIG. 8, the output signal CP of the oscillator 17 (FIG. 4) is T- as a trigger pulse from the input terminal 47.
It is supplied to the FF circuit 49, inverted by the inverter 48, and supplied to the AND gates 50 and 51.

The T-FF circuit 49 is triggered by the rising edge of the signal CP,
Each time it is triggered, its Q output and output are level inverted. Therefore, these Q output and output are obtained by frequency-dividing the signal CP by two, and have a mutually opposite phase relationship.

The Q output and output of the T-FF circuit 49 are supplied to AND gates 50 and 51 as gate pulses, respectively. For this purpose, AND gates 50 and 51 alternately extract the signal CP from the inverter 48. Therefore, the AND gates 50 and 51 are 180
° Clocks CP ₁ and CP ₂ with different phases are obtained. The clock CP ₃ shown in FIG. 4 is the clock CP ₁ , CP ₂
Either one may be used.

As described above, in this embodiment, the arithmetic unit 24, the data frequency divider 26, and the phase counter 25 are constituted by the up / down counter, and a predetermined arithmetic processing is performed by the up / down counter. In order to obtain a characteristic, it is not necessary to use an adder or a multiplier for obtaining such a characteristic in the related art. It can also be used for the phase compensation circuit. As a result, the phase compensation circuit can be configured with a small number of elements.

Further, the phase control data generated by the phase compensation circuit can be used as the preset value of the frequency-voltage converter for speed control data generation in the speed control system, and as a result, the speed control data and the phase control data can be combined. The frequency-voltage converter can also be used as an adder for addition, and the overall configuration of the control device can be simplified.

In the above embodiment, the case where the capstan motor of the video tape recorder is controlled has been described, but similarly, the drum of the video tape recorder that requires the phase compensation circuit having the filter characteristic shown in FIG. Obviously, it can be applied to control of motors and control of other similar controlled systems.

[Effects of the Invention] As described above, according to the present invention, it can be realized by using an up-down counter in the phase compensation circuit of the phase control system,
This can also be used as a counter used for other purposes in the control system, and the number of constituent elements of the phase compensation circuit can be significantly reduced, and the phase control signal and the speed control signal, which were conventionally required, can be directly used. An adder for adding can be omitted, and a digital controller having an excellent function can be provided at low cost, except for the above-mentioned drawbacks of the prior art.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital controller according to the present invention, FIG. 2 is an explanatory diagram of the first-order lag lead filter characteristic, and FIG. 3 is an explanation of the arithmetic processing of the phase compensation circuit in FIG. Fig. 4 is the first flowchart
5 is a block diagram showing the phase compensating circuit in more detail, FIG. 5 and FIG. 6 are waveform diagrams showing the signals of the respective parts in FIG. 4, and FIG. 7 is a specific example of the clock divider in FIG. FIG. 8 is a waveform diagram showing signals of respective parts in FIG. 7, FIG. 9 (a) is a circuit diagram showing an example of a conventional phase compensation circuit, and FIG. 9 (b) is FIG. FIG. 10 is a characteristic diagram of the phase compensation circuit shown in (a), and FIG. 10 is a block diagram showing another example of the conventional phase compensation circuit. 10 …… magnetic tape, 11 …… capstan motor, 12 …… frequency generator, 14 …… control head, 15 …… reference phase generator, 16 …… phase system controller, 17 …… oscillator, 18…
… Clock divider, 19 …… Gate, 19 ₁ , 19 ₂ , 20, 21, 21 ……
AND gate, 22 ...... Read only memory, 23 …… Latch circuit, 24 …… Calculator, 25 …… Phase counter, 26 …… Data divider, 26 ₁ , 26 ₂ …… Divider, 27 …… Clock divider, 28
... Speed controller, 29 ... AND gate, 30 ... frequency-voltage converter, 31 ... pulse width modulator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Fukushima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Electric Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Eiichi Funagi 1410 Inada, Katsuta-shi, Ibaraki Company Hitachi, Ltd. Tokai factory (56) Reference JP 61-94579 (JP, A) JP 59-59088 (JP, A) JP 59-67884 (JP, A)

Claims (1)

[Claims] 1. A digital phase error detecting means for detecting a phase difference between a signal representing a phase of a controlled object and a reference phase signal, and a digital filter for arithmetically processing a phase information group successively obtained by the digital phase error detecting means. Means, a digital speed error detecting means for inputting a signal representing the speed of the controlled object, and a digital adding means for adding speed information obtained from the digital speed error detecting means and output information of the digital filter means, In a digital control device comprising digital-analog conversion means for converting the output of the digital addition means from a digital signal to an analog signal, the digital filter means has a first reference clock and a frequency of the first reference clock. Second reference clocks having the same phase and different phases, and the first and second reference clocks And a period Tx corresponding to the phase difference detected by the digital phase error detecting unit, and a clock generator for generating a third reference clock having the same frequency The first frequency dividing means, the second reference clock of the period Tx corresponding to the phase difference detected by the digital phase error detecting means, and the output of the first frequency dividing means, and the mixing is performed. The second to divide the clock by c
And a preset value is set, and the preset value is set to the second value.
First counter means for counting the output of the frequency dividing means and the count value after counting the output of the second frequency dividing means by the first counter means, and the next time by the digital phase error detecting means. And a preset means for generating the next preset value when the first counter means counts the output of the second frequency dividing means in accordance with the detection of the phase error of The preset means upcounts the third reference clock in the period Tx, and then downcounts the third reference clock by the upcount, and the first operation. And a second counter means for performing a second operation of down-counting the third reference clock by the value of the first counter means, and the first operation of the second counter means. Out of During the down-counting period, the second reference clock divided by c by the second frequency-dividing means is down-counted by the first counter means, and the second reference clock of the second counter means is down-counted. During the operation period of 1, the first counter means down-counts the first reference clock divided by b by the first and second frequency-dividing means. A preset value for the next generation is generated, wherein the first reference clock divided by b by the first and second frequency dividers is counted from the preset value by the first counter means. , A low-pass filter characteristic is obtained, and the second reference clock divided by c by the second frequency dividing means is counted by the first counter means, whereby a predetermined attenuation characteristic is obtained and the digital signal is obtained. The characteristics of the filter means are lagging as a whole Digital control apparatus characterized by forming the over de properties.