JP2754807B2 - Control device for rotating body - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a rotating body for controlling the speed and phase of the rotating body used in a magnetic recording / reproducing apparatus or the like.

2. Description of the Related Art A control device for a rotating body is provided with a speed control for controlling a cycle of an output signal (hereinafter, referred to as an FG signal) of a frequency generator attached to the rotating body so as to have a desired cycle, and a control apparatus attached to the rotating body. Phase control is performed to control the phase difference between the signal indicating the position (hereinafter, referred to as a PG signal) and the reference phase signal to a desired value.

For example, in a cylinder motor of a magnetic recording / reproducing apparatus, a frequency generator attached to the motor generates an FG signal of six pulses per rotation, and generates a PG signal of one pulse per rotation. Since the cylinder motor rotates at 30 Hz, the frequency of the FG signal is 180 Hz, and the reference cycle is 1/180 sec. Therefore, the speed control is performed so that the period of the FG signal becomes 1/180 sec. Further, the frequency of the PG signal is 30 Hz, and phase control is performed so as to have a predetermined phase difference from the reference phase signal.

The error output of the speed control and the error output of the phase control are combined at their respective combined ratios, output to the drive circuit of the cylinder motor, and the output of the drive circuit drives the cylinder motor to perform rotation control.

However, a steady speed deviation and a steady phase deviation occur due to an offset, a load, and the like generated between the combined output of the speed control output and the phase control output and the drive circuit. The steady-state speed deviation hardly occurs because the phase control operates as an integral term of the speed control system.However, since the phase control system operates to correct the steady-state speed deviation of the speed control, the correction output is output to the error output of the phase control. Appears, and the center value of the phase error output is shifted. In particular, since the gain of the phase control system is larger than the gain of the speed control system, a small steady-state speed deviation appears as a large steady-state phase deviation, which causes a large steady-state phase deviation.

Since the stationary phase deviation has no integral term in the phase control system, only one gain of the phase control remains. Therefore, PG
The phase difference between the signal and the reference phase signal cannot be set to the set value. Thus, a low-pass compensation filter is inserted into the phase error output so as to compensate for the low-frequency error output. With this filter, the steady phase deviation is eliminated.

If this low-pass compensation filter is constituted by a digital filter, it becomes as shown in FIG. This filter is digitally configured because the speed control and phase control are processed digitally. If the operation of the filter can be processed digitally, all the control including the operation of the filter can be implemented as a digital IC. Because. Further, by digitizing the filter, it is possible to eliminate a change in characteristics caused by a variation in parts, a change in temperature, or the like.

Here, the operation of the digital filter shown in FIG. 9 will be described. First, input data is input from a terminal 1101 and is multiplied by a constant by a multiplier 1102. In a block 1103 for performing the cumulative addition, the cumulative output of the output data of the multiplier 1102 is performed, and the cumulative result is stored in the memory. Here, Z ¹ is a symbol representing one sample delay. The multiplier 1104 multiplies the accumulation result of the block 1103 by a constant, adds the output data of the multiplier 1104 and the output data of the multiplier 1102 in the adder 1105, and outputs the result from the output terminal 1106 as the output data of the digital filter.

In the block 1103 for performing the cumulative addition, the accumulated data stored in the memory is data for compensating for the steady-state speed deviation and the steady-state phase deviation. Or become. Therefore, when a large load is applied or when the speed deviation is large, the accumulated data stored in the memory has a large value.

However, in the above configuration, when the speed deviation and the phase deviation are large, the accumulated data of the low-pass compensation filter for compensating for the deviation has a large value, and the memory storing the accumulated data has a large value. It may exceed the maximum possible value. For this reason, the value stored in the memory is fixed to the upper limit or the lower limit, and as a result, compensation cannot be performed by the cumulative term, and a deviation remains. The fact that the steady phase deviation remains means that the performance of the phase control has deteriorated. In an extreme case, there is a problem that the phase is not locked and the phase control does not operate normally.

Means for Solving the Problems In order to solve the above-described problems, a rotating body control device of the present invention has a frequency discriminating unit for frequency discriminating a signal having speed information of the rotating body, and has position information of the rotating body. Phase comparing means for comparing the phase of the signal with the reference phase signal output from the reference phase signal generating means, a digital filter for compensating the output of the phase comparing means in a low frequency range, and an output of the digital filter and the frequency discriminating means. Synthesizing means for synthesizing the outputs of the digital filter, driving means for driving the rotating body by the output of the synthesizing means, overflow detecting means for detecting overflow of the digital filter, and an output signal of the overflow detecting means. Output correction means for correcting the output of the digital filter so that the operating point is substantially at the center; It is comprised including.

The present invention detects the overflow of the accumulated term of the digital filter for compensating for the steady speed deviation and the steady phase deviation caused by the offset, the load, and the like, and corrects the output signal of the digital filter by the detected output. Since the accumulated term of the digital filter does not overflow, the digital filter (low-pass compensation filter) can remove the steady-state speed deviation of the speed system and the steady-state phase deviation of the phase control system.

Embodiment Hereinafter, a control device for a rotating body according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a control device for a rotating body showing an embodiment of the present invention. 1 is a rotating body (motor), 2
Is a frequency generator for extracting rotation information of the motor 1,
The FG signal is output. Reference numeral 3 denotes frequency discriminating means for discriminating the frequency of the FG signal. Reference numeral 4 denotes a synthesizing unit that synthesizes the output of the frequency discriminating unit 3 and the output of the output correcting unit 11 (described later). Reference numeral 5 denotes a digital-analog converter to which the digital data output of the synthesizing means 4 is input, and reference numeral 6 denotes a power amplifier for amplifying the analog signal, and the output drives the motor 1. The speed control system is configured by the above loop.

Next, reference numeral 7 denotes position detecting means for extracting a position signal of the motor 1, and the position signal (PG signal) is input to the phase comparator 8. The reference phase signal output from the reference phase signal generating means 9 is input to the phase comparator 8. The output of the phase comparator 8 is input to a digital filter 10, where low-frequency compensation is performed. The digital filter 10 sends the output after the filter processing to the output correction means 11, and sends the overflow detection signal to the output correction means 11. Output correction means 11 is based on the overflow detection signal of digital filter 10,
The output data of the digital filter 10 is corrected. The above loop constitutes a phase control system.

FIG. 2 is a time chart for explaining the operation of the frequency discriminating means 3, in which a is an FG signal, b is a trapezoidal wave for performing frequency discrimination, and a trapezoidal waveform at the time when the FG signal a is input. The speed error output c is obtained by sampling the value of the wave b. After the trapezoidal wave b is sampled by the FG signal, a new reference cycle is set to create a trapezoidal wave of the next FG signal. The speed error output c outputs a positive error output when the period of the FG signal a is shorter than the reference period, and outputs a negative error output when the period is longer than the reference period.

FIG. 3 is a flowchart in the case where the above operation of the frequency discriminating means 3 is realized by software.
In, it is determined whether the FG signal is input,
If the FG signal has been input, the process proceeds to a process 302, and if the FG signal has not been input, the process proceeds to a process 307. In process 302
The cycle of the FG signal is calculated. NSB is the count value of the base counter when the previous FG signal was input, and NS is the count value of the base counter when the current FG signal was input.
Assuming that A, the period PER_S of the FG signal is obtained by equation (1).

PER_S = NSB-NSA (1) Here, the base counter is treated as operating as a cyclic counter that counts down the reference clock signal.

Next, in the process 303, the speed error ERR_S is obtained by the equation (2) using the period PER_S of the FG signal obtained in the process 302 and the reference period REF_S.

ERR_S = REF_S-PER_S (2) Then, in process 304, a limit process is performed so that the speed error ERR_S falls within a prescribed range, and in process 305, the speed error ERR_S is output to the combining means 4. after that,
In preparation for the processing of the next FG signal, in processing 306, the count value NSA of the base counter at the time when the current FG signal is input is stored again in the NSB, and the operation of the frequency discriminating means 3 is terminated.

If the FG signal is not input in the processing 301, the next F is input after the previous FG signal is input in the processing 307.
It is determined whether or not the G signal has exceeded the allowable time to be inputted. If it has, the speed error output for maximally accelerating the motor 1 is output to the synthesizing means 4 in processing 308, and the processing is terminated. Exit without doing anything.

As described above, for the speed error ERR_S, a positive value is input if the measured period PER_S of the FG signal is shorter than the reference period REF_S, and a negative value is input if it is longer.

FIG. 4 is a time chart for explaining the phase comparison means 8, wherein a is a reference phase signal, b is a trapezoidal wave for performing phase comparison created from the reference phase signal a, and a PG signal. The phase error output d is obtained by sampling the trapezoidal wave b at the time when c is input. The phase error output c is a positive error when the phase difference between the reference phase signal a and the PG signal c is shorter than a predetermined phase difference. Outputs an error, and outputs a negative error output when the output is long.

FIG. 5 is a flowchart in the case where the operation of the phase comparison means 8 is realized by software. In a process 501, it is determined whether or not the reference phase means (REF_P) is input from the reference phase signal generation means 9 and the reference phase signal is determined. If the reference phase signal has not been input, the process proceeds to step 502. In process 502, the count value of the base counter at the time when the reference phase signal is input
CN1 is stored in the memory N_REF. In the process 503, it is determined whether or not the PG signal has been input. If the PG signal has been input, the process proceeds to the process 504, and the count value CN2 of the base counter at the time when the PG signal was input is stored in the memory NPA. ing. In the process 505, the phase error ERR_P is obtained by the equation (3).

ERR_P = N_REF_P- (N_REF-NPA) (3) Here, N_REF_P is a count value representing a reference phase difference.

Next, in processing 506, limit processing is performed so that the phase error ERR_P falls within a specified range, and in processing 507, the phase error ERR_P is output to the digital filter 10. Thus, the operation of the phase comparison means 8 is completed.

If the PG signal is not input in the process 503, the process ends without doing anything.

Next, FIG. 6 shows a block diagram of the digital filter 10. Input data is input from an input terminal 601 and is multiplied by a constant by a block 602. Input terminal 60 in block 603
The cumulative addition of the input data input from 1 is performed, and the cumulative result is stored in the memory. In block 604, block 603
Is multiplied by a constant, and in block 603 block 6
Adds the output data of 04 and the output data of block 602 and outputs it as digital filter output data.
Output from 606.

When the memory storing the accumulation result overflows in block 603, an overflow detection signal is output from an overflow output terminal 607. The overflow detection signal includes data indicating the polarity of the overflow.

FIG. 7 is a flowchart when the operation of the digital filter 10 is realized by software. In the process 701, the data D1 input to the input terminal 601 shown in FIG.
Is stored in the memory MI. In the process 702, the data of the memory MI is multiplied by the constant C1, and the multiplication result is stored in the memory M2. In the process 703, the data of the memory MI in which the accumulated result is stored and the input data D1 are added, and the added result is stored in the memory MI again. In process 704, memory M
It is determined whether the addition result stored in I exceeds the maximum value or the minimum value that can be stored in the memory MI, that is, whether the overflow has occurred. memory
If the MI has not overflowed, the process proceeds to processing 705,
The data of the memory MI, which is the accumulation result, is multiplied by a constant C2, and the multiplication result is stored in the memory M3. Then, in the process 706, the data of the memory M2 and the data of the memory M3 are added, and the addition result is output as output data of the digital filter 10.

In the process 704, if the memory MI overflows, the process proceeds to the process 707, and it is determined whether the overflow exceeds the maximum value or the minimum value. That is, the polarity of the overflow is determined. When the overflow of the memory MI is the maximum value, the process proceeds to step 708, where the memory M
The value of I is set to the maximum value, and a positive overflow signal is output from the output terminal 607 shown in FIG. When the overflow of the memory MI is the minimum value, the processing shifts to processing 709, where the value of the memory MI is set to the minimum value, and a negative overflow signal is output from the output terminal 607. After that, the processing shifts to processing 705. As described above, the digital film is processed by the software.

Next, the output correction means 11 for correcting the output of the digital filter 10 based on the output of the overflow detection signal will be described. FIG. 8 is a flowchart when the output correction means 11 is realized by software. In step 801, the overflow signal output from the digital filter 10 is fetched, and it is determined whether or not the memory MI of the digital filter 10 has overflowed. If not, the process ends. If the digital filter 10 has overflown, the flow shifts to processing 802. In the process 802, it is determined whether or not the polarity of the overflow signal is positive. In the process 803, the following process is performed.

The positive polarity of the overflow signal means that
Although the output of the digital filter 10 must output a larger value than the positive value, the output is limited by the cumulative memory MI and cannot be increased beyond the limit value. Therefore, the digital filter
The output of 10 is corrected using the correction value so that the accumulated memory MI does not overflow.

That is, as shown in equation (4), the digital filter
What is necessary is just to correct ten output data FIL.

FIL_C = FIL + ΔC (4) Here, FIL_C is an output of the output correction means 11 that has corrected the output data of the digital filter 10, and ΔC is a correction value. Large steady speed deviation or steady phase deviation,
When the overflow of the digital filter 10 is not improved only by performing the correction by the expression (4) once, the correction by the expression (4) is repeated, and the value of the memory MI storing the accumulated value becomes almost “0”. If this is done until the operation is centered, the pull-in range by the phase control system is greatly improved.

When the polarity of the overflow signal in the process 802 is negative, a process similar to the process performed in the process 803 is performed in the process 804. That is, the correction value Δ used in equation (4)
What is necessary is just to subtract C from the output data FIL of the digital filter 10, and it is represented by the equation (5).

FIL_C = FIL_C (5) As described above, the overflow of the low-pass compensation filter (digital filter 10) of the phase control system caused by the steady speed deviation is corrected by correcting the output signal of the digital filter 10. Can be prevented from overflowing, and the operating point of the digital filter 10 can be set near the center, so that a low-frequency compensation operation with a wide operating range can be performed.

In the present embodiment, the case where each process is configured by software has been described. However, it may be configured by hardware so that the same operation can be performed.

As described above, the present invention provides a frequency discriminating means for frequency discriminating a signal having speed information of a rotating body, a signal having position information of the rotating body, and a reference phase signal output from a reference phase signal generating means. Phase comparing means for comparing the phase of the digital filter, a digital filter for compensating the output of the phase comparing means in a low frequency range, a synthesizing means for synthesizing the output of the digital filter and the output of the frequency discriminating means, Drive means for driving the rotating body, overflow detection means for detecting overflow of the digital filter, and output of the digital filter such that the operating point of the digital filter is substantially centered by an output signal of the overflow detection means. Output correction means for correcting the steady speed deviation and the constant speed deviation. The overflow of the low-pass compensation filter (digital filter) of the phase control system caused by the normal phase deviation is corrected using the correction value of the output of the digital filter so that the digital filter does not overflow and the operation of the digital filter is performed. Since the point can be set near the center, a low-frequency compensation operation with a wide operation range can be performed, and a great effect is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a control device for a rotating body according to an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of the frequency discriminating means, and FIG. FIG. 4 is a time chart for explaining the operation of the phase comparator, FIG. 5 is a flowchart in the case where the phase comparator is constituted by software, FIG. 6 is a block diagram of a digital filter, and FIG. FIG. 8 is a flowchart for explaining the operation of the output correction means when the filter is constituted by software, and FIG. 9 is a block diagram of a conventional digital filter. DESCRIPTION OF SYMBOLS 1 ... Motor, 2 ... Speed generator, 3 ... Frequency discriminating means, 4 ... Synthesizing means, 5 ... Digital-analog converter, 6 ... Power amplifier, 7 ... Position detecting means, 8 ...
Phase comparison means, 9 ... Reference phase signal generation means, 10 ... Digital filter, 11 ... Output correction means.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H02P 5/00

Claims (4)

(57) [Claims] A frequency discriminating means for frequency discriminating a signal having speed information of a rotating body, and a phase comparison between a signal having position information of the rotating body and a reference phase signal outputted from a reference phase signal generating means. Phase comparing means, a digital filter for compensating the output of the phase comparing means in a low frequency range, synthesizing means for synthesizing the output of the digital filter and the output of the frequency discriminating means, and driving the rotating body with the output of the synthesizing means Drive means, an overflow detection means for detecting overflow of the digital filter, and an output correction means for correcting an output of the digital filter so that an operating point of the digital filter is substantially centered by an output signal of the overflow detection means. A control device for a rotating body, comprising: 2. A digital filter, comprising: multiplying input data by a coefficient to obtain a proportional term; multiplying a cumulative term obtained by accumulating the input data by a coefficient to obtain an integral term; The control device for a rotating body according to claim 1, wherein the addition of the integral term is performed to output a result of the addition. 3. An apparatus according to claim 2, wherein said overflow detecting means detects that an integral term of said digital filter has exceeded a predetermined upper limit value or lower limit value. 4. The apparatus according to claim 3, wherein the output correction means adds or subtracts a correction value to or from the output of the digital filter in accordance with the polarity of the output signal of the overflow detection means for detecting overflow of the digital filter. Of rotating body control.