JPH0779228B2 - Edge detection circuit - Google Patents

Description

The present invention relates to an edge detection circuit, and an object thereof is to realize an edge detection circuit that receives two input signals in which at least one logic level changes asynchronously with a small circuit scale and high responsiveness. In response to the edge of the first input signal, the internal logic state is changed, the logic state is held until a predetermined first release command is input, and the first logic corresponding to the held logic state is set. First holding means for outputting the first state signal, first instruction means for outputting the first state signal as a first release instruction after delaying the first state signal for a predetermined time, and edge of the second input signal In response to the change, the internal logic state is changed, the logic state is held until a predetermined second release command is input, and a second state signal corresponding to the held logic state is output. Holding means and usually A second state signal is passed through the second state signal, and a second state signal passing through the second state signal and a second state signal passing through the second state signal are output to the predetermined state. A second state in which the internal logic state is changed in response to the second command means that outputs a second release command after the time delay and the first state signal, and the logic state has passed through the prohibiting means. Third holding means for holding the signal until it receives the signal and outputting an output signal according to the logic state.

[Industrial application field]

The present invention relates to an edge detection circuit, and more particularly to an edge detection circuit which receives two signals whose one logic level changes asynchronously.

Generally, in many cases, signals are exchanged between a plurality of electronic devices in common with a common clock signal, but some of them are asynchronously exchanged. As an example, when the control signal Ca is transmitted from the device A to the device B, the function of the device B is switched, and when the control signal (asynchronous) Cc is transmitted from the device C to the device B, the function of the device B is changed. Consider a system that can be restored. Now, when Cc is sent at a sufficient elapsed time after Ca is sent, the function of the device B operates normally as switching → returning.

By the way, since Cc is asynchronous, it can be sent out almost at the same time as Ca. In this case, the function of device B cannot be switched (Ca was not received), or after switching, the recovery was not performed (Cc was not received). Cause of.

[Conventional technology]

As a conventional countermeasure of this kind, for example, there is one using a sampling clock. In this device, an asynchronous signal is sampled and synchronized, so that the above-mentioned problem can be solved.

[Problems to be Solved by the Invention]

However, in this type of conventional device, when a timing clock is required, a sampling circuit is required, and the period of the timing clock is long, an unintentional shift occurs between the control signal and the actual response. There are various defects such as. That is, there are problems in terms of the circuit scale and the responsiveness of the circuit operation.

The present invention has been made in view of such problems,
It is an object of the present invention to realize an edge detection circuit that receives two input signals in which at least one logic level changes asynchronously with a small circuit scale and high responsiveness.

[Means for Solving the Problems]

FIG. 1 shows a block diagram of the principle of the edge detection circuit of the present invention.

In FIG. 1, the internal logic state is changed in response to the edge of the first input signal, the logic state is held until a predetermined first release command is input, and the held logic state is maintained. A first holding means 1 for outputting a corresponding first state signal, and after delaying the first state signal for a predetermined time,
A first command means 2 for outputting as a first release command, and an internal logical state is changed in response to an edge of a second input signal, and the predetermined second release command signal is input to the logical state. Second holding means 3 which holds the second state signal in accordance with the held logical state and the second state signal which is normally passed and outputs the first state signal. While prohibiting the passage of the second state signal, the second state signal that has passed through the prohibiting means 4 is delayed for a predetermined time and then output as a second release command.
Of the instruction means 5 and the first state signal to change the internal logical state, hold the logical state until the second state signal that has passed through the prohibiting means 4 is received, and respond to the logical state. Third holding means 6 for outputting an output signal
It is configured with.

[Work]

In the present invention, the second input signal is held in the second holding means from the change of the logic level of the first input signal until the output of the first release command (hereinafter, period A). During this period, the output signal is output at a predetermined logic level according to the first input signal. When the first release command is output after the period A has passed, the output signal is output at a predetermined logic level according to the second input signal. That is, within the period A, the output signal does not change even if the second input signal is input, and the second input signal is held in the second holding means during this period, so the first and second input signals are held. It is possible to avoid problems when is input almost at the same time. Therefore, since a sampling circuit or the like is not required, the circuit scale can be reduced, and since synchronization due to sampling is not taken, deterioration of responsiveness can be avoided.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

2 and 3 are diagrams showing an embodiment of the present invention.

First, the configuration will be described. In FIG. 2, 1 is first holding means, 2 is first commanding means, 3 is second holding means, 4
Is a prohibiting means, 5 is a second commanding means, 6 is a third holding means, and 7 is a NAND.

First holding means 1, two NAND1a, has a S-R latch constituted by 1b, S-R latch, the first input signal SI ₁ is applied to the input at "L" level In the initial state, XQ ₁ as the first state signal is set to the “H” level, and SR ₁ as the first release command signal is set to the “L” level while SR ₁ rises. When it goes up, XQ _{1 is set} to “L” level. NAND7 sets XQ ₁ to XQ ₁ ′ while SI ₁ = “H”
As it is, let it pass. First command means 2 is constituted by serially connecting an even number of INV2a～2n, and outputs the SR ₁ delays the XQ 'by a predetermined delay time Td ₁ corresponding to the number of connections INV. The second holding means 3 has two NANDs 3a and 3b, and SR
A latch, and the SR latch serves as a second input signal SI ₂
In the initial state where is applied to the input at the “L” level, XQ ₂ as the second state signal is set to the “H” level, and SR ₂ as the second release command signal is at the “L” level. If SI ₂ rises while being applied to the input, XQ _{2 is set} to “L” level. Inhibiting means 4 to pass through as SI ₂ = "H" and XQ ₁ '= "H" as XQ ₂ the XQ ₂ in terms of', if XQ ₁ '
When = “L”, fix XQ ₂ ′ to “H”. That is,
In this case, the passage of XQ ₂ is prohibited. The second command means 5 is configured by connecting an even number of INVs 5a to 5n in series, and XQ ₂ ′ is set to IN.
SR _{2 after} delaying a predetermined delay time Td ₂ according to the number of V connections
Output as. The third holding means 6 has two NANDs 6a and 6b.
Has S-R latch constituted by, S-R latch by changing the logic state of the internal at the rising edge of XQ ₁ 'applied to the input output SO = "H", also in the input At the falling edge of the added XQ ₂ ′, the internal logic state is inverted and SO = “L” is output.

The circuit operation will be described below with reference to the timing chart of FIG. First, the two input signals, namely SI ₁ and S
Pay attention to the section X when the rising edges of I ₂ are input with a sufficient time difference. At time t ₀ , when XQ ₁ changes from “H” to “L” at the rising edge of SI ₁ , XQ ₁ ′ also changes to “H”.
→ It changes to “L”, the third holding means 6 is set, and SO
Becomes "H".

During this period, the change of XQ ₁ ′ from “H” to “L” is caused by the first command means 2
At t ₁ after a predetermined delay time Td ₁ has passed through each INV in sequence, SR ₁ changes from “H” to “L”. Then, the SR ₁ resets the first holding means 1 and XQ ₁ = “H”, and therefore XQ ₁ ′ = “H”,
XQ ₁ ′ is generated as a negative gate of width Td ₁ starting from the rising edge of SI ₁ .

On the other hand, at t ₂ , XQ ₂ goes “H” at the rising edge of SI ₂ →
When it changes to "L", SI ₂ = "H", XQ ₁ '= "H" at this time
Therefore, XQ ₂ ′ also changes from “H” to “L”, the third holding means 6 is reset, and SO becomes “L”.

During this time, XQ ₂ 'of "H" → "L" changes continue to successively pass through each INV of the second instruction means 5, a predetermined delay time t ₂ Td ₂
At time t ₃ after the passage of time, SR ₂ changes from “H” to “L”. And this by SR ₂ second holding means 3 is reset, XQ ₂ = "H", therefore, XQ ₂ '= "H" next to, XQ _2' width Td ₂ originating from the rising edge of the SI ₂ Is generated as a negative gate of.

Next, pay attention to the section Y which is the point of the present invention when the rising edges of SI ₁ and SI ₂ are input very close to each other. From t _{4 to} t ₆ , when SI ₁ rises, XQ ₁ ′ is generated as a negative gate having a width Td ₁ as in the section X described above.
When SI ₂ rises at t ₅ within this width Td ₁ , “H” of XQ ₂
→ Until "L" change, it is performed in the same way as in the above section X,
At this t ₅ , since XQ ₁ ′ = “L”, passage through the prohibiting means 4 is prohibited, and XQ ₂ ′ is fixed at “H”. Then, at t ₆ when Td ₁ has elapsed, at the same time as XQ ₁ ′ = “H”, passage of the prohibiting means 4 is permitted, and XQ ₂ ′ changes from “H” to “L”.
, And at T ₇ which is Td ₂ after this change, X
Q ₂ ′ changes from “L” to “H”. Ie SI ₁ and S
When the rising edge of I ₂ is extremely close (within Td ₁ ), the negative gate generation of XQ ₂ ′ accompanying the rising edge of SI ₂ is
'It becomes a negative gate generation of wait until the completion, XQ _{1' 1} and XQ ₂ negative gate will not be overlapping '.

Thus, in this embodiment, the first holding means 1 and the second holding means
Each of the holding means 3 is self-restored with a delay time of Td ₁ , Td ₂ , and the second holding means 3 is self-restoring until the first holding means 1 is self-restored. Therefore, if the rise of SI ₁ and SI ₂ are in close proximity (within Td _1), SO is set at t ₄ is a rising timing of the SI _1, further from the rise timing of the SI ₁ Td ₁ after the t _Since it is reset at ₆ , correct SO and stable SO according to SI ₁ , SI ₂
Can be output. Further, in the present embodiment, since sampling or the like is not required, a sampling clock is not required, so that the circuit scale can be reduced. Further, in the present embodiment, when SI ₁ and SI ₂ are input at a distance of Td ₁ or more, SO becomes SI ₁ and S.
Responds in real time to the I _2, also, even if the SI ₁ and SI ₂ has become less than Td ₁ close, only generated slight response delay, minus their close time from Td _1. Moreover,
This response delay can be further reduced by appropriately adjusting the number of INVs in the first command means 2. Therefore, the responsiveness can be remarkably improved as compared with the case of using the sampling clock.

〔The invention's effect〕

According to the present invention, an edge detection circuit that receives two input signals in which at least one logic level changes asynchronously,
It can be realized with a small circuit scale and high responsiveness.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIGS. 2 and 3 are diagrams showing an embodiment of the present invention, FIG. 2 is a circuit diagram thereof, and FIG. 3 is a timing for explaining the circuit operation. It is a chart. 1 ... 1st holding means, 2 ... 1st command means, 3 ... 2nd holding means, 4 ... prohibition means, 5 ... 2nd command means, 6 ... 3rd holding means .

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hidenori Tobita, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Microcomputer Systems Limited (56) Reference JP 62-219711 (JP, A)

Claims (1)

[Claims] 1. An internal logic state is changed in response to an edge of a first input signal, the logic state is held until a predetermined first release command is input, and the held logic state is maintained. First holding means (1) for outputting a corresponding first status signal, and first command means (2) for delaying the first status signal for a predetermined time and then outputting it as a first cancellation command. And changing the internal logic state in response to the edge of the second input signal, holding the logic state until a predetermined second release command is input, and changing the internal logic state according to the held logic state. A second holding means (3) for outputting a second status signal, and a second status signal normally passed therethrough, and the second status signal is prohibited from passing while the first status signal is being output. And a second state signal that has passed through the prohibiting means (4). 2nd command means (5) which outputs as a 2nd cancellation | release command after delaying for the time of, and internal logic state was changed in response to the said 1st state signal, this logic state passed the prohibition means. An edge detection circuit comprising: a third holding means (6) for holding the second state signal until receiving the second state signal and outputting an output signal according to the logic state.