JPH0778962B2 - DAI demodulation circuit - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a DAI for demodulating a digital audio interface (DAI) signal used for exchanging data signals between digital audio devices such as CDs and R-DATs. The present invention relates to a demodulation circuit.

[Technical background of the invention and its problems]

Digital audio devices such as CD and DAT use different signal processing formats. As described above, the DAI signal format is defined by the standard in order to enable the exchange of data signals between devices having different signal processing formats.

FIG. 4 shows the frame format of the standardized DAI signal. In the figure, 192 frames form one block, each frame consists of two subframes, and each subframe has the format shown in FIG. As shown, it is composed of 32 time slots including a preamble sync signal assigned to 4 time slots, subcode data assigned to 8 time slots, PCM audio data assigned to 16 time slots, and the remaining 4 time slots. U of the remaining time slots is a user's bit, C is a channel status bit, and P is a parity bit. Of these, user's bit U,
The channel status bit C is used in units of one block, and the parity bit P is used in units of subframes.

As the preamble sync signal, there are three types of patterns of B, W, and M. B is the beginning ch1 of the block, M is the beginning ch1 of the block, W is the beginning of the subframe of ch2, 3 ... Each of them has a pattern as shown in FIG. Also, NRZ "1" and "0" are the 7th
As shown in the figure, they are modulated by T and 2T biphase patterns, respectively.

As a circuit that modulates the DAI signal as described above,
The one shown in the figure was used.

In the figure, 1 is a signal input terminal to which a biphase-modulated DAI signal is input, and 2 is a biphase demodulator that demodulates the DAI signal input to the signal input terminal 1,
The demodulated NRZ signal is output at its output by bi-phase demodulation. A U-bit data latch 3 extracts and latches only the U-bit data in the demodulated NRZ signal, and outputs the extracted U-bit data to its output.

A block sync detector 4 detects the block sync portion of the CDSUB code from the U-bit data from the U-bit data latch 3, and outputs a block sync signal to its output a. A frame sync detector 5 detects a frame sync portion in the U-bit data from the U-bit data latch 3, and outputs a frame sync signal to its output b. Reference numeral 6 is a SUB code register for extracting and shifting SUB code data (Q to W) from the U-bit data from the U-bit latch 3 by a clock from the shift lock input terminal C and outputting the SUB code data at its output d. Shift out code data.

Block sync signal from the block sync detector 4, frame sync signal from the frame sync detector 5, and SU
The SUB code data from the B code register 6 is input to and processed by the CPU 7 to generate a SUB code ID based on the SUB code data.

By the way, when the digital audio device transmitting the DAI signal is a CD player, the transmission format of the DAI signal is as shown in FIG. In the figure, N
o is a subframe number, 12 subframes correspond to one frame of CD format, and 8 bits of user bits of CD format are U of each subframe of DAI signal.
-The bits are inserted in order. Then, a block sync is represented by inserting 0s into U-bits of 16 or more subframes, and 1, Q, R, S, T, U, V from the beginning every 12 U-bits thereafter. It is designed to insert W. Note that U-bit 1 indicates a CD format frame sync, and Q indicates audio information such as presence or absence of emphasis and copy inhibition.
Information for image data is inserted into W, respectively.

As described above, the U-bit data latch 3 latches the U-bit in the DAI signal and uses this as U-bit data as the block sync detector 4, the frame sync detector 5, and
It is sent to the SUB code register 6. In response to this, when the block sync detector 4 detects that the U-bits of 16 or more subframes are continuously 0, it is regarded as a block sync and its output a is as shown in FIG. 10 (a). Na L
Output level block sync signal. When the frame sync detector 5 detects 1 inserted in the U-bit for every 12 subframes, it outputs an L level frame sync signal as shown in FIG. 10 (b) to this output b. . Further, the SUB code register 6 takes in the SUB codes Q to W in the U-bit data and stores them in the tenth code from the CPU7.
It is shifted by a clock as shown in FIG. 10 (c), and is output to its output d as SUB code data as shown in FIG. 10 (d).

The CPU 7 that inputs the signals and data as described above executes the work shown in the flowchart of FIG. 11 according to a predetermined control program.

That is, the CPU 7 starts its work when the demodulation circuit receives the DAI signal, waits for the block sync signal to change from the L level to the H level in the first step S1, and when the determination in the step S1 is YES, the step Go to S2,
Here, it waits for the frame sync signal to change from H level to L level. If the determination in step S2 is YES, then step S2
Proceeding to 3, the shift clock is generated and applied to the SUB code register 6 here. After that, the process proceeds to step S4, and the SUB code data from the SUB code register 6 is fetched. Succeedingly, in a step S5, only the "Q" bit is extracted from the SUB code data fetched here, is stored in a RAM (not shown) in the next step S6, and is used thereafter.

The conventional circuit is configured as described above and outputs all of Q to W as SUB code data, but in reality, the time information and control signal information required are Q to W. Of these, only "Q", and in most cases, image information SW is not required. Also, the image information R to W is Q.
Since it is output together with, the data rate increases,
The load on the CPU that takes in data increases accordingly. For this reason, it becomes a constraint when trying to add more features to the digital audio device to which the DAI demodulation circuit as described above is added, and trying to make the CPU as the system control microcomputer do more work. It was

[Object of the Invention]

The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional ones, and makes the data easy to handle and reduces the data rate to reduce the load on the CPU, or expands in the future. The purpose is to provide a DAI demodulation circuit that is effective for holding.

〔Overview〕

DAI demodulation circuit made to achieve the above object, preamble signal and user's bits are added to the digital audio signal, bi-phase demodulated the transmitted digital audio interface signal by the bi-phase modulation, the demodulated signal By selecting and outputting either the extracted user's bit or the extracted specific bit from the extracted user's bit, the system control microcomputer that performs data processing identifies the specific bit of this output. Since there is no need to do the work of extracting the bit of, the burden is reduced by that amount, and the user's bit of the output can be received,
The expandability of equipment using this circuit is also maintained.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 11 is a bi-phase modulated DAI.
Signal input terminal to which a signal is input, 12 is a timing generator for generating a clock synchronized with the sub-frame based on the DAI signal inputted to the signal input terminal 11, 2F its output a _S (F _S: sampling frequency) Output the clock. A biphase demodulator 13 biphase demodulates the DAI signal input to the signal input terminal 11, and outputs a demodulated NRZ signal to its output. 14 is U of the demodulated NRZ signal
A U-bit data latch as a first extracting means for extracting and latching only bit data, and outputs the extracted U-bit data to its output b.

A block sync detector 15 detects the block sync part of the CDSUB code in the U-bit data from the U-bit data latch 14, and outputs a block sync signal to its output c. Reference numeral 16 is a frame sync detector for detecting the frame sync portion of the CDSUB code of the U-bit data from the U-bit data latch 14, and its output d
The frame sync signal is output to. Reference numeral 17 is a SUB code Q detector as a second extracting means for extracting only the "Q" beat in the U-bit data from the U-bit data latch 14, and outputs the SUB code Q data to its output e. .

18 is the timing generator being fed to its input
A clock changeover switch that selects and outputs one of the clock from 12 or the frame sync signal from the frame sync detector 16, and outputs a clock composed of either the clock or the frame sync signal to its output. 19 is U-bit data from the U-bit latch 14 supplied to its input or SUB code Q from the SUB code Q detector 17.
SUB as an output means for selecting and outputting one of the data
It is a code data switch, and outputs SUB code data consisting of either U-bit data or SUB code Q data to its output.

The block sync signal from the block sync detector 15, the clock from the clock switch 18 and the SUB code data from the SUB code data switch 19 are input to the CPU 20 which generates SUB code information from the SUB code data and processed.

The clock switch 18 and the SUB code data switch 19 are switched depending on whether all SUB code data is output or only Q is output, and the control thereof is performed by the CPU 20.
Done by

In the above configuration, the output a of the timing generator 12, but 2F _S clock as shown in FIG. 2 (a) is output, which sub-frame as is clear from DAI signal format shown in FIG. 5 This is because 1 bit is assigned to the U-bit and the frequency of the subframe is 2F _S , and therefore 2F _S is required as a clock for outputting the U-bit every time.

The biphase demodulator 13 biphase demodulates the DAI signal and outputs it as a demodulated NRZ signal. The U-bit data latch 14 to which this series of demodulated NRZ signals is input extracts and takes in only one bit assigned to the U-bit, and outputs the U-bit as shown in FIG. 2 (b). -Output as bit data.

The block sync detector 15 detects a section in which "0" continues 16 times or more in the U-bit data, and outputs it as a block sync signal as shown in FIG. 2 (c) at its output c. The frame sync detector 16 detects "0" following "0" in the U-bit data and outputs this to the output d as the second
It is output as a frame sync signal as shown in FIG. The SUB code Q detector 17 extracts only "Q" bits from the U-bit data and outputs it as SUB code data as shown in FIG. 2 (e) at its output e.

Clock switch 18 and SUB code data switch 1
9 is switched synchronously, and all U-bit data is
When outputting as code data, the clock shown in FIG. 2 (a) is output from the output a of the timing generator 12, and when outputting only "Q" of U-bit data, the clock from the output d of the frame sync detector 16 is output. Figure 2 (d)
A frame sync signal as shown in is output.

The CPU 20 for inputting the signals and data as described above executes the work shown in the flowchart of FIG. 3 according to a predetermined control program.

That is, the CPU 20 starts its work when the demodulation circuit receives the DAI signal, and at the first step S1, U-
Whether or not to input all bit data as SUB code data is determined by a signal from an operation unit (not shown) or the like. If the determination in step S1 is NO, the process proceeds to step S2, and waits until the block sync signal changes from L level to H level. If the determination in step S2 is YES, step S2 is performed.
Go to 3. In step S3, it waits for the frame sync signal to change from H level to L level, and when the determination in step S3 is YES, the process proceeds to step S4. In step S4, the "Q" data input through the SUB code data switch 19 is fetched and stored in RAM in the next step S5.

On the other hand, if the determination in step S1 is YES, step S6
The process proceeds, here taking the U- bit data inputted through the SUB code data switch 19 in the clock 2F _S being inputted via the clock change-over switch 18. Thereafter, in step S7, the block sync signal is extracted, and in step S8, the frame sync signal is extracted.
Extract W data. The extracted Q to W data is stored in the RAM in the next step S10. The data stored in RAM is used for subsequent ID generation.

[Effect]

As described above, according to the present invention, the user's bit extracted by the first extracting means or the specific bit extracted by the second extracting means from the user's bit is output. When the bits of (1) are output, the handling of the user's bits is facilitated, the data rate is lowered, and the load on the syscon that performs data processing for receiving the user's bits can be reduced. Also, when the extracted user's bits are output, any signal source can be supported, so it is possible to handle whatever data is inserted in the user's bits and transmitted in the future. However, the expandability of equipment using this circuit is also maintained.

[Brief description of drawings]

FIG. 1 is a block diagram of an electric circuit showing an embodiment of the present invention, FIG. 2 is a timing chart showing signals of respective parts in FIG. 1, and FIG. 3 is a flow chart showing work of the CPU in FIG. Fig. 4, Fig. 4 is a diagram showing the format of the DAI signal, Fig. 5 is a diagram showing the format of the sub-frame in Fig. 4, Fig. 6 is a diagram showing the pattern of the preamble sync signal in Fig. 4, FIG. 7 is a diagram showing a method of bi-phase modulation of a DAI signal, FIG. 8 is a block diagram of an electric circuit showing a conventional example, FIG. 9 is a diagram showing a format of a DAI signal from a CD player, and FIG. FIG. 11 is a timing chart showing the signals of the respective parts in the figure, and FIG. 11 is a flow chart showing the work of the CPU in FIG. 13 ... Bi-phase demodulator, 14 ... U-bit data latch (first extracting means), 17 ... SUB code Q detector (second extracting means), 19 ... SUB code data switch ( Output means).

Front page continuation (72) Hiroo Okamoto Inventor Hiroo Okamoto 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Home Appliances Research Institute, Hitachi, Ltd. (72) Inventor Yuji Hatanaka 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa In the laboratory (56) Reference JP 62-22277 (JP, A) JP 62-107473 (JP, A)

Claims (2)

[Claims] 1. A demodulation circuit that adds a preamble signal and a user's bit to a digital audio signal, and demodulates the transmitted digital audio interface signal by biphase modulation. Biphase for biphase demodulating the digital audio interface signal Demodulation means, first extracting means for extracting the user's bits from the signal demodulated by the bi-phase demodulating means, and extracting a specific bit from the user's bits extracted by the first extracting means A DAI demodulation circuit comprising: a second extracting means for outputting; and an output means for selecting and outputting one of the first extracting means or the second extracting means. 2. The second extracting means extracts and outputs bit data corresponding to a CD player from the user's bits when the output source of the digital audio interface signal is a CD player. The DAI demodulation circuit according to claim 1.