JPH077895B2 - Variable gain amplifier - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier, and more particularly to a variable gain amplifier that amplifies a multilevel baseband signal obtained by demodulating a modulated wave of a digital carrier transmission system.

[Conventional technology]

A variable gain amplifier that amplifies a multilevel baseband signal obtained by demodulating a modulated wave of a digital carrier transmission system requires a constant gain from the DC component to the frequency corresponding to the band of the multilevel baseband signal. Generally, a direct-coupled amplifier is used.

FIG. 2 is a circuit diagram showing an example of a conventional variable gain amplifier.

In this figure, the demodulated multilevel baseband signal is
Input signals having a phase difference of 180 ° are input to the input terminals 14 and 15, respectively. At this time, the transistor 5
A signal having a phase opposite to that of the input signal of the input terminal 14 appears at the collector of, and a signal of the positive phase appears at the collector of the transistor 6. That is, the transistors 5 and 6 operate as a differential amplifier having the transistors 1, 2 and 3, 4 as loads.

Transistors 1 to 4 operate as four base-grounded amplifiers to which the negative-phase and positive-phase signals appearing at the collectors of transistors 5 and 6 are input, but in the configuration of this figure, transistors 1 and 3 and transistor 2 Since the collectors of 4 and 4 are connected to each other, the signal appearing at the output terminals 16 and 17 is a combination of the negative-phase and positive-phase signals appearing at the collectors of the transistors 5 and 6.

Now, the bias voltage V ₁₂ applied to the gain control terminals 12 and 13
Considering the case where V ₁₃ is V ₁₂ >> V ₁₃ , and the transistors 2 and 3 are cut off, no signal appears at the collectors of the transistors 2 and 3, and the transistors at the output terminals 16 and 17 are
The same signal that appears at the collectors of 1,4 is output, and the gain is largely determined by the current flowing through resistors 7-9 and transistors 5,6.

Also, when V ₁₂ << V ₁₃ and the transistors 1 and 4 are cut off, the same signal that appears at the collectors of the transistors 2 and 3 is output from the output terminals 16 and 17 contrary to the above case, and the amplitude The gain is the same as when V ₁₂ >> V ₁₃ .

When comparing the cases of the V ₁₂ «V ₁₃ of V ₁₂ >> V _13, the amplitude of the output signal is the same in each case Izure phase to the input signal is different 180 °. That is, when V ₁₂ >> V ₁₃ and the transistors 2 and 3 are cut off, the output signal of the output terminal 16 is in the opposite phase to the input signal of the input terminal 14, and the output signal of the output terminal 17 is in the positive phase. Also,
When V ₁₂ << V ₁₃ and the transistors 1 and 4 are cut off, the output terminal 16 outputs a positive phase output signal and the output terminal 17 outputs a negative phase output signal.

Further, when V ₁₂ = V ₁₃ and the transistors 1 and 2 and the transistors 3 and 4 have the same amplification factor, the positive and negative phase signals cancel each other out at the output terminals 16 and 17. No signal appears and the gain of the amplifier becomes infinitesimally small.

As described above, the conventional amplifier has the gain control terminal 12 and the terminal
By adjusting the potential difference of the bias voltage applied to 13, it is possible to change the gain from a finite gain to an infinitely small gain, so that it operates as a variable gain amplifier.

However, as mentioned above, V ₁₂ >> V ₁₃ and V ₁₂
≪The output phase is inverted in the case of V ₁₃ , which means that even if the transistor 2, 3 or 1, 4 is not cut off, V ₁₂
With the boundary of = V ₁₃ , the output phase is inverted in the states of V ₁₂ > V ₁₃ and V ₁₂ <V ₁₃ .

Therefore, to prevent phase inversion, V ₁₂ ≧ V ₁₃
Or, so that only one of V ₁₂ ≤ V ₁₃ can be taken,
Although it is necessary to add a voltage limiting circuit to the gain control terminal 12 or 13, the change in gain with respect to the potential difference between the gain control terminals 12 and 13 and the phase inversion phenomenon are due to the base-emitter diode characteristics of the transistors 1 to 4, It shows a sudden change with respect to the change of the potential difference.

Therefore, the voltage limiting circuit to be added becomes large-scale and complicated and is not practical.

[Problems to be Solved by the Invention]

As described above, the conventional amplifier can operate as a variable gain amplifier, but since the output phase is inverted by the bias voltage that determines the gain, the variable gain amplifier that amplifies the demodulated baseband signal of the digital carrier transmission system. Is unsuitable as

It is an object of the present invention to provide a variable gain amplifier which can be used as a variable gain amplifier for amplifying this type of baseband signal and which prevents output phase inversion.

[Means for Solving the Problems]

The variable gain amplifier of the present invention has different gains,
Also, a pair of first and second transistors for synthesizing and outputting collector signals having an antiphase relationship, a base-grounded amplifier serving as a load for these transistor pairs to improve frequency characteristics, and a direct current as a constant current source for each pair of transistors. It is provided with a third transistor pair with a voltage limiting circuit for controlling the value of current and a constant current source.

[Action]

In this configuration, a difference occurs in the gains of the first and second transistor pairs, and the voltage limiting circuit that limits the gain control voltage prevents the output phase from being inverted by the gain control voltage.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of a variable gain amplifier of the present invention. In the figure, reference numerals 19 and 20 denote transistors each having a multi-valued baseband signal as an input and having emitter resistors 29 and 30, which form a first transistor pair. Further, 21 and 22 are transistors having the same signal as that of the first transistor pair as an input and having emitter resistors 31 and 32 having different values from the emitter resistors 29 and 30, respectively. Constitute. Each collector of the first and second transistor pairs cross-connects the transistors 19, 20 and 21, 22 with each other and outputs a collector combined output signal in antiphase. Then, each collector is connected to a base-grounded amplifier composed of two transistors 25 and 26 to which the combined output signal is input. A third transistor pair composed of transistors 23 and 24 is connected to the emitters of the first and second transistor pairs, respectively. This third transistor pair has voltage control diodes 27 and 28,
It is configured as a constant current source having a voltage limiting circuit that prevents one base potential from becoming lower than the other base potential.
Further, each transistor 2 of this third transistor pair
A constant current source 9 is connected to the emitters of 3,24 via resistors 33,34.

Note that 37 is a constant voltage source, 38 and 39 are input terminals, 40 and 41 are output terminals, 44 is a gain control terminal, 45 is a bias terminal, and 18 is a power supply terminal.

In this configuration, the input signals input from the input terminals 38 and 39 are assumed to be 180 degrees out of phase with the signal at the input terminal 39 as in the conventional case.

The input signals input from the input terminals 38 and 39 are respectively amplified by the first transistor pair (transistors 19 and 20) and the second transistor pair (transistors 21 and 22). Since the collectors of the transistors 20 and 22 are connected, the signals obtained by combining the signals amplified by the first and second transistor pairs are input to the emitters of the transistors 25 and 26.

The transistors 25 and 26 improve the frequency characteristic of the amplifier,
Broaden the band. That is, since the input impedances considering the emitters of the transistors 25 and 26 are sufficiently low, the product of the combined collector capacitance of the transistors 19 and 21 and the transistors 20 and 21 and the input impedance of the transistors 25 and 26 is the transistors 19 and 21, and It is smaller than the product of the combined collector capacitance of the transistors 20 and 21 and the load resistors 42 and 43, and the band of the amplifier can be widened.

Now, the bias voltage V ₄₄ given to the gain control terminal ₄₄ is
If sufficiently higher than the voltage V ₃₇ of the constant voltage source 37, since the diode 27 for voltage control in an open equivalent, transistor
The bias voltage V ₄₄ is directly applied to the base of 23. On the other hand, the base voltage of the transistor 24 is V ₃₇ −V _D when the operating voltage of the diode 28 is V _D , regardless of the voltage V ₄₄ of the gain control terminal 44.

Therefore, when V ₄₄ >> V ₃₇ −V _D and the transistor 24 is cut off, no current flows in the transistor 24,
Since no current flows through the transistors 21 and 22, the collector of the second transistor pair is equivalent to open.

Therefore, the signal appearing at the output terminals 40 and 41 is a signal amplified by the gain which is generally determined by the first transistor pair, the emitter resistors 29 and 30, the load resistors 42 and 43, and the flowing current value. At this time, with respect to the phase of the input signal of the input terminal 38, the output terminal 40 has a reverse phase signal and the output terminal 41 has a positive phase signal.

Next, when V ₄₄ = V ₃₇ −V _D , equal currents flow through the transistors 23 and 24, so that the first and second transistor pairs are input with gains determined by the emitter resistance and the negative resistance and the flowing current. Although the signal is amplified, since the collectors of the transistors 19 and 21 and the transistors 20 and 22 are connected as described above, the output terminals 40 and 41 are connected to the first
A signal obtained by combining the signals amplified by the first and second transistor pairs appears.

At this time, if the emitter resistors 29, 30, 31, 32 all have the same resistance value, the combined signals of the positive and negative phases cancel each other, so that no output signal appears at the output terminals 40 and 41.
_{If 29} = R ₃₀ <R ₃₁ = R ₃₂ , the gain of the first transistor pair becomes larger than the gain of the second transistor pair, and as a result, the gain of the first transistor pair and the gain of the second transistor pair. A signal amplified by the gain of the difference of is output from the output terminals 40 and 41.

In the above description, the rate of change of gain with respect to the voltage of the gain control terminal 44, that is, the gain control sensitivity, is
It can be changed by the emitter resistance of the third transistor pair of 4. Therefore, it is possible to set the sensitivity to a level sufficient to activate the voltage limiting circuit.

In addition, the voltage V _{44 at} the gain control terminal 44 becomes even lower, and V ₄₄
If a «V ₃₇ -V _D, since the voltage limiting diode 27 becomes conductive, the base potential of the transistor 23 is V ₃₇ -V
_It does not go below _D , ie the base potential of transistor 24. Also, diodes 27 and 28 and transistors 23 and 24
Even if the current flowing through the transistor 23 is slightly reduced by the current flowing through the transistor 24 due to a mismatch in the characteristics of the first transistor pair and the like, the gain of the first transistor pair is different from that of the first transistor pair. Unless the current flowing through the transistor 23 is reduced to such an extent that the gain is equal to or lower than the gain of the second transistor pair, the output phase is not inverted or the gain is infinitely small.

In general, when transistors and diodes of the same standard are used, the above-mentioned mismatch in characteristics is so small that it can be ignored, so that the output phase is not inverted. Increasing,
When the circuit of the present invention is implemented as an LSI, the matching of each element is extremely improved, and the phenomenon of phase inversion as described above does not occur.

In the above description, the case where the gain of the first transistor pair is larger than that of the second transistor pair has been described. However, conversely, the case where the gain of the second transistor pair is larger than that of the first transistor pair is essential. However, the phase of the output signal is reversed and the polarity of the voltage limiting diode may be reversed.

Further, in this embodiment, the positive power supply voltage is applied to the power supply terminal 18, but the power supply terminal 18 is grounded,
It is clear that the circuit does not change essentially even if the ground of FIG. 1 is used as a negative power source.

〔The invention's effect〕

As described above, according to the present invention, the outputs of the first transistor pair and the second transistor pair having different gains are combined, and the frequency characteristic is improved by the grounded base amplifier. Further, the first and second transistors are combined. Since the voltage limiting circuit is provided in the third transistor pair capable of controlling the direct current of the pair to control the gain, a variable gain amplifier capable of changing the gain without the output phase being inverted by the gain control voltage is provided. Can be configured. Further, in this configuration, since a circuit can be basically constituted by a transistor and a resistor without using a coupling capacitor or the like, a monolithic IC can be easily formed, and an amplifier can be downsized and highly integrated.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional variable gain amplifier. 1 to 6 ... transistor, 7,8 ... resistor, 9 ... constant current source, 10,11 ... resistor, 12,13 ... gain control terminal, 14,15 ...
… Input terminal, 16,17 …… Output terminal, 18 …… Power supply terminal, 19,
20 ... Transistor (first transistor pair), 21,22
...... Transistor (second transistor pair), 23,24 …… Transistor (grounded base amplifier), 25,26…
… Transistors (third transistor pair), 27, 28 ……
Voltage control diode, 29 to 39 ... resistance, 37 ... constant voltage source, 38, 39 ... input terminal, 40, 41 ... output terminal, 42, 43 ... load resistance, 44 ... gain control terminal, 45 …… Bias terminal.

Claims (1)

[Claims] 1. A variable gain amplifier for amplifying a multilevel baseband signal obtained by demodulating a modulated wave of a digital carrier transmission system, comprising: a first transistor pair having a multilevel baseband signal as an input and having an emitter resistance. , This first
A second transistor pair, which receives the same signal as the transistor pair and has an emitter resistance having a value different from that of the first transistor pair, and a collector output signal of the first and second transistor pairs, which are in an opposite phase relationship to each other, Two base-grounded amplifiers each having a combined signal as an input;
And a third transistor pair having a voltage limiting circuit that serves as a constant current source for the second transistor pair and prevents the base potential of one from becoming lower than the base potential of the other, and a current is passed through a resistor through each transistor of the third transistor pair. And a constant current source for supplying the variable gain amplifier.