JPH0778937A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0778937A JPH0778937A JP5224317A JP22431793A JPH0778937A JP H0778937 A JPH0778937 A JP H0778937A JP 5224317 A JP5224317 A JP 5224317A JP 22431793 A JP22431793 A JP 22431793A JP H0778937 A JPH0778937 A JP H0778937A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- chip
- lead
- semiconductor device
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に係わり、特にリードフレームに半導体チップを
搭載した半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a semiconductor chip mounted on a lead frame and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】リードフレームのチップ搭載部（アイラ
ンド部）の片面に１個もしくは複数個の半導体チップを
搭載し樹脂で封止した半導体装置は広く用いられてい
る。2. Description of the Related Art A semiconductor device in which one or a plurality of semiconductor chips are mounted on one surface of a chip mounting portion (island portion) of a lead frame and sealed with resin is widely used.
【０００３】一方、図４に示すように、１つのリードフ
レーム１のチップ搭載部１１の上面および下面に半導体
集積回路チップ２，２’をそれぞれ搭載固着し、半導体
チップ２の電極と内部リード（インナーリード）１２の
上面とをボンディング細線３で接続し、半導体チップ
２’の電極と内部リード１２の下面とをボンディング細
線３’で接続し、樹脂７で全体を封止する構造が実装密
度を高めた半導体集積回路装置として、例えば、特開平
１−２２０８３７号公報もしくは特開平２−２０９７６
１号公報に開示されてある。On the other hand, as shown in FIG. 4, semiconductor integrated circuit chips 2 and 2'are mounted and fixed on the upper surface and the lower surface of the chip mounting portion 11 of one lead frame 1, respectively, and the electrodes of the semiconductor chip 2 and internal leads ( The upper surface of the inner lead) 12 is connected with the bonding thin wire 3, the electrode of the semiconductor chip 2 ′ and the lower surface of the inner lead 12 are connected with the bonding thin wire 3 ′, and the structure in which the whole is sealed with the resin 7 reduces the mounting density. As an improved semiconductor integrated circuit device, for example, Japanese Patent Application Laid-Open No. 1-220837 or Japanese Patent Application Laid-Open No. 2-20976.
It is disclosed in Japanese Patent Publication No.
【０００４】[0004]
【発明が解決しようとする課題】上述した従来の個別半
導体装置において、リードフレームの片方の面のみに半
導体チップを搭載している構造では、パッケージの寸法
（封止樹脂の外形寸法）が半導体チップの面積の大きさ
で制限されてパッケージの小型化が困難となる。また、
表面実装パッケージにおける電流容量の大きな半導体チ
ップの搭載や単一パッケージ内での複数の半導体チップ
による複合接続搭載も困難となる。In the conventional individual semiconductor device described above, in the structure in which the semiconductor chip is mounted only on one surface of the lead frame, the size of the package (outer dimension of the sealing resin) is the semiconductor chip. The size of the package makes it difficult to miniaturize the package. Also,
It is also difficult to mount a semiconductor chip having a large current capacity in a surface mount package or mount a composite connection of a plurality of semiconductor chips in a single package.
【０００５】一方、図４に示す半導体集積回路装置で
は、１つのリードフレームのチップ搭載部の上面および
下面の両面にそれぞれ半導体チップを搭載する構造とな
っているので、製造方法上、リードフレームへ半導体チ
ップを搭載するチップマウント作業や搭載された半導体
チップの電極と各内部リード間をボンディング細線で接
続するワイヤーボンディング作業とを同一のリードフレ
ームの上面側および下面側の両方に実施する必要があ
る。このために製造工程が複雑となり、工程数の増加あ
るいはマウンター、ボンダー、搬送等で特殊な構造の設
備が必要となり、製造コストや製造技術上の大きな問題
があった。On the other hand, the semiconductor integrated circuit device shown in FIG. 4 has a structure in which semiconductor chips are mounted on both upper and lower surfaces of the chip mounting portion of one lead frame. It is necessary to perform chip mounting work for mounting the semiconductor chip and wire bonding work for connecting the electrodes of the mounted semiconductor chip and each internal lead with a bonding thin wire on both the upper surface side and the lower surface side of the same lead frame. . This complicates the manufacturing process, increases the number of processes, and requires equipment with a special structure such as a mounter, a bonder, and a conveyor, which poses a serious problem in manufacturing cost and manufacturing technology.
【０００６】本発明の目的は、上記従来技術の欠点を除
去した有効な半導体装置及びその製造方法を提供するこ
とである。An object of the present invention is to provide an effective semiconductor device and a method for manufacturing the same, in which the above-mentioned drawbacks of the prior art are eliminated.
【０００７】[0007]
【課題を解決するための手段】本発明の特徴は、第１の
リードフレームのチップ搭載部の一主表面上に第１の半
導体チップを固着し、前記第１の半導体チップと前記第
１のリードフレームの内部リード間をボンディング細線
で接続し、第２のリードフレームのチップ搭載部の一主
表面上に第２の半導体チップを固着し、前記第２の半導
体チップと前記第２のリードフレームの内部リード間を
ボンディング細線で接続し、前記第１および第２のリー
ドフレームのチップ搭載部の他主表面どうしを面接触さ
せ、前記第１および第２の半導体チップを一体的に樹脂
によりモールド封止した半導体装置にある。ここで他主
面どうしは接着材を介して面接触しこれにより両者は固
着されていることができる。また、前記第１および第２
の半導体チップはそれぞれバイポーラトランジスタであ
り、それらのコレクタが共通接続されてコレクタコモン
ダーリントン接続回路を構成することを可能とすること
ができる。あるいは、前記第１および第２の半導体チッ
プはそれぞれＮチャネルおよびＰチャネル型ＦＥＴであ
り、両者がコンプリーメンタリー接続されていることが
できる。A feature of the present invention is that a first semiconductor chip is fixed on one main surface of a chip mounting portion of a first lead frame, and the first semiconductor chip and the first semiconductor chip are bonded together. The inner leads of the lead frame are connected with a bonding thin wire, the second semiconductor chip is fixed on one main surface of the chip mounting portion of the second lead frame, and the second semiconductor chip and the second lead frame Of the inner leads of the first and second lead frames are brought into surface contact with each other on the chip mounting portions of the first and second lead frames, and the first and second semiconductor chips are integrally molded with resin. It is in a sealed semiconductor device. Here, the other main surfaces are brought into surface contact with each other via an adhesive material, so that the two can be fixed to each other. In addition, the first and second
The respective semiconductor chips are bipolar transistors, and their collectors can be commonly connected to form a collector-common Darlington connection circuit. Alternatively, the first and second semiconductor chips may be N-channel and P-channel FETs, respectively, and both may be connected in a complementary manner.
【０００８】本発明の他の特徴は、２枚のリードフレー
ムのチップ搭載部の一方の面にそれぞれ半導体チップを
マウントし、このマウントされた半導体チップとそれぞ
れのリードフレームの内部リード間をボンディング細線
で接続し、しかる後、前記半導体チップがたがいに反対
向きとなるように前記２枚のリードフレームのチップ搭
載部の他方の面どうしを面接触させ、この状態でこれら
の半導体チップを単一パッケージ内にモールドする半導
体装置の製造方法にある。ここで、前記他方の面どうし
の面接触は、モールド工程の前に接着材を介して両者を
固着して行うことができる。あるいは、前記他方の面ど
うしの面接触は、モールド工程の金型へのセットにおい
て行うことができる。Another feature of the present invention is that a semiconductor chip is mounted on one surface of the chip mounting portion of each of the two lead frames, and a thin bonding wire is provided between the mounted semiconductor chip and the internal lead of each lead frame. Then, the other surfaces of the chip mounting portions of the two lead frames are brought into surface contact so that the semiconductor chips are opposite to each other, and in this state, these semiconductor chips are packaged in a single package. This is a method of manufacturing a semiconductor device that is molded inside. Here, the surface contact between the other surfaces can be performed by fixing the two surfaces via an adhesive before the molding step. Alternatively, the surface contact between the other surfaces can be performed in the setting in the mold in the molding step.
【０００９】[0009]
【実施例】以下、図面を参照して本発明を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【００１０】図１は本発明の実施例の製造方法を示すフ
ローチャート（Ａ）および断面図（Ｂ）である。第１の
リードフレーム１のチップ搭載部（アイランド部）１１
の一方の主面（表面）上に第１の半導体チップ２を固着
搭載（第１のチップマウント工程）した後、、第１の半
導体チップ２の表面に形成されてあるボンディング電極
（図示省略、以下同じ）と第１のリードフレーム１の内
部リード（インナーリード）１２とをボンディング細線
３によりボンディング接続する（第１のワイヤーボンデ
ィング工程）。同様に、第２のリードフレーム１’のチ
ップ搭載部（アイランド部）１１’の一方の主面（表
面）上に第２の半導体チップ２’を固着搭載（第２のチ
ップマウント工程）した後、、第２の半導体チップ２’
の表面に形成されてあるボンディング電極と第２のリー
ドフレーム１’の内部リード（インナーリード）１２’
とをボンディング細線３’によりボンディング接続する
（第２のワイヤーボンディング工程）。FIG. 1 is a flow chart (A) and a sectional view (B) showing a manufacturing method of an embodiment of the present invention. Chip mounting portion (island portion) 11 of the first lead frame 1
After the first semiconductor chip 2 is fixedly mounted on one of the main surfaces (front surface) (first chip mounting step), a bonding electrode (not shown in the figure, which is formed on the surface of the first semiconductor chip 2 The same applies hereinafter) and the internal lead (inner lead) 12 of the first lead frame 1 are connected by bonding with the thin bonding wire 3 (first wire bonding step). Similarly, after the second semiconductor chip 2'is fixedly mounted on one main surface (front surface) of the chip mounting portion (island portion) 11 'of the second lead frame 1' (second chip mounting step) ,, second semiconductor chip 2 '
Of the bonding electrodes formed on the surface of the second lead frame 1'and the inner leads (inner leads) 12 'of the second lead frame 1'.
And are bonded to each other by a bonding thin wire 3 '(second wire bonding step).
【００１１】次に、第１および第２の半導体チップ２，
２’がたがいに反対向きになるように、第１のリードフ
レーム１のチップ搭載部１２の第１の半導体チップ２が
搭載されない方の他方の主面（裏面）と第２のリードフ
レーム１’のチップ搭載部１２’の第２の半導体チップ
２’が搭載されない方の他方の主面（裏面）とをはんだ
ペースト等の導電性接着材４により貼合せ積層する（リ
ードフレーム貼合せ工程）。Next, the first and second semiconductor chips 2,
The second lead frame 1 ′ and the other main surface (back surface) of the chip mounting portion 12 of the first lead frame 1 on which the first semiconductor chip 2 is not mounted are arranged so that 2 ′ is opposite to each other. The other main surface (back surface) of the chip mounting portion 12 'on which the second semiconductor chip 2'is not mounted is bonded and laminated with a conductive adhesive 4 such as a solder paste (lead frame bonding step).
【００１２】次に、樹脂封止工程において、封止金型の
キャビティ５の中に、貼合せられた２枚のリードフレー
ムの位置決め穴が金型の位置決めピンと合うようにセッ
トし、金型ゲート６および６’より樹脂供給を行い、樹
脂モールド７を行う。Next, in the resin encapsulation process, the two lead frames that are bonded together are set in the cavity 5 of the encapsulation mold so that the positioning holes of the two lead frames are aligned with the positioning pins of the mold, and the mold gate is set. The resin is supplied from 6 and 6 ', and the resin mold 7 is performed.
【００１３】あるいは、樹脂封止工程において金型へ各
リードフレームをそれぞれセットする際に両者の裏面ど
うしを面接触させることもできる。Alternatively, when the respective lead frames are set in the mold in the resin sealing step, the back surfaces of the two may be brought into surface contact with each other.
【００１４】この製造方法においては、２枚のリードフ
レームを用い、各々個別にリードフレームの片方の面に
チップマウント及びボンディング配線を行う製法となっ
ているので、従来と同じ設備、製法でワイヤボンディン
グ迄の加工が可能である。In this manufacturing method, since two lead frames are used and the chip mounting and the bonding wiring are individually performed on one surface of the lead frame, the wire bonding is performed by the same equipment and manufacturing method as the conventional one. Up to processing is possible.
【００１５】さらに、封止前又は封止工程でこれら２枚
のリードフレームの貼合せ積層を行うことで、同一パッ
ケージ内のリードフレーム対の上側及び下側の両面にそ
れぞれ半導体チップの搭載が可能になるから、図４の半
導体装置と同様に高密度実装が可能なものとなる。Further, by laminating and laminating these two lead frames before or during the sealing process, semiconductor chips can be mounted on both upper and lower surfaces of the lead frame pair in the same package. Therefore, high-density mounting is possible as in the semiconductor device of FIG.
【００１６】図２は、図１の実施例の製造方法により得
られた表面実装タイプのミニモールドパッケージに複合
接続素子を搭載した半導体装置を示す図であり、図２
（Ａ）は平面図、図２（Ｂ）は図２（Ａ）のＸ−Ｘ’部
の断面図、図２（Ｃ）は回路図である。FIG. 2 is a view showing a semiconductor device in which a composite connection element is mounted on a surface mount type mini mold package obtained by the manufacturing method of the embodiment shown in FIG.
2A is a plan view, FIG. 2B is a cross-sectional view of the XX ′ portion of FIG. 2A, and FIG. 2C is a circuit diagram.
【００１７】尚、図２において図１と同じ機能もしくは
類似の機能の箇所は同一の符号で示してある。In FIG. 2, parts having the same or similar functions to those in FIG. 1 are designated by the same reference numerals.
【００１８】第１のリードフレーム１のチップ搭載部１
１に第１の半導体チップ２として第１のＮＰＮ型バイポ
ーラトランジスタＴｒ1 が搭載され、Ｔｒ1 のエミッタ
およびベースはそれぞれ内部リード（インナーリード）
１２にボンディング細線３により接続されてその外部リ
ード（アウターリード）１３がそれぞれエミッタ端子Ｅ
1 およびベース端子Ｂ1 として、またＴｒ1 チップの裏
面がコレクタとなりそのままチップ搭載部１１に接続さ
れそれに繋がる外部リード１３がコレクタ端子Ｃ1 とし
てそれぞれモールド樹脂７の側面（図で左側の側面）か
ら導出されている。Chip mounting portion 1 of the first lead frame 1
1 to the first first NPN-type bipolar transistor Tr 1 as the semiconductor chip 2 is mounted, the emitter of the Tr 1 and the base are respectively internal leads (inner leads)
The external leads (outer leads) 13 connected to the thin wire 12 by the bonding thin wire 3 are respectively the emitter terminals E.
1 and the base terminal B 1 , and the back surface of the Tr 1 chip serves as a collector and is directly connected to the chip mounting portion 11 and the external lead 13 connected thereto is used as the collector terminal C 1 from the side surface (the side surface on the left side in the figure) of the molding resin 7. It has been derived.
【００１９】同様に第１のリードフレーム１とそのチッ
プ搭載部の裏面どうしが積層接着される第２のリードフ
レーム１’のチップ搭載部１１’に第２の半導体チップ
２’として第２のＮＰＮ型バイポーラトランジスタＴｒ
2 が搭載され、Ｔｒ2 のエミッタおよびベースはそれぞ
れ内部リード１２’にボンディング細線３’により接続
されてその外部リード１３がそれぞれエミッタ端子Ｅ2
およびベース端子Ｂ2として、またＴｒ2 チップの裏面
がコレクタとなりそのままチップ搭載部１１’に接続さ
れそれに繋がる外部リード１３’がコレクタ端子Ｃ2 と
してそれぞれモールド樹脂７の側面（図で右側の側面）
から導出されている。Similarly, the second lead frame 1 and the chip mounting portion 11 ′ of the second lead frame 1 ′ where the rear surfaces of the chip mounting portion are laminated and adhered to each other are used as the second NPN as the second semiconductor chip 2 ′. Type bipolar transistor Tr
2 is mounted, and the emitter and base of Tr 2 are respectively connected to the internal lead 12 ′ by a thin bonding wire 3 ′, and the external lead 13 is connected to the emitter terminal E 2 respectively.
Also, as the base terminal B 2 , and the back surface of the Tr 2 chip serves as a collector, the external lead 13 ′ connected to the chip mounting portion 11 ′ as it is and connected to it as the collector terminal C 2 is the side surface of the molding resin 7 (the side surface on the right side in the figure).
Is derived from.
【００２０】Ｔｒ1 のコレクタとＴｒ2 のコレクタとは
リードフレームのチップ搭載部の裏面どうしの積層接着
により共通接続され、図２（Ｃ）に示すように、Ｔｒ1
のエミッタ端子Ｅ1 とＴｒ2 のベース端子Ｂ2 とをパッ
ケージの外部で接続（点線で示す）することによりコレ
クタコモンのダーリントン接続素子を構成した半導体装
置となる。[0020] The collectors of the Tr 2 of Tr 1 are connected in common by the lamination adhesive on the back surface each other of the chip mounting portion of the lead frame, as shown in FIG. 2 (C), Tr 1
By connecting the emitter terminal E 1 of the above and the base terminal B 2 of the Tr 2 outside the package (shown by the dotted line), a semiconductor device having a collector common Darlington connection element is formed.
【００２１】尚、第１および第２の半導体チップとして
それぞれＰＮＰ型のバイポーラトランジスタを用いて、
コレクタコモンのダーリントン接続素子を構成した半導
体装置とすることもできる。In addition, PNP type bipolar transistors are used as the first and second semiconductor chips, respectively,
It is also possible to use a semiconductor device having a Darlington connection element of collector common.
【００２２】この図２のダーリントン接続のバイポーラ
トランジスタを単一パッケージに形成した高い実装密度
の半導体装置は、図１で説明したように、製造を容易に
して得ることができる。The Darlington-connected bipolar transistor of FIG. 2 formed in a single package can be easily manufactured as described with reference to FIG.
【００２３】図３は図１の一実施例の製造方法により得
られたＣＭＯＳ構造の自立タイプの半導体装置を示し、
図３（Ａ）は正面図、図３（Ｂ）は図３（Ａ）のＹ−
Ｙ’部の断面図、図３（Ｃ）は図３（Ａ）の底面図、図
３（Ｄ）は回路図である。尚、図３において図１と同じ
機能もしくは類似の機能の箇所は同一の符号で示してあ
る。FIG. 3 shows a freestanding type semiconductor device having a CMOS structure obtained by the manufacturing method of the embodiment of FIG.
3A is a front view, and FIG. 3B is Y- in FIG.
3'is a sectional view, FIG. 3 (C) is a bottom view of FIG. 3 (A), and FIG. 3 (D) is a circuit diagram. In FIG. 3, parts having the same or similar functions to those in FIG. 1 are designated by the same reference numerals.
【００２４】第１のリードフレーム１のチップ搭載部１
１に第１の半導体チップ２としてＰチャネル型ＭＯＳＦ
ＥＴが搭載され、このＭＯＳＦＥＴ２のソースおよびゲ
ートはそれぞれ内部リード（インナーリード）１２にボ
ンディング細線３により接続されてその外部リード（ア
ウターリード）１３がそれぞれＰチャネルＭＯＳＦＥＴ
のソース端子Ｓ1 およびゲート端子Ｇ1 として、またチ
ップの裏面がドレインとなりそのままチップ搭載部１１
に接続されそれに繋がる外部リード１３がドレイン端子
Ｄ1 としてそれぞれモールド樹脂７の側面（図で下側の
側面）から導出されている。Chip mounting portion 1 of the first lead frame 1
1 is a P-channel MOSF as the first semiconductor chip 2.
The ET is mounted, and the source and gate of the MOSFET 2 are connected to an internal lead (inner lead) 12 by a bonding thin wire 3, and the external lead (outer lead) 13 is a P-channel MOSFET.
As the source terminal S 1 and the gate terminal G 1 of the chip, and the back surface of the chip serves as the drain as it is.
The external leads 13 connected to and connected to the respective terminals are led out from the side surface (lower side surface in the figure) of the molding resin 7 as the drain terminal D 1 .
【００２５】同様に第１のリードフレーム１とそのチッ
プ搭載部の裏面どうしが積層接着される第２のリードフ
レーム１’のチップ搭載部１１’に第２の半導体チップ
２’としてＮチャネルＭＯＳＦＥＴが搭載され、このＭ
ＯＳＦＥＴ２’のソースおよびゲートはそれぞれ内部リ
ード１２’にボンディング細線３’により接続されてそ
の外部リード１３’がそれぞれＮチャネルＭＯＳＦＥＴ
のソース端子Ｓ2 およびゲート端子Ｇ2 として、またチ
ップの裏面がドレインとなりそのままチップ搭載部１
１’に接続されそれに繋がる外部リード１３’がドレイ
ン端子Ｄ2 としてそれぞれモールド樹脂７の側面（図で
下側の側面）から導出されている。Similarly, an N-channel MOSFET is formed as a second semiconductor chip 2'on the chip mounting portion 11 'of the second lead frame 1'where the back surfaces of the first lead frame 1 and its chip mounting portion are laminated and bonded. Mounted, this M
The source and gate of the OSFET 2'are connected to the internal lead 12 'by a bonding thin wire 3', and the external lead 13 'thereof is an N-channel MOSFET.
As the source terminal S 2 and the gate terminal G 2 of the chip, and the back surface of the chip serves as the drain as it is.
Are led from the respective side surface of the mold resin 7 (lower side surface in FIG.) 1 'is connected to an external lead 13 connected thereto' as a drain terminal D 2.
【００２６】Ｐチャネル型ＭＯＳＦＥＴ２のドレインと
Ｎチャネル型ＭＯＳＦＥＴ２’のドレインとはチップ搭
載部の裏面どうしの積層接着により共通接続され、図３
（Ｄ）の回路図に示すように、ＣＭＯＳの出力端ＶOUT
となる。また、Ｐチャネル型ＭＯＳＦＥＴ２のソース端
子Ｓ1 は正電源ラインＶCCに接続され、Ｎチャネル型Ｍ
ＯＳＦＥＴ２’のソース端子Ｓ2 は負電源ラインＶEEに
接続され、両ＭＯＳＦＥＴのゲート端子Ｇ1 ，Ｇ2 はパ
ッケージの外部で共通接続されてこのＣＭＯＳの入力端
ＶINとなる。The drain of the P-channel type MOSFET 2 and the drain of the N-channel type MOSFET 2'are commonly connected by laminating and adhering the back surfaces of the chip mounting portion to each other.
As shown in the circuit diagram of (D), the output terminal V OUT of the CMOS
Becomes Further, the source terminal S1 of the P-channel type MOSFET 2 is connected to the positive power supply line V CC , and the N-channel type M
The source terminal S2 of the OSFET 2'is connected to the negative power supply line V EE, and the gate terminals G 1 and G 2 of both MOSFETs are commonly connected outside the package to be the input terminal V IN of this CMOS.
【００２７】図３のコンプリメンタリー接続のＭＯＳト
ランジスタを単一パッケージに形成した高い実装密度の
半導体装置は、図１で説明したように、製造を容易にし
て得ることができる。The semiconductor device having a high packaging density in which the complementary-connected MOS transistors shown in FIG. 3 are formed in a single package can be easily manufactured as described with reference to FIG.
【００２８】[0028]
【発明の効果】以上説明したように、ワイヤーボンディ
ング済みの２枚のリードフレームを封止前又は封止工程
で、チップ実装面が反対向きとなるように面接触させた
貼合せ積層し、単一パッケージ内にモールド封止するこ
とで、特殊な製法や特殊な設備を用いることなく、モー
ルド内の一枚のリードフレームの片面のみに半導体チッ
プを搭載する従来の半導体装置の製造技術をそのまま用
いて、高い実装密度を可能とする半導体装置を得ること
ができる。As described above, the two wire-bonded lead frames are laminated before being sealed or in the sealing step so that the chip mounting surfaces are in face-to-face contact so as to face in opposite directions. By encapsulating in one package with a mold, without using a special manufacturing method or special equipment, the conventional semiconductor device manufacturing technology in which a semiconductor chip is mounted on only one surface of one lead frame in the mold is used as it is. As a result, it is possible to obtain a semiconductor device that enables high packaging density.
【図１】本発明の実施例の製造方法を示す図であり、
（Ａ）は工程のフローチャート、（Ｂ）は各工程におけ
る断面図である。FIG. 1 is a diagram showing a manufacturing method according to an embodiment of the present invention,
(A) is a process flow chart, and (B) is a sectional view in each process.
【図２】図１の製造方法で得られた一実施例の半導体装
置を示す図であり、（Ａ）は平面図、（Ｂ）は（Ａ）の
Ｘ−Ｘ’部の断面図、（Ｃ）は回路図である。2A and 2B are diagrams showing a semiconductor device of one embodiment obtained by the manufacturing method of FIG. 1, in which FIG. 2A is a plan view, FIG. 2B is a cross-sectional view taken along line XX ′ in FIG. C) is a circuit diagram.
【図３】図１の製造方法で得られた他の実施例の半導体
装置を示す図であり、（Ａ）は正面図、（Ｂ）は（Ａ）
のＹ−Ｙ’部の断面図、（Ｃ）は底面図、（Ｄ）は回路
図である。3A and 3B are diagrams showing a semiconductor device of another embodiment obtained by the manufacturing method of FIG. 1, in which FIG. 3A is a front view and FIG.
Is a cross-sectional view of the section YY ', (C) is a bottom view, and (D) is a circuit diagram.
【図４】従来技術の半導体装置を示す断面図である。FIG. 4 is a cross-sectional view showing a conventional semiconductor device.
１，１’ リードフレーム ２，２’ 半導体チップ ３，３’ ボンディングワイヤー ４ 接着材 ５ 封止金型キャビティ ６，６’ 封止金型ゲート ７ 封止樹脂 １１，１１’ リードフレームのチップ搭載部（アイ
ラド部） １２，１２’ リードフレームの内部リード端子（イ
ンナーリード） １３，１３’ リードフレームの外部リード端子（ア
ウターリード）1,1 'Lead frame 2,2' Semiconductor chip 3,3 'Bonding wire 4 Adhesive 5 Sealing mold cavity 6,6' Sealing mold gate 7 Sealing resin 11,11 'Lead frame chip mounting part (Irad part) 12,12 'Internal lead terminal of lead frame (inner lead) 13,13' External lead terminal of lead frame (outer lead)
Claims (7)
一主表面上に第１の半導体チップを固着し、前記第１の
半導体チップと前記第１のリードフレームの内部リード
間をボンディング細線で接続し、第２のリードフレーム
のチップ搭載部の一主表面上に第２の半導体チップを固
着し、前記第２の半導体チップと前記第２のリードフレ
ームの内部リード間をボンディング細線で接続し、前記
第１および第２のリードフレームのチップ搭載部の他主
表面どうしを面接触させ、前記第１および第２の半導体
チップを一体的に樹脂によりモールド封止したことを特
徴とする半導体装置。1. A first semiconductor chip is fixed on one main surface of a chip mounting portion of a first lead frame, and a thin bonding wire is provided between the first semiconductor chip and an internal lead of the first lead frame. Then, the second semiconductor chip is fixed on one main surface of the chip mounting portion of the second lead frame, and the second semiconductor chip and the internal lead of the second lead frame are connected by a bonding thin wire. A semiconductor device in which the other main surfaces of the chip mounting portions of the first and second lead frames are brought into surface contact with each other, and the first and second semiconductor chips are integrally molded and sealed with a resin. .
触しこれにより両者は固着されていることを特徴とする
請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the other main surfaces are in surface contact with each other via an adhesive, and thereby the two are fixed to each other.
れぞれバイポーラトランジスタであり、それらのコレク
タが共通接続されてコレクタコモンダーリントン接続回
路を構成することを可能とする請求項１に記載の半導体
装置。3. The semiconductor device according to claim 1, wherein each of the first and second semiconductor chips is a bipolar transistor, and collectors thereof are commonly connected to form a collector common Darlington connection circuit. .
れぞれＮチャネルおよびＰチャネル型ＦＥＴであり、両
者がコンプリーメンタリー接続されていることを特徴と
する請求項１に記載の半導体装置。4. The semiconductor device according to claim 1, wherein the first and second semiconductor chips are N-channel and P-channel FETs, respectively, and both of which are complementarily connected.
一方の面にそれぞれ半導体チップをマウントし、このマ
ウントされた半導体チップとそれぞれのリードフレーム
の内部リード間をボンディング細線で接続し、しかる
後、前記半導体チップがたがいに反対向きとなるように
前記２枚のリードフレームのチップ搭載部の他方の面ど
うしを面接触させ、この状態でこれらの半導体チップを
単一パッケージ内にモールドすることを特徴とする半導
体装置の製造方法。5. A semiconductor chip is mounted on one surface of the chip mounting portion of each of the two lead frames, and the mounted semiconductor chips and the internal leads of each lead frame are connected by a bonding thin wire, and thereafter, , The other surfaces of the chip mounting portions of the two lead frames are brought into surface contact so that the semiconductor chips are opposite to each other, and in this state, these semiconductor chips are molded into a single package. A method for manufacturing a characteristic semiconductor device.
ド工程の前に接着材を介して両者を固着して行うことを
特徴とする請求項５に記載の半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein the surface contact between the other surfaces is performed by fixing the two surfaces via an adhesive before the molding step.
ド工程の金型へのセットにおいて行うことを特徴とする
請求項５に記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 5, wherein the surface contact between the other surfaces is performed in a mold set in a molding step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5224317A JPH0778937A (en) | 1993-09-09 | 1993-09-09 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5224317A JPH0778937A (en) | 1993-09-09 | 1993-09-09 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0778937A true JPH0778937A (en) | 1995-03-20 |
Family
ID=16811859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5224317A Pending JPH0778937A (en) | 1993-09-09 | 1993-09-09 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0778937A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536893A (en) * | 1991-08-02 | 1993-02-12 | Nec Corp | Hybrid integrated circuit |
| JP4120247B2 (en) * | 2002-03-26 | 2008-07-16 | 松下電工株式会社 | Beauty equipment |
-
1993
- 1993-09-09 JP JP5224317A patent/JPH0778937A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0536893A (en) * | 1991-08-02 | 1993-02-12 | Nec Corp | Hybrid integrated circuit |
| JP4120247B2 (en) * | 2002-03-26 | 2008-07-16 | 松下電工株式会社 | Beauty equipment |
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