JPH0778846A - Tape carrier package - Google Patents
Tape carrier packageInfo
- Publication number
- JPH0778846A JPH0778846A JP5221514A JP22151493A JPH0778846A JP H0778846 A JPH0778846 A JP H0778846A JP 5221514 A JP5221514 A JP 5221514A JP 22151493 A JP22151493 A JP 22151493A JP H0778846 A JPH0778846 A JP H0778846A
- Authority
- JP
- Japan
- Prior art keywords
- tape carrier
- outer lead
- carrier package
- semiconductor element
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はテ−プキャリアパッケ−
ジの改良に係わる。BACKGROUND OF THE INVENTION The present invention relates to a tape carrier package.
Involved in the improvement of Ji.
【0002】[0002]
【従来の技術】半導体素子の集積度の増大により、ピン
数も増えており、これを組立てる外囲器のピン数も当然
増えている。このようなピン数の増大により半導体素子
の組立方式は従来からのリ−ドフレ−ム方式と共にいわ
ゆるテ−プキャリア方式も多品種にわたって採用されて
いる。2. Description of the Related Art As the degree of integration of semiconductor devices has increased, the number of pins has increased, and the number of pins of an envelope for assembling the same has naturally increased. Due to such an increase in the number of pins, the so-called tape carrier method has been adopted in many kinds of semiconductor element assembling methods in addition to the conventional lead frame method.
【0003】テ−プキャリア方式により板状の半導体素
子を組立てる方法を図1乃至図4により説明するが、図
1にテ−プキャリア方式により組立てた半導体素子の断
面図、この半導体素子を所定の基板に実装する工程を図
2の断面図により示し、図3は図2の要部を拡大した
図、図4は図1の断面図に対応する上面図である。図1
の断面図ならびに図4の上面図に明らかなように板状の
半導体素子1の周辺には例えばポリイミド樹脂から成る
タブ2を取付け、これに設ける導電性パタ−ン3(図2
参照)には直線状に延長するアウタ−リ−ド4を形成す
る。この導電性パタ−ン3と半導体素子1は直線状のリ
−ド5を介して電気的に接続し更に半導体素子1の周囲
とその一面を封止樹脂層6により覆ってタブ2を一体に
形成する構造が一般的である。A method of assembling a plate-shaped semiconductor element by the tape carrier method will be described with reference to FIGS. 1 to 4. FIG. 1 is a sectional view of the semiconductor element assembled by the tape carrier method, and this semiconductor element is predetermined. 2 is a sectional view showing the step of mounting on the substrate of FIG. 2, FIG. 3 is an enlarged view of a main part of FIG. 2, and FIG. 4 is a top view corresponding to the sectional view of FIG. Figure 1
As is clear from the sectional view of FIG. 4 and the top view of FIG. 4, a tab 2 made of, for example, a polyimide resin is attached to the periphery of the plate-shaped semiconductor element 1, and a conductive pattern 3 (FIG.
The outer lead 4 which extends linearly is formed in (see). The conductive pattern 3 and the semiconductor element 1 are electrically connected via a linear lead 5, and the periphery of the semiconductor element 1 and one surface thereof are covered with a sealing resin layer 6 to integrally form the tab 2. The structure to be formed is general.
【0004】この結果図4に明らかなように封止樹脂層
6の外側にポリイミド樹脂から成るタブ2が配置され、
板状の半導体素子1内に形成する能動素子または受動素
子は金属細線5または直線状のリ−ド5、タブ2に設置
する導電性パタ−ン3ならびにアウタ−リ−ド4を介し
て電子機器に電気的に接続して所定の電子回路を構成す
る。As a result, as is apparent from FIG. 4, the tab 2 made of polyimide resin is arranged outside the sealing resin layer 6,
An active element or a passive element formed in the plate-shaped semiconductor element 1 is an electronic element via a thin metal wire 5 or a linear lead 5, a conductive pattern 3 installed on the tab 2 and an outer lead 4. A predetermined electronic circuit is configured by being electrically connected to the device.
【0005】このようなテ−プキャリアパッケ−ジ8に
設置するアウタ−リ−ド4と電子機器用基板7との電気
的な接続は図2及び図3により説明する。前記のように
ポリイミド樹脂などから成るタブ2の表面部分には例え
ばエッチング法などにより銅箔などから成る導電性パタ
−ン3を設けて利用する。半導体基板と導電性パタ−ン
3の電気的な接続に利用するリ−ド5の形成に際して
は、板状の半導体素子に形成するいわゆるバンプ電極7
を利用する。The electrical connection between the outer lead 4 installed on the tape carrier package 8 and the electronic equipment substrate 7 will be described with reference to FIGS. 2 and 3. As described above, the conductive pattern 3 made of copper foil or the like is provided on the surface portion of the tab 2 made of polyimide resin or the like, for example, by an etching method or the like. When forming the lead 5 used for electrical connection between the semiconductor substrate and the conductive pattern 3, the so-called bump electrode 7 formed on the plate-shaped semiconductor element is used.
To use.
【0006】導電性パタ−ン3にはアウタ−リ−ド4を
直線状に取付け、その先端を電子機器用基板7に半田な
どにより固定して電気的に接続するが、先端を図2に示
すように同一方向に折曲げて曲線部8を形成する。The outer lead 4 is linearly attached to the conductive pattern 3, and its tip is fixed to the electronic device substrate 7 by soldering or the like to be electrically connected. As shown, the curved portion 8 is formed by bending in the same direction.
【0007】一方封止樹脂層6などにより組立てられた
複数の半導体素子1を電子機器用基板7に取付けるには
図2に明らかなように上に重ねた状態とする方法が採ら
れている。On the other hand, in order to attach the plurality of semiconductor elements 1 assembled by the sealing resin layer 6 and the like to the electronic device substrate 7, a method of putting them on top of each other as apparent from FIG. 2 is adopted.
【0008】[0008]
【発明が解決しようとする課題】前記のようにテ−プキ
ャリアパッケ−ジ8に組立てられた複数の半導体素子1
を電子機器用基板7に取付けるには図3に明らかにする
ようにオフセット量a、bの相違による難点が生ずる。
即ち夫々の相違に対応して多段数に応じたアウタ−リ−
ド曲げ金型が必要になる。A plurality of semiconductor elements 1 assembled in the tape carrier package 8 as described above.
3 is attached to the electronic device substrate 7, there is a problem due to the difference in the offset amounts a and b, as is apparent from FIG.
That is, the outer reel corresponding to the number of stages corresponding to each difference
A bending mold is required.
【0009】本発明はこのような事情により成されたも
ので、特に金型数を抑制可能な新規なテ−プキャリアパ
ッケ−ジを提供する。The present invention has been made in view of the above circumstances, and particularly provides a novel tape carrier package capable of suppressing the number of molds.
【0010】[0010]
【課題を解決するための手段】板状の半導体素子の外側
に配置するタブと,前記タブに形成し前記半導体素子に
電気的に接続する複数の直線状のアウタ−リ−ドと,前
記アウタ−リ−ドを実装する基板と,前記基板に対して
垂直方向に配置する前記アウタ−リ−ド端部と,互いに
隣接する前記アウタ−リ−ド端部に連続しかつ互いに逆
方向に折曲げた曲線部とに本発明に係わるテ−プキャリ
アパッケ−ジの特徴がある。A tab disposed outside a plate-shaped semiconductor element, a plurality of linear outer leads formed on the tab and electrically connected to the semiconductor element, and the outer A board on which the leads are mounted, the outer lead ends arranged in a direction perpendicular to the board, and the outer lead ends that are adjacent to each other, are continuous with each other and fold in opposite directions. The bent curved portion is characteristic of the tape carrier package according to the present invention.
【0011】更に前記曲線部を固着する基板に対して直
立状態とする板状の半導体素子とにも特徴がある。Another feature is a plate-shaped semiconductor element that is in an upright state with respect to the substrate to which the curved portion is fixed.
【0012】[0012]
【作用】以上のように本発明に係わるテ−プキャリアパ
ッケ−ジは、基板に対して垂直方向にアウタ−リ−ドを
配置すると共に、互いに隣接する曲線部の曲げ方向を逆
に形成することにより多数の半導体素子が実装できる。As described above, in the tape carrier package according to the present invention, the outer leads are arranged in the direction perpendicular to the substrate, and the curved portions adjacent to each other are formed in the opposite bending directions. As a result, many semiconductor elements can be mounted.
【0013】[0013]
【実施例】本発明に係わる実施例を図5乃至図9を参照
して詳細に説明する。図5には電子機器用基板表面に対
して垂直方向に実装可能なテ−プキャリアパッケ−ジの
断面図を示し、図6はその要部の拡大図、図7はテ−プ
キャリアパッケ−ジをモジュ−ル(Module)化し
た例であり、図8は高密度実装する基板に形成するフッ
トプリントの配置を明らかにする図であり、図9は他の
テ−プキャリアパッケイジ例を明らかにした。Embodiments of the present invention will be described in detail with reference to FIGS. FIG. 5 shows a sectional view of a tape carrier package which can be mounted in a direction perpendicular to the surface of the electronic device substrate, FIG. 6 is an enlarged view of the main part thereof, and FIG. 7 is a tape carrier package. FIG. 8 is an example in which the module is modularized, FIG. 8 is a diagram for demonstrating the layout of footprints formed on a substrate for high-density mounting, and FIG. 9 is another example of a tape carrier package. I chose
【0014】本発明に係わるテ−プキャリアパッケ−ジ
においてはアウタ−リ−ド以外が従来の構造と同じだが
簡単に説明する。The tape carrier package according to the present invention has the same structure as the conventional one except for the outer lead, but will be briefly described.
【0015】能動素子または受動素子の外に電極、配線
層、絶縁物層らびにパッシベイション層などを造り込ん
だ板状の半導体素子10の周辺には例えばポリイミド樹
脂から成るタブ11を取付ける。タブ11には例えばス
クリ−ン印刷法により銅などから成る導電性パタ−ン1
2を設け、これに電気的に接続するアウタ−リ−ド13
を設置する。導電性パタ−ン12と板状の半導体素子1
0の接続には、板状の半導体素子10に設置するバンプ
電極14と導電性パタ−ン12間にリ−ド15を固着す
ることにより電気的な接続を図る。A tab 11 made of, for example, a polyimide resin is attached to the periphery of a plate-shaped semiconductor element 10 in which an electrode, a wiring layer, an insulating layer and a passivation layer are formed outside the active element or the passive element. The tab 11 has a conductive pattern 1 made of copper or the like, for example, by a screen printing method.
2 is provided and is electrically connected to the outer lead 13
Set up. Conductive pattern 12 and plate-shaped semiconductor element 1
For the connection of 0, a lead 15 is fixed between the bump electrode 14 and the conductive pattern 12 provided on the plate-shaped semiconductor element 10 to achieve electrical connection.
【0016】このように電気的に接続したタブ11と板
状の半導体素子10の表面部分には封止樹脂層16によ
り覆われると共に両者が一体となり、封止樹脂層16の
外側にポリイミド樹脂から成るタブ11が配置され、導
電性パタ−ン12に電気的に接続するアウタ−リ−ド1
3が直線状に配置される。The tab 11 electrically connected in this way and the surface of the plate-shaped semiconductor element 10 are covered with a sealing resin layer 16 and are integrated with each other. The outer lead 1 is provided with a tab 11 and is electrically connected to the conductive pattern 12.
3 are arranged linearly.
【0017】アウタ−リ−ド13は例えば銅などの金属
製の箔から成りその末端に曲線部17を形成して電子機
器用基板18への表面実装に備える。図5で点線で囲ん
だ部分Aの拡大図が図6である。The outer lead 13 is made of, for example, a metal foil such as copper, and a curved portion 17 is formed at the end thereof to prepare for surface mounting on a substrate 18 for electronic equipment. FIG. 6 is an enlarged view of a portion A surrounded by a dotted line in FIG.
【0018】この図に明らかなように隣り合うアウタ−
リ−ド13に設置した曲線部17の曲げる方向は互いに
逆方向であり更に電子機器用基板18表面に対してアウ
タ−リ−ド13の軸方向が垂直になる。なお図7に示す
ように曲線部17は例えば接着剤19により固着し、機
械的強度を補うべく壁20を電子機器用基板18に設置
することも可能である。As is apparent from this figure, the outer casings adjacent to each other
The curved portions 17 installed on the lead 13 are bent in opposite directions, and the axial direction of the outer lead 13 is perpendicular to the surface of the electronic device substrate 18. Note that, as shown in FIG. 7, the curved portion 17 may be fixed by an adhesive 19, for example, and the wall 20 may be installed on the electronic device substrate 18 in order to supplement the mechanical strength.
【0019】図8は高密度実装する基板に形成するフッ
トプリントの配置を示しており、電子機器用基板18左
端にテ−プキャリアパッケ−ジを実装するフットプリン
トであり21aならびに左端から2番目に設置するフッ
トプリント21bを記載した。FIG. 8 shows an arrangement of footprints formed on a board for high-density mounting, which is a footprint for mounting a tape carrier package on the left end of the electronic device board 18 and is the second from the left end 21a. The footprint 21b to be installed in is described.
【0020】更に垂直に立てるばかりでなく、図9の方
式も可能である。即ち複数の板状の半導体素子10を電
子機器用基板18に取付けるに当っては、前記のように
接着剤19を利用し、これに重ねる他の半導体素子10
も同様に例えば接着剤19により両者を固着する。そし
て前記のように隣り合うアウタ−リ−ド13に形成する
曲線部17の曲げる方向を逆に形成する。ただし例えば
銅箔などから成るアウタ−リ−ド13は、末端に形成す
る曲線部17の前に一旦90°に折曲げることにより電
子機器用基板18表面に接触可能となる。In addition to standing vertically, the method of FIG. 9 is also possible. That is, when the plurality of plate-shaped semiconductor elements 10 are attached to the electronic device substrate 18, the adhesive 19 is used as described above, and another semiconductor element 10 to be stacked thereon is used.
Similarly, the both are fixed by the adhesive 19, for example. Then, as described above, the curved portions 17 formed on the outer leads 13 adjacent to each other are formed so that the bending direction is reversed. However, the outer lead 13 made of, for example, copper foil or the like can be brought into contact with the surface of the electronic device substrate 18 by bending it once at 90 ° before the curved portion 17 formed at the end.
【0021】この場合は電子機器用基板18表面と接着
剤19により板状の半導体素子10が固着しているので
曲線部17の機械的強度は前記の例より大きい。In this case, since the plate-shaped semiconductor element 10 is fixed to the surface of the electronic device substrate 18 by the adhesive 19, the mechanical strength of the curved portion 17 is larger than that in the above example.
【0022】[0022]
【発明の効果】本発明に係わるテ−プキャリアパッケ−
ジにあっては複数の半導体素子を基板に取付けるのにア
ウタ−リ−ドを折曲げる金型を最低2個用意すれば良い
のでコストダウンができる上に、複数個の半導体素子を
高密度に実装可能になる。The tape carrier package according to the present invention.
In order to attach a plurality of semiconductor elements to the substrate, it is sufficient to prepare at least two molds for bending the outer lead, so that the cost can be reduced and the plurality of semiconductor elements can be densely arranged. Can be implemented.
【図1】従来のテ−プキャリアパッケ−ジの断面を示す
図である。FIG. 1 is a view showing a cross section of a conventional tape carrier package.
【図2】複数のテ−プキャリアパッケ−ジを配置する状
況を明らかにする断面である。FIG. 2 is a cross-sectional view showing a situation in which a plurality of tape carrier packages are arranged.
【図3】図3は図2の要部を拡大した図である。FIG. 3 is an enlarged view of a main part of FIG.
【図4】図1に示すテ−プキャリアパッケ−ジの上面図
である。FIG. 4 is a top view of the tape carrier package shown in FIG.
【図5】本発明に係わるテ−プキャリアパッケ−ジの断
面図である。FIG. 5 is a cross-sectional view of a tape carrier package according to the present invention.
【図6】その一部を拡大する断面図である。FIG. 6 is an enlarged cross-sectional view of a part thereof.
【図7】本発明に係わるテ−プキャリアパッケ−ジをモ
ジュ−ル化した状態を示す図である。FIG. 7 is a view showing a state in which the tape carrier package according to the present invention is modularized.
【図8】高密度実装する基板に形成するフットプリント
の配置を明らかにする図である。FIG. 8 is a diagram showing the layout of footprints formed on a substrate for high-density mounting.
【図9】図7の変形としてテープキャリアパッケージを
モジュール化した他の状態を示す図である。9 is a diagram showing another state in which the tape carrier package is modularized as a modification of FIG. 7. FIG.
1、10:半導体素子、 2、11:タブ、 3、12:導電性パタ−ン、 4、13:アウタ−リ−ド、 5、15:リ−ド、 14:バンプ電極、 6、16:封止樹脂層、 7、18:電子機器用基板、 8、17:曲線部、 19:接着剤、 20:壁、 21a、b:フットプリント。 1, 10: Semiconductor element, 2, 11: Tab, 3, 12: Conductive pattern, 4, 13: Outer lead, 5, 15: Lead, 14: Bump electrode, 6, 16: Sealing resin layer, 7, 18: Substrate for electronic device, 8, 17: Curved portion, 19: Adhesive, 20: Wall, 21a, b: Footprint.
Claims (2)
と,前記タブに形成し前記半導体素子に電気的に接続す
る複数の直線状のアウタ−リ−ドと,前記アウタ−リ−
ドを実装する基板と,前記基板に対して垂直方向に配置
する前記アウタ−リ−ド端部と,互いに隣接する前記ア
ウタ−リ−ド端部に連続しかつ互いに逆方向に折曲げた
曲線部とを具備することを特徴とするテープキャリアパ
ッケージ。1. A tab arranged outside a plate-shaped semiconductor element, a plurality of linear outer leads formed on the tab and electrically connected to the semiconductor element, and the outer lead.
A board on which a board is mounted, the outer lead end arranged in a direction perpendicular to the board, and a curve continuous with the outer lead ends adjacent to each other and bent in opposite directions. And a tape carrier package.
状態とする板状の半導体素子を具備することを特徴とす
る請求項1記載のテープキャリアパッケージ。2. The tape carrier package according to claim 1, further comprising a plate-shaped semiconductor element that is in an upright state with respect to a substrate to which the curved portion is fixed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5221514A JPH0778846A (en) | 1993-09-07 | 1993-09-07 | Tape carrier package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5221514A JPH0778846A (en) | 1993-09-07 | 1993-09-07 | Tape carrier package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0778846A true JPH0778846A (en) | 1995-03-20 |
Family
ID=16767910
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5221514A Pending JPH0778846A (en) | 1993-09-07 | 1993-09-07 | Tape carrier package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0778846A (en) |
-
1993
- 1993-09-07 JP JP5221514A patent/JPH0778846A/en active Pending
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20011023 |