JPH0775405B2 - Driving method for solid-state imaging device - Google Patents

Driving method for solid-state imaging device

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Publication number
JPH0775405B2
JPH0775405B2 JP1096713A JP9671389A JPH0775405B2 JP H0775405 B2 JPH0775405 B2 JP H0775405B2 JP 1096713 A JP1096713 A JP 1096713A JP 9671389 A JP9671389 A JP 9671389A JP H0775405 B2 JPH0775405 B2 JP H0775405B2
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JP
Japan
Prior art keywords
semiconductor substrate
potential
solid
region
period
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP1096713A
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Japanese (ja)
Other versions
JPH02274184A (en
Inventor
満 沖川
一弘 数井
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP1096713A priority Critical patent/JPH0775405B2/en
Publication of JPH02274184A publication Critical patent/JPH02274184A/en
Publication of JPH0775405B2 publication Critical patent/JPH0775405B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は縦型オーバーフロードレイン方式のCCD固体撮
像素子の駆動方法に関する。
The present invention relates to a method for driving a vertical overflow drain type CCD solid-state image sensor.

(ロ) 従来の技術 従来、CCD固体撮像素子を用いた撮像装置に於いては、C
CDの動作原理を活用して電子的に露光制御を行うことが
考えられている。このような露光制御方法に於いては、
電気的に走査される撮像素子の垂直走査期間毎の光電変
換期間の途中でそれまで撮像部に蓄積される光電荷を排
出させ、残余の光電変換期間に得た光電荷を蓄積するよ
うに構成している。ここで、問題となるのは、撮像部の
光電荷を排出する方法であり、撮像素子の出力する映像
信号に影響なく、不要な光電荷を十分に排出させるため
の方法が種々考えられている。
(B) Conventional technology Conventionally, in the image pickup device using the CCD solid-state image pickup device,
It is considered to electronically control exposure by utilizing the operating principle of CD. In such an exposure control method,
In the middle of the photoelectric conversion period of each vertical scanning period of the electrically scanned image pickup device, the photocharges accumulated in the image pickup unit until then are discharged, and the photocharges obtained in the remaining photoelectric conversion period are accumulated. is doing. Here, the problem is the method of discharging the photocharges of the image pickup unit, and various methods have been considered for sufficiently discharging the unnecessary photocharges without affecting the video signal output from the image pickup device. .

例えば、日経マイクロデバイス1987年10月号P60〜P67の
「38万画素に達した固体撮像素子」では、撮像部の光電
荷を基板側に排出させる、所謂縦型オーバーフロードレ
イン方式のCCD固体撮像素子が記載されている。
For example, in the Nikkei Microdevice October 1987 issue P60-P67 "Solid-state image sensor reaching 380,000 pixels", the so-called vertical overflow drain CCD solid-state image sensor that discharges the photocharge of the image pickup section to the substrate side. Is listed.

また、本出願人既提案の特願昭63−95881号では、縦型
オーバーフロードレイン方式のCCDB固体撮像素子に於い
て、転送電極の電位を下げることで転送電極の下のチャ
ネル領域のポテンシャルを浅くして光電荷を基板側に排
出させることが示されている。
Also, in Japanese Patent Application No. 63-95881 proposed by the present applicant, in a vertical overflow drain CCDB solid-state imaging device, the potential of the channel region under the transfer electrode is reduced by lowering the potential of the transfer electrode. Then, the photocharge is discharged to the substrate side.

第4図は、上述の如き縦型オーバーフロードレイン方式
のCCD固体撮像素子の撮像部を示す平面図であり、第5
図はそのX−X′線断面図である。
FIG. 4 is a plan view showing an image pickup section of the vertical overflow drain type CCD solid-state image pickup device as described above.
The figure is a sectional view taken along line XX '.

N型の半導体基板(1)の一方の面には、P−Well領域
(2)が形成され、このP−Well領域(2)内にはP+
のチャネルストップ領域(3)が複数本平行に配列形成
される。各チャネルストップ領域(3)の間にはN型の
拡散領域(4)が形成されて埋込型の蓄積転送チャネル
が構成される。そして、拡散領域(3)上にチャネルス
トップ領域(3)に直交する転送電極(5a)(5b)が絶
縁膜(6)を介して形成される。この転送電極(5a)
(5b)は、2層構造を成し、このうち上層の転送電極
(5b)はチャネルストップ領域(3)上でその幅が細く
なっていると共に、隣り合う下層の転送電極(5a)間に
跨がって設けられる。これら転送電極(5a)(5b)は、
4相の転送クロックφF1〜φF4に依ってパルス駆動され
るものであり、各転送電極(5a)(5b)には4層の転送
クロックφF1〜φF4が順次印加される。
A P-Well region (2) is formed on one surface of the N-type semiconductor substrate (1), and a plurality of P + -type channel stop regions (3) are formed in the P-Well region (2). Arrayed in parallel. An N-type diffusion region (4) is formed between each channel stop region (3) to form a buried storage transfer channel. Then, transfer electrodes (5a) and (5b) orthogonal to the channel stop region (3) are formed on the diffusion region (3) via the insulating film (6). This transfer electrode (5a)
(5b) has a two-layer structure, of which the upper transfer electrode (5b) has a narrower width on the channel stop region (3) and between the adjacent lower transfer electrodes (5a). It is provided across. These transfer electrodes (5a) (5b) are
It is pulse-driven by four-phase transfer clocks φ F1 to φ F4 , and four layers of transfer clocks φ F1 to φ F4 are sequentially applied to each transfer electrode (5a) (5b).

一方、半導体基板(1)は、一定の電位Vsubに固定さ
れ、P−Well領域(2)はチャネルストップ領域(3)
を介し接地電位に固定される。このように、半導体基板
(1)及びP−Well領域(2)に特定の電位を印加した
ときのY−Y′線(第5図中)のポテンシャルの状態を
第6図に示す。このとき、転送電極(5b)は、接地レベ
ルに対して一定の値だけ高いレベルに保持され、P−We
ll領域(2)付近にポテンシャル障壁が形成される。従
って、このポテンシャル障壁と半導体基板(1)表面の
ポテンシャル障壁との間に形成されるポテンシャル井戸
に光電荷eが蓄積されることになる。この光電荷eの転
送は、P−Well領域(2)付近のポテンシャル障壁が十
分な高さを維持できる範囲で各転送電極(5a)(5b)の
電位を変動して行う。
On the other hand, the semiconductor substrate (1) is fixed at a constant potential Vsub, and the P-Well region (2) is a channel stop region (3).
It is fixed to the ground potential via. FIG. 6 shows the potential state of the YY ′ line (in FIG. 5) when a specific potential is applied to the semiconductor substrate (1) and the P-Well region (2). At this time, the transfer electrode (5b) is held at a level higher than the ground level by a constant value, and P-We
A potential barrier is formed near the ll region (2). Therefore, the photocharges e are accumulated in the potential well formed between this potential barrier and the potential barrier on the surface of the semiconductor substrate (1). The transfer of the photocharge e is performed by changing the potentials of the transfer electrodes (5a) and (5b) within a range in which the potential barrier near the P-Well region (2) can maintain a sufficient height.

ここで、転送電極(5a)(5b)の電位を一定レベル以
下、或いは負にすると、第6図に破線で示す如く半導体
基板(1)表面のポテンシャルが浅くなり、これに伴っ
て拡散領域(4)内のポテンシャルが浅くなるためにP
−Well領域(2)付近のポテンシャル障壁が消滅して光
電荷eが全て半導体基板(1)側に流れる。従って、蓄
積転送チャネルに蓄積される光電荷eを排出する場合に
は、転送電極(5a)(5b)の電位を下げることに依って
行うことができる。
Here, when the potentials of the transfer electrodes (5a) and (5b) are set to a certain level or below or negative, the potential on the surface of the semiconductor substrate (1) becomes shallow as shown by the broken line in FIG. 4) Because the potential inside is shallow, P
The potential barrier near the -Well region (2) disappears and all the photocharges e flow to the semiconductor substrate (1) side. Therefore, the discharge of the photocharge e accumulated in the accumulation transfer channel can be performed by lowering the potentials of the transfer electrodes (5a) and (5b).

(ハ) 発明が解決しようとする課題 上述の如き縦型オーバーフロードレイン方式のCCDに於
いては、転送電極(5a)(5b)の電位を下げたときに光
電荷eが半導体基板(1)側に流れるようにP−Well領
域(2)の濃度や各電位を設定する必要がある。即ち、
光電荷eを転送駆動するときの転送電極(5a)(5b)の
電位に対しては、第6図の実線の如くP−Well領域
(2)付近にポテンシャル障壁を形成し、光電荷eを排
出するときの転送電極(5a)(5b)の電位に対しては、
第6図の破線の如く半導体基板(1)の表面から裏面に
かけてポテンシャル障壁を形成しないようにP−Well領
域(2)の濃度及び深さを設定する。そこで、P−Well
領域(2)の不純物濃度を低くするか、或いはP−Well
領域(2)を半導体基板(1)の浅い位置に設けると、
転送電極(5a)(5b)の電位を下げたときに光電荷eが
半導体基板(1)に流れ易くなることから、転送電極
(5a)(5b)の電位変動の幅を小さくできる。ところ
が、P−Well領域(2)の濃度を低くすると、P−Well
領域(2)のポテンシャル障壁が低くなり、光電荷eを
蓄積できる容量が小さくなると共に、P−Well領域
(2)を浅くすると、光電変換に有効な領域が狭くなる
ことから、受光感度が低下する。
(C) Problems to be Solved by the Invention In the vertical overflow drain type CCD as described above, when the potentials of the transfer electrodes (5a) and (5b) are lowered, the photocharge e is on the semiconductor substrate (1) side. It is necessary to set the concentration and each potential of the P-Well region (2) so as to flow in the direction. That is,
With respect to the potentials of the transfer electrodes (5a) and (5b) when transferring and driving the photocharge e, a potential barrier is formed near the P-Well region (2) as shown by the solid line in FIG. For the potential of the transfer electrodes (5a) and (5b) when discharging,
The concentration and depth of the P-Well region (2) are set so that a potential barrier is not formed from the front surface to the back surface of the semiconductor substrate (1) as indicated by the broken line in FIG. So P-Well
Decrease the impurity concentration in region (2), or use P-Well
When the region (2) is provided at a shallow position of the semiconductor substrate (1),
Since the photocharge e easily flows into the semiconductor substrate (1) when the potentials of the transfer electrodes (5a) (5b) are lowered, the range of potential fluctuations of the transfer electrodes (5a) (5b) can be reduced. However, if the concentration of P-Well region (2) is lowered, P-Well
The potential barrier of the region (2) becomes low, the capacity for accumulating the photocharge e becomes small, and when the P-Well region (2) is made shallow, the effective region for photoelectric conversion becomes narrow, and thus the light receiving sensitivity decreases. To do.

逆に、蓄積容量の増大や受光感度の向上を図るためにP
−Well領域(2)の濃度を高くしたり、P−Well領域
(2)を深く形成すると光電荷eが排出され難くなるた
めに転送電極(5a)(5b)の電位の変動の幅を広くする
必要があるのに加え、光電荷eの排出が不完全となる虞
れがある。
On the contrary, in order to increase the storage capacity and the light receiving sensitivity, P
If the concentration of the -Well region (2) is increased or the P-Well region (2) is deeply formed, it becomes difficult for the photocharge e to be discharged. Therefore, the fluctuation range of the potential of the transfer electrodes (5a) (5b) is widened. In addition to this, there is a possibility that the discharge of the photocharge e may be incomplete.

そこで本発明は、縦型オーバーフロードレイン方式のCC
Dに於いて、光電荷の排出動作を損うことなく蓄積容量
の増大や受光感度の向上を図ることを目的とする。
Therefore, the present invention is a vertical overflow drain type CC.
The purpose of D is to increase the storage capacity and the light receiving sensitivity without impairing the operation of discharging the photocharge.

(ニ) 課題を解決するための手段 本発明は上述の課題を解決するためになされたもので、
半導体基板の一主面に設けられた基板とは逆導電型の拡
散領域上に転送電極が形成され、光電変換に依って発生
する光電荷を蓄積するチャネル領域が上記拡散領域内に
形成される縦型オーバーフロードレイン方式のCCD固体
撮像素子の駆動方法に於いて、上記チャネル領域と上記
半導体基板との間に電位障壁を形成しうる上記転送電極
及び上記半導体基板の両電位に対し、上記転送電極を低
電位とすると共に上記半導体基板を高電位とすること
で、上記チャネル領域と上記半導体基板との間の電位障
壁を消滅させ、上記チャネル領域中の不要な光電荷を上
記半導体基板側に排出せしめることを特徴とする。
(D) Means for Solving the Problems The present invention has been made to solve the above problems.
A transfer electrode is formed on a diffusion region of a conductivity type opposite to that of the substrate provided on one main surface of the semiconductor substrate, and a channel region for accumulating photocharges generated by photoelectric conversion is formed in the diffusion region. In a vertical overflow drain type CCD solid-state imaging device driving method, the transfer electrode capable of forming a potential barrier between the channel region and the semiconductor substrate and the transfer electrode with respect to both potentials of the semiconductor substrate. Is set to a low potential and the semiconductor substrate is set to a high potential to eliminate a potential barrier between the channel region and the semiconductor substrate, and unnecessary photocharges in the channel region are discharged to the semiconductor substrate side. It is characterized by being busy.

(ホ) 作用 本発明に依れば、転送電極の電位を下げると共に半導体
基板の電位を上げることで、拡散領域が高濃度に設けら
れる場合や基板に深く設けられる場合でもチャネル領域
の光電荷を確実に半導体基板側に排出させる。逆に、転
送電極の電位を上げると共に半導体基板の電位を下げる
ことで、拡散領域付近に形成されるポテンシャル障壁が
高くなりチャネル領域の蓄積容量を大きくできる。
(E) Action According to the present invention, by lowering the potential of the transfer electrode and raising the potential of the semiconductor substrate, the photocharge in the channel region is prevented even when the diffusion region is provided at a high concentration or deep in the substrate. Be sure to discharge to the semiconductor substrate side. On the contrary, by raising the potential of the transfer electrode and lowering the potential of the semiconductor substrate, the potential barrier formed in the vicinity of the diffusion region is increased and the storage capacitance of the channel region can be increased.

(ヘ) 実施例 本発明の実施例を図面に従って説明する。(F) Example An example of the present invention will be described with reference to the drawings.

第1図は本発明駆動方法に依るCCD固体撮像素子のポテ
ンシャルの状態を示す図である。CCD固体撮像素子自体
は、第4図及び第5図と同一のものであり、ここでは説
明を省略する。
FIG. 1 is a diagram showing a potential state of a CCD solid-state image pickup device according to the driving method of the present invention. The CCD solid-state image pickup device itself is the same as that shown in FIGS. 4 and 5, and a description thereof will be omitted here.

本発明の特徴とするところは、転送電極(5a)(5b)の
電位の変動に合わせて半導体基板(1)の電位を変動す
ることにある。即ち、半導体基板(1)には、第5図に
示す一定電位Vsubに換えて、排出動作時に高レベルとな
る排出制御クロックφsubが印加されることになる。こ
の排出制御クロックφsubは、排出動作の期間中上述の
電位Vsubに保持され、光電荷を蓄積する期間には電位Vs
ubより低電位に保持される。
The feature of the present invention resides in that the potential of the semiconductor substrate (1) is changed according to the change of the potentials of the transfer electrodes (5a) and (5b). That is, instead of the constant potential Vsub shown in FIG. 5, the semiconductor substrate (1) is applied with the discharge control clock φsub which becomes high level during the discharge operation. This discharge control clock φsub is held at the above-mentioned potential Vsub during the discharge operation, and is kept at the potential Vs during the period for accumulating photocharges.
It is kept at a lower potential than ub.

転送電極(5a)(5b)が高電位で且つ半導体基板(1)
が低電位となると、CCD固体撮像素子の深さ方向のポテ
ンシャル(第5図Y−Y′線に対応)は第4図の実線に
示す如くP−Well領域(2)付近にポテンシャル障壁が
形成される。従って、このポテンシャル障壁と半導体基
板(1)表面のポテンシャル障壁との間に光電荷eが蓄
積される。
The transfer electrodes (5a) (5b) have a high potential and the semiconductor substrate (1)
When the potential becomes low, the potential of the CCD solid-state image sensor in the depth direction (corresponding to the line YY 'in FIG. 5) forms a potential barrier near the P-Well region (2) as shown by the solid line in FIG. To be done. Therefore, the photocharge e is accumulated between this potential barrier and the potential barrier on the surface of the semiconductor substrate (1).

逆に転送電極(5a)(5b)が低電位で且つ半導体基板
(1)が高電位(Vsub)となると第1図の破線で示す如
く半導体基板(1)の表面から裏面に向ってポテンシャ
ルの勾配ができ、光電荷eはその勾配に沿って半導体基
板(1)側に流れる。
On the contrary, when the transfer electrodes (5a) and (5b) have a low potential and the semiconductor substrate (1) has a high potential (Vsub), the potential of the semiconductor substrate (1) is changed from the front surface to the back surface as shown by the broken line in FIG. There is a gradient, and the photocharge e flows along the gradient toward the semiconductor substrate (1) side.

ここで、第1図のポテンシャルの状態を第6図の場合と
比較すると、排出動作時のポテンシャルの状態(図中破
線で示す)は同一であるが、光電荷eの蓄積時のポテン
シャルの状態(図中実線で示す)に於いては、電荷の蓄
積容量が大きくなっていることが分かる。
Here, comparing the potential state of FIG. 1 with the case of FIG. 6, the potential state during the discharging operation (shown by the broken line in the figure) is the same, but the potential state during the accumulation of the photocharge e. In (indicated by the solid line in the figure), it can be seen that the charge storage capacity is large.

第2図は本発明駆動方法を採用してCCD固体撮像素子の
露光制御を行う際の構成を示すブロック図である。
FIG. 2 is a block diagram showing a configuration when performing exposure control of a CCD solid-state image pickup device by adopting the driving method of the present invention.

CCD(10)は、受光した画像を光電変換して映像情報を
得るもので、パルス駆動されることに依り、画面単位で
連続する映像信号X(t)を出力する。この映像信号X(t)
信号処理回路(11)に於いてサンプルホールド、ガンマ
補正等の処理が施されてビデオ信号Y(t)として外部機器
に出力される。
The CCD (10) obtains video information by photoelectrically converting a received image, and outputs a continuous video signal X (t) on a screen-by-screen basis by being pulse-driven. The video signal X (t) is subjected to processing such as sample hold and gamma correction in the signal processing circuit (11) and output as a video signal Y (t) to an external device.

一方CCD(10)の転送電極には、読出クロック発生回路
(12)から転送クロックφが供給され、基板には排出
クロック発生回路(13)から排出制御クロックφsubが
供給される。これらクロック発生回路(12)(13)に
は、動作タイミング及び動作期間を設定する読出タイミ
ング信号FT及び排出期間設定信号DTが夫々読出タイミン
グ発生回路(14)及び排出期間設定回路(15)から供給
される。この読出タイミング発生回路(14)及び排出期
間設定回路(15)は、垂直走査信号VD及び水平走査信号
HDに基づいて動作し、排出期間設定回路(15)は露光量
判定回路(16)の判定出力に応じて排出期間を伸縮制御
する。
On the other hand, the transfer clock φ F is supplied from the read clock generation circuit (12) to the transfer electrode of the CCD (10), and the discharge control clock φsub is supplied from the discharge clock generation circuit (13) to the substrate. The clock generation circuits (12) and (13) are supplied with the read timing signal FT and the discharge period setting signal DT for setting the operation timing and the operation period from the read timing generating circuit (14) and the discharge period setting circuit (15), respectively. To be done. The read timing generation circuit (14) and the discharge period setting circuit (15) are provided with a vertical scanning signal VD and a horizontal scanning signal.
The discharge period setting circuit (15) operates based on HD, and the discharge period is expanded / contracted according to the determination output of the exposure amount determination circuit (16).

露光量判定回路(16)は、CCD(10)から得られる映像
信号X(t)のレベルを判定し、適正範囲よりレベルが高け
れば露光抑制信号CLOSEを出力し、逆に適正範囲よりレ
ベルが低ければ露光促進信号OPENを出力する。
The exposure amount determination circuit (16) determines the level of the video signal X (t) obtained from the CCD (10), and outputs an exposure suppression signal CLOSE if the level is higher than the proper range, and conversely if the level is higher than the proper range. If it is low, the exposure promotion signal OPEN is output.

第3図は、第2図の動作を示すタイミング図である。FIG. 3 is a timing diagram showing the operation of FIG.

読出タイミング信号FTは、垂直走査信号VDのブランキン
グ期間毎の所定のタイミングにタイミングパルス イを
発生し、このタイミングパルス イの入力で読出クロッ
ク発生回路(12)はクロックパルス ロを発生する。一
方、排出期間設定信号DTは垂直走査信号VDの立上りで低
レベルとなり、CCD(10)の露光量に応じて決まるタイ
ミングで再び高レベルとなるもので、低レベルの期間を
排出期間として設定する。また、この排出期間設定信号
DTの低レベルから高レベルへの立上りのタイミングは、
露光抑制信号CLOSEで遅らせられ、露光促進信号OPENで
早められるように構成される。この様な構成は、例えば
水平走査信号HDでカウントアップされるステップカウン
タと、立上りのタイミングを水平走査線数で記憶し、露
光抑制信号CLOSEでカウントアップ、露光促進信号OPEN
でカウントダウンされるアップダウンカウンタとを用
い、両カウンタの出力の一致をコンパレータで検知し、
そのコンパレータの出力をフリップフロップのセット入
力とし、垂直走査信号VDの立上りをリセット入力とし
て、そのフリップフロップの出力を排出期間設定信号DT
とすることで得られる。
The read timing signal FT generates a timing pulse I at a predetermined timing in each blanking period of the vertical scanning signal VD, and the read clock generation circuit (12) generates a clock pulse B at the input of this timing pulse I. On the other hand, the discharge period setting signal DT becomes low level at the rising edge of the vertical scanning signal VD and becomes high level again at the timing determined according to the exposure amount of the CCD (10), and the low level period is set as the discharge period. . Also, this discharge period setting signal
The timing of the rise of DT from low level to high level is
It is configured so that it is delayed by the exposure suppression signal CLOSE and accelerated by the exposure promotion signal OPEN. In such a configuration, for example, a step counter that counts up with the horizontal scanning signal HD and a rising timing are stored as the number of horizontal scanning lines, and the exposure suppression signal CLOSE counts up and the exposure promotion signal OPEN.
By using the up-down counter which is counted down by, the coincidence of the outputs of both counters is detected by the comparator,
The output of the comparator is used as the set input of the flip-flop, the rising edge of the vertical scanning signal VD is used as the reset input, and the output of the flip-flop is used as the discharge period setting signal DT.
It can be obtained by

排出期間設定信号DTが低レベルとなると、転送クロック
φは水平走査信号HDのブランキング期間に低レベルに
なると共に、排出制御クロックφsubが高レベルとな
る。従って、水平走査信号HDのブランキング期間中にCC
D(10)の深さ方向のポテンシャルが第1図の破線で示
すようになり、光電荷が排出される。
When the discharge period setting signal DT becomes low level, the transfer clock φ F becomes low level during the blanking period of the horizontal scanning signal HD and the discharge control clock φsub becomes high level. Therefore, during the blanking period of the horizontal scanning signal HD, CC
The potential in the depth direction of D (10) becomes as shown by the broken line in FIG. 1, and the photocharge is discharged.

排出期間設定信号DTが低レベルから高レベルに立上った
後には、転送クロックφは、読出タイミング信号FTの
タイミングパルス イが入力されるまで高レベルに保持
され、排出制御クロックφsubは低レベルに保持され
る。このときには、第1図の実線のようなポテンシャル
が形成され、光電荷に蓄積される。従って、排出期間設
定信号DTが低レベルから高レベルに立上るタイミングか
ら読出タイミング信号FTがタイミングパルス イを発生
するタイミングまでの期間が光電変換期間Eとして設定
され、この光電変換期間Eに一画面分の映像情報が蓄積
される。
After the discharge period setting signal DT rises from the low level to the high level, the transfer clock φ F is held at the high level until the timing pulse y of the read timing signal FT is input, and the discharge control clock φsub is low. Hold on to the level. At this time, a potential as shown by the solid line in FIG. 1 is formed and accumulated in the photocharge. Therefore, the period from the timing when the discharge period setting signal DT rises from the low level to the high level to the timing when the read timing signal FT generates the timing pulse is set as the photoelectric conversion period E, and one screen is displayed in this photoelectric conversion period E. Minute video information is accumulated.

以上の構成に依れば、CCD(10)の露光量が適正範囲よ
り高くなると排出期間設定信号DTの立上りのタイミング
が1H(水平走査信号HDの1周期)単位で遅れるために光
電変換期間Eが短縮され、逆に適正範囲より低くなると
排出期間設定信号DTの立上りのタイミングが早められる
ために光電変換期間Eが伸長され、何れの場合にもCCD
(10)の露光量が適正範囲内に収まるように制御され
る。
According to the above configuration, when the exposure amount of the CCD (10) becomes higher than the proper range, the rising timing of the discharge period setting signal DT is delayed by 1H (one cycle of the horizontal scanning signal HD), so that the photoelectric conversion period E Is shortened, and conversely, when it is lower than the proper range, the rising timing of the discharge period setting signal DT is advanced and the photoelectric conversion period E is extended.
The exposure amount of (10) is controlled so that it falls within an appropriate range.

ところで、通常のCCD(10)に於いては、光電荷の排出
動作を行っている期間中にも映像信号X(t)を順次出力し
ていることから、排出動作の際のノイズが映像信号X(t)
に重畳する虞れがある。そこで、本実施例では上述の転
送クロックφを第3図に示す如く変動させ水平走査信
号HDのブランキング期間に同期して光電荷の排出を行え
ば映像信号X(t)への影響は極めて少なくなる。また、排
出制御クロックφsubを水平走査信号HDのブランキング
期間に同期して変動させることでも同様に映像信号X(t)
へのノイズの重畳を防止できる。
By the way, in the normal CCD (10), since the video signal X (t) is sequentially output even during the period when the photocharge discharging operation is performed, the noise during the discharging operation causes the video signal. X (t)
May be superimposed on. Therefore, in the present embodiment, if the transfer clock φ F is changed as shown in FIG. 3 and the photocharges are discharged in synchronization with the blanking period of the horizontal scanning signal HD, the influence on the video signal X (t) is not affected. Extremely low. Similarly, by changing the discharge control clock φsub in synchronization with the blanking period of the horizontal scanning signal HD, the video signal X (t)
It is possible to prevent the noise from being superimposed on.

尚、本実施例に於いては、光電荷の排出期間を垂直走査
信号VDの立上りから露光量に応じて決まるタイミングま
での期間に設定しているが、排出期間の終了時点が同じ
であれば排出期間の始まりを垂直走査信号VDの立上りの
タイミングに一致させる必要はない。
In this embodiment, the discharge period of the photocharges is set to the period from the rising of the vertical scanning signal VD to the timing determined according to the exposure amount, but if the end time of the discharge period is the same. It is not necessary to match the start of the discharge period with the rising timing of the vertical scanning signal VD.

特に、本発明の如き駆動方法に於いては、極めて短い期
間で光電荷の排出を完了することも可能であるために排
出期間を1H期間以内とすることも考えられる。
Particularly, in the driving method according to the present invention, it is possible to complete the discharge of the photocharges in an extremely short period, so that it is possible to set the discharge period to within 1H period.

(ト) 発明の効果 本発明に依れば、CCD固体撮像素子の受光感度の向上及
び蓄積容量の増大が望める。また、受光感度の低下及び
蓄積容量の減少なしにCCDの駆動クロックの変動範囲を
小さくすることが可能であることから、省電力化が望め
る。
(G) Effect of the Invention According to the present invention, it is expected that the light receiving sensitivity and the storage capacity of the CCD solid-state imaging device will be improved. In addition, since it is possible to reduce the variation range of the CCD drive clock without lowering the light receiving sensitivity and the storage capacity, power saving can be expected.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明駆動方法を説明するポテンシャル図、第
2図は本発明駆動方法を採用した露光制御方法の構成を
示すブロック図、第3図はそのタイミング図、第4図は
縦型オーバーフロードレイン方式のCCD固体撮像素子の
要部平面図、第5図はX−X′線断面図、第6図はY−
Y′線のポテンシャル図である。 (1)……半導体基板、(2)……P−Well領域、
(3)……チャネルストップ領域、(4)……拡散領
域、(5a)(5b)……転送電極、(10)……CCD、(1
1)……信号処理回路、(12)……読出クロック発生回
路、(13)……排出制御クロック発生回路、(14)……
読出タイミング発生回路、(15)……排出期間設定回
路、(16)……露光量判定回路。
FIG. 1 is a potential diagram for explaining the driving method of the present invention, FIG. 2 is a block diagram showing the structure of an exposure control method adopting the driving method of the present invention, FIG. 3 is its timing diagram, and FIG. 4 is a vertical overflow. FIG. 5 is a cross-sectional view taken along line XX ′ of FIG. 5, and FIG. 6 is Y-
It is a potential diagram of Y'line. (1) …… Semiconductor substrate, (2) …… P-Well region,
(3) …… Channel stop region, (4) …… Diffusion region, (5a) (5b) …… Transfer electrode, (10) …… CCD, (1
1) …… Signal processing circuit, (12) …… Read clock generation circuit, (13) …… Discharge control clock generation circuit, (14) ……
Readout timing generation circuit, (15) ... discharge period setting circuit, (16) ... exposure amount judgment circuit.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板の一主面に所定の深さで基板と
は逆導電型のウェル領域が設けられると共に、上記半導
体基板上に上記ウェル領域を被って複数の転送電極が配
置され、光電変換に依って発生する光電荷を蓄積するチ
ャネル領域が上記転送電極の下の上記ウェル領域内に形
成される縦型オーバーフロードレイン方式のCCD固体撮
像素子の駆動方法に於いて、上記半導体基板の表面側か
ら深部への電荷の移動を阻止する電位障壁を上記ウェル
領域内に形成して上記光電荷を上記チャネル領域に蓄積
する際に上記転送電極に印加する第1の電位及び上記半
導体基板に印加する第2の電位に対し、上記転送電極に
印加する電位を上記第1の電位より低電位とすると共に
上記半導体基板に印加する電位を上記第2の電位より高
電位として上記ウェル領域内の電位障壁を消滅させ、上
記チャネル領域中の不要な光電荷を上記半導体基板側に
排出せしめることを特徴とする固体撮像素子の駆動方
法。
1. A well region having a conductivity type opposite to that of the substrate is provided at a predetermined depth on one main surface of a semiconductor substrate, and a plurality of transfer electrodes are arranged on the semiconductor substrate so as to cover the well region. In a method of driving a vertical overflow drain type CCD solid-state imaging device in which a channel region for accumulating photocharges generated by photoelectric conversion is formed in the well region under the transfer electrode, the semiconductor substrate of the semiconductor substrate A first potential applied to the transfer electrode when the photo barrier is accumulated in the channel region by forming a potential barrier in the well region that blocks the movement of charges from the surface side to the deep region, and the semiconductor substrate The potential applied to the transfer electrode is lower than the first potential and the potential applied to the semiconductor substrate is higher than the second potential with respect to the applied second potential. It abolished the potential barrier in the region, the driving method of the solid-state imaging device unnecessary light charge in the channel region, characterized in that to discharge to the semiconductor substrate side.
【請求項2】請求項第1項記載の固体撮像素子の駆動方
法に於いて、水平及び垂直方向に走査される固体撮像素
子の垂直走査期間中、垂直走査期間の始まりから途中ま
での第1の期間に上記チャネル領域の光電荷を上記半導
体基板側に排出せしめた後、残余の第2の期間に上記半
導体基板の表面側から深部側への電荷の移動を阻止する
電位障壁を上記ウェル領域内に形成して上記チャネル領
域に光電荷を蓄積し、この第2の期間に蓄積した光電荷
から一画面分の映像情報を得ることを特徴とする固体撮
像素子の駆動方法。
2. The method for driving a solid-state image pickup device according to claim 1, wherein during the vertical scanning period of the solid-state image pickup device which is scanned in the horizontal and vertical directions, the first to the middle of the vertical scanning period. After the photocharges of the channel region are discharged to the semiconductor substrate side during the period of, the potential barrier that blocks the movement of the charge from the surface side of the semiconductor substrate to the deep side is applied to the well region during the remaining second period. A method of driving a solid-state image pickup device, comprising: forming a photoelectric charge in a channel region, accumulating photocharges in the channel region, and obtaining image information for one screen from the photocharges accumulated in the second period.
【請求項3】請求項第2項記載の固体撮像素子の駆動方
法に於いて、上記チャネル領域中の光電荷を水平走査の
帰線期間内に限って上記半導体基板側に排出せしめるこ
とを特徴とする固体撮像素子の駆動方法。
3. The method for driving a solid-state image pickup device according to claim 2, wherein the photocharges in the channel region are discharged to the semiconductor substrate side only within a blanking period of horizontal scanning. And a method for driving a solid-state image sensor.
JP1096713A 1989-04-17 1989-04-17 Driving method for solid-state imaging device Expired - Lifetime JPH0775405B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1096713A JPH0775405B2 (en) 1989-04-17 1989-04-17 Driving method for solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1096713A JPH0775405B2 (en) 1989-04-17 1989-04-17 Driving method for solid-state imaging device

Publications (2)

Publication Number Publication Date
JPH02274184A JPH02274184A (en) 1990-11-08
JPH0775405B2 true JPH0775405B2 (en) 1995-08-09

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Country Link
JP (1) JPH0775405B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2725714B2 (en) * 1991-01-04 1998-03-11 シャープ株式会社 CCD solid-state imaging device
JP2010040668A (en) * 2008-08-01 2010-02-18 Panasonic Corp Solid-state imaging device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59185475A (en) * 1983-04-06 1984-10-22 Canon Inc Driving method of solid-state image pickup element
JPH0814663B2 (en) * 1986-06-27 1996-02-14 株式会社リコー Collimating lens for semiconductor laser

Also Published As

Publication number Publication date
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