JPH0774385A - Electrostatic induction type avalanche photodiode - Google Patents

Abstract

PURPOSE:To provide electrostatic induction type APD operating at a low voltage without losing high-speed high-gain characteristics. CONSTITUTION:P<-> layer 22 is formed on a semiconductor substrate 21 of p<+> and dispersion p layer 23 is buried onto the p<-> layer 22. N<+> layer 26 is formed on the p<-> layer 22 where the p player 23 is buried. Also, a cathode electrode 27 and an anode electrode 30 are formed on the n layer 26 and on the lower surface of the semiconductor substrate 21. respectively. SiO2 film 29 covers nearly all region of a flat surface including the surface of the n<+> layer 26, thus protecting the element below the SiO2 film 29 and at the same time retaining insulation between the Al wiring (not shownhere) deposited on the SiO2 film 29 and the element below the SiO2 film 29.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static induction avalanche photodiode.

[0002]

2. Description of the Related Art Conventionally, an avalanche photodiode (APD) has been used for optical communication as a photodetector having a high speed and a high multiplication factor. As an APD capable of performing uniform multiplication, there is one disclosed in JP-A-60-178673.

By the way, a general reach-through type APD
Has a structure as shown in FIG. This APD
Includes a p ⁻ type epitaxial layer 2 formed on a p ⁺ type semiconductor substrate 1, and a p layer 3 for forming a strong electric field where avalanche multiplication occurs and an n ⁺ layer 6 serving as a cathode are formed on the epitaxial layer 2. They are sequentially formed, n ⁺ pp ^- to form a p ⁺ structure. The cathode electrode 7 is provided on the upper surface of the n ⁺ layer 6.
However, an anode electrode 10 is formed on the lower surface of the semiconductor substrate 1, and by applying a voltage of about 100 V between the electrodes 7 and 10, a depletion layer extending from the n ⁺ layer 6 to the p layer 3 direction is formed. To the semiconductor substrate 1, and n
By the light incident through the SiO ₂ film 9 formed on the ⁺ layer 6, electrons and holes generated in the p ⁻ type epitaxial layer 2 are respectively directed to the n ⁺ layer 6 and the p ⁺ type semiconductor substrate 1. To accelerate. Since a strong electric field is applied to the p layer 3, the electrons injected into this region are avalanche multiplied.
Further, a guard ring 4 is provided on the outer periphery of the n ⁺ layer 6,
Leakage current and breakdown in the n ⁺ layer 6 are prevented. Incidentally, the SiO ₂ film 9 covers the substantially whole area of a plane including the surface of the n ⁺ layer 6, not Al wiring (shown deposited on the SiO ₂ film 9 at the same time protecting the elements of the lower SiO ₂ film 9 ) And the element under the SiO ₂ film 9 are kept insulated.

In the conventional APD having such a structure, the p-layer 3 for multiplication utilizing avalanche breakdown and the p ⁻ -type epitaxial layer 2 for light absorption are vertically separated from each other, and are about 100V. The operating voltage enables high-speed and high-sensitivity light detection.

[0005]

[SUMMARY OF THE INVENTION However, longitudinal sectional structure in this manner, n ⁺ pp as shown in FIG. 7 ^- has the following problem when it has a p ⁺ structure.

The voltage at which the depletion layer generated from the pn junction between the epitaxial layer 2 and the n ⁺ layer 6 reaches the semiconductor substrate 1 and reaches through is the voltage p which forms the avalanche high electric field.
It is the sum of the electric field integrals of both the layer 3 and the p ⁻ epitaxial layer 2 that absorbs light and generates carriers. For this reason, especially when it is desired to thicken the region of the epitaxial layer 2 of p ⁻ ,
The operating voltage of the APD becomes very high because the voltage required to reach through the depletion layer increases.

The voltage applied to the avalanche strong electric field forming portion (p layer 3) by the operating voltage is controlled by the layer thickness of the p layer 3 and the impurity concentration. However, these p layers 3
It is very difficult to control the layer thickness and the impurity concentration of the avalanche, the voltage applied to the avalanche strong electric field forming portion cannot be controlled accurately, and it is difficult to design the avalanche multiplication gain to an arbitrary voltage.

The present invention has been made in view of the above problems, and has a novel structure of the electrostatic induction AP capable of reducing the operating voltage without impairing the high speed and high sensitivity characteristics.
It is intended to provide D.

[0009]

In order to solve the above problems, the present invention is directed to an electrostatic induction avalanche photodiode, which includes a first conductivity type low resistance semiconductor layer and a low resistance semiconductor. A first-conductivity-type high-resistance semiconductor layer formed on the layer, a first-conductivity-type low-resistance semiconductor region dispersed and embedded only in a part of a surface layer portion on the high-resistance semiconductor layer, and a low-resistance The semiconductor layer of the second conductivity type is formed on the high resistance semiconductor layer in which the semiconductor region is embedded.

[0010]

According to this structure, first, by applying a relatively low reverse bias to the static induction avalanche photodiode, the semiconductor layer of the second conductivity type and the high resistance semiconductor layer of the first conductivity type are formed. The depletion layer easily reaches through to the first conductivity type low resistance semiconductor layer from the interface. At this time, the electric field strength inside the first-conductivity-type low-resistance semiconductor region is very high even when a relatively low reverse bias is applied because the carrier concentration is high. Then, when light is incident on the high-resistance semiconductor layer of the first conductivity type, carriers are generated therein. The generated carriers are efficiently electrostatically induced in the low resistance semiconductor portion to which a strong electric field is applied, and avalanche breakdown occurs in the low resistance semiconductor portion to be multiplied.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In the description, the same elements will be denoted by the same reference symbols and redundant description will be omitted.

First, the structure and operating principle of an APD according to an embodiment of the present invention will be described with reference to FIG. Figure 1 (a)
Shows a perspective configuration showing this APD in a partial cross section.

A p ⁻ layer 22 is formed on a p ⁺ semiconductor substrate 21.
And the dispersed p layer 2 is formed on the p ⁻ layer 22.
3 is embedded. The p in which the p layer 23 is embedded
^An n ⁺ layer 26 is formed on the ⁻ layer 22. Also, n
^{On the +} layer 26, the cathode electrode 27 is provided on the semiconductor substrate 21.
Anode electrodes 30 are formed on the lower surface of each.
Incidentally, the SiO ₂ film 29 covers substantially the whole area of a plane including the surface of the n ⁺ layer 26, not Al wiring to be deposited on the SiO ₂ film 29 at the same time protecting the elements of the lower SiO ₂ film 29 (shown ) And the element under the SiO ₂ film 29 are kept insulated.

Next, referring to FIGS. 1 (b) to 1 (c), the AP
The operating principle of D will be described.

FIG. 1 (b) shows an enlarged vertical sectional structure of a portion surrounded by a dotted line in FIG. 1 (a). FIG. 1C shows the electric field intensity distribution a1 on the cross sections A1 and A2 in FIG.
a2 and FIG. 1 (d) are cross-sections B1, B2 in FIG. 1 (a).
The upper field intensity distributions b1 and b2 are shown respectively.

First, when a reverse bias is applied between the electrodes 27 and 30, the depletion layer reaches the semiconductor substrate 21 from the vicinity of the interface between the n ⁺ layer 26 and the p ⁻ layer 22, and the p ⁻ layer 22 laterally. It also spreads in the direction. A depletion layer extends from the interface between the n ⁺ layer 26 and the p layer 23 toward the semiconductor substrate 21.

Si, which is an antireflection film, is formed on such an APD.
When light enters from above the O ₂ film 29, carriers are mainly generated in the p ⁻ layer 22. Of the generated carriers, the electrons 100 and 102 drift and travel into the p-layer 23 according to the electric field intensity distributions of FIGS. 1C and 1D,
The holes 101 and 103 are accelerated toward the semiconductor substrate 21.

That is, the electron 100 is b in FIG.
1, the electric field has a gentle gradient in the distance Y direction, and the electric field has a gentle gradient in the distance −X direction as indicated by a1 in FIG. 1C. These electric fields induce the electron 100 in the positive Y direction and the negative X direction,
It is implanted into the p layer 23. The electron 102 is also a2 in FIG.
In the electric field having a gradual gradient in the distance X direction as shown in FIG. 2, and after being accelerated in the right direction (X positive direction) in the drawing by this electric field, the distance Y direction as shown in b1 of FIG. Is introduced into an electric field having a gentle gradient, and thereafter, is injected into the p layer 23 in the same manner as the electrons 100.

As shown by b2 in FIG. 1D, the p layer 23
Since a strong electric field is applied inside, the electrons 100 and 102 injected into this region are avalanche multiplied and n ^+.
A signal current flows through the layer 26. Further, the electrons that have not been induced into the p layer 23 are also directly injected into the n ⁺ layer 26 and contribute to the signal current.

FIG. 2 shows a carrier concentration distribution in the depth direction on the cross sections B1 and B2 for realizing the electric field strength shown in FIG. 1 (d). As is clear from the figure, p
The concentration of the ⁺ semiconductor substrate 21 is about 1 × 10 ²⁰ cm ⁻³ , p ⁻
The layer 22 has a concentration of about 1 × 10 ¹³ cm ⁻³ , the p layer 23 has a concentration of about 1 × 10 ¹⁸ cm ⁻³ , and the n ⁺ layer 26 has a concentration of about 1 × 10 ^20.
cm ^-3 .

Various patterns are conceivable as the arrangement pattern of the p-layer 23. As an example of this, dot-shaped, mesh-shaped, and concentric (corner) -shaped patterns are shown in FIGS.

In FIG. 3A, p layers 23 having a dot diameter of several μm are arranged in the p ⁻ layer 22 at intervals of 10 to 20 μm. Further, in FIG. 4A, a mesh p-layer 23 having a mesh interval of 10 to 20 μm is arranged in the p ⁻ layer 22. In FIG. 5A, concentric polygonal p-layers 23 having a spacing of 10 to 20 μm are arranged in the p ⁻ layer 22. Further, the p ⁻ layer 22 and the p layer 23 may be replaced with each other as shown in FIGS.

As described above, according to the above electrostatic induction type APD, the following effects can be obtained. First
Further, from the vicinity of the interface between the n ⁺ layer 26 and the p ⁻ layer 22, the depletion layer reaches the semiconductor substrate 21 at a low operating voltage (several to several tens of volts), and carriers generated by the incidence of light are p
Since the avalanche multiplication is performed by the strong electric field induced in the layer 3 and applied thereto, it is possible to perform photodetection with a high amplification factor at a low operating voltage. Second, even if the avalanche multiplication is unstable in each p-layer 3, the characteristics of the electrostatic induction APD as a whole are made uniform, so that highly reliable photodetection is possible. .

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made.

For example, FIG. 6 shows the electrostatic induction type APD of FIG.
In order to achieve uniform multiplication and high reliability on the light-receiving surface, a guard ring 24 is provided around the n ⁺ layer 26, and the electrode 27 in FIG. 1 is replaced by a hollow disk-shaped electrode 47 to achieve uniform light detection. It is an example. A p-type channel stopper 31 is formed below the wiring 28 in order to prevent negative charges from being induced in the surface layer of the p ⁻ layer 22 by applying a positive voltage to the wiring 28 on the SiO ₂ film 29. ing. With such a configuration, it is possible to detect light with higher reliability.

[0026]

As described above, according to the present invention, the carriers generated by the incidence of light on the high resistance semiconductor layer are electrostatically induced in the low resistance semiconductor region to which the strong electric field is applied, and avalanche multiplication is performed. Therefore, it is possible to perform photodetection with high voltage and high multiplication gain at low voltage. Further, since it operates at a low voltage, it can be applied to the photodetection of long wavelength light that requires a wide depletion layer region.

Further, by having the dispersed low resistance semiconductor region, the voltage applied to the low resistance semiconductor region can be accurately controlled, and the avalanche multiplication gain can be designed to an arbitrary voltage. . Since the multiplication gain and the operating voltage can be changed by designing the pattern of the low resistance semiconductor portion, the degree of freedom in designing the operating characteristics within one chip can be increased.

[Brief description of drawings]

FIG. 1 is a perspective view partially showing a perspective view of a perspective configuration according to an embodiment of the present invention and an explanatory diagram for explaining an operating principle.

FIG. 2 is a diagram showing a carrier concentration distribution in a depth direction on a vertical cross section shown in FIG. 1 (d).

FIG. 3 is a diagram showing an arrangement example of p layers according to an embodiment of the present invention.

FIG. 4 is a diagram showing an arrangement example of p layers according to an embodiment of the present invention.

FIG. 5 is a diagram showing an arrangement example of p layers according to an embodiment of the present invention.

FIG. 6 is a perspective view showing a partial perspective view of a perspective structure according to an embodiment of the present invention.

FIG. 7 is a perspective view showing a perspective structure of a conventional reach-through APD in a partial vertical section.

[Explanation of symbols]

1, 21 ... Semiconductor substrate, 2.22 ... Epitaxial layer,
3, 23 ... P layer, 6, 26 ... N ⁺ layer, 7, 10, 27,
30, 47 ... Electrodes, 9, 29 ... SiO ₂ films, 4, 24 ...
Guard ring, 28 ... Wiring.

Claims (1)

[Claims] 1. A low resistance semiconductor layer of a first conductivity type, a high resistance semiconductor layer of a first conductivity type formed on the low resistance semiconductor layer, and a part of a surface layer portion on the high resistance semiconductor layer. A low-conductivity-type semiconductor region of a first conductivity type dispersedly embedded only in the semiconductor layer, and a second-conductivity-type semiconductor layer formed on the high-resistance semiconductor layer in which the low-resistance semiconductor region is embedded. An electrostatic induction avalanche photodiode characterized by the above.