JPH0738140A - Avalanche photodiode - Google Patents

Abstract

PURPOSE:To provide an APD which is high in sensitivity to light of a long wavelength band and response speed. CONSTITUTION:An avalanche photodiode is equipped with a high-resistive P-type silicon substrate 1 of FZ crystal 200mum to 300mum in thickness and 1kOMEGA.cm or above in resistivity, a P-type anode layer 8 formed on the rear of the high- resistive P-type silicon substrate 1, a P-type intense electric field forming layer 3 which is more doped than the P-type silicon substrate l and formed on the front of the P-type silicon substrate 1, and an N-type cathode layer 5 formed on the P-type intense electric field forming layer 3. All the thickness of the high-resistive P-type silicon substrate 1 is made to serve as a photodetecting region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reach-through avalanche photodiode having a light absorption layer entirely in the thickness direction of a silicon substrate and an amplification layer utilizing avalanche breakdown in which an electric field is uniformly controlled. .

[0002]

2. Description of the Related Art FIG. 7 shows a general reach-through type avalanche photodiode according to the prior art (hereinafter referred to as
"Conventional example 1"). As shown in FIG. 7, this avalanche photodiode (hereinafter, referred to as “APD”) has p
^A p ⁻ type epitaxial layer 22 is grown on a ⁺ type semiconductor substrate 21 to form a light absorption region, and a p layer 23 for an avalanche electric field and an n ⁺ layer 24 serving as an anode are formed thereon by double diffusion. ^{It has a +} pp ^- p ⁺ structure. That is, the p-region 23 for avalanche multiplication and the p ^- region 22 for light absorption are separated from each other, and
The depletion layer reaches through by operating voltage before and after, and becomes a high-speed and high-sensitivity photodetector. Incidentally, apart from the layers p ^- -type epitaxial layer, p-type channel stopper layer 25
And n-type guard ring layers 26 are formed on both sides of the n ⁺ layer 24.

Further, FIG. 8 shows n ⁺ np ^- pp ^- p designed for lowering voltage and uniforming avalanche electric field.
An APD having a ⁺ structure is shown (hereinafter referred to as "conventional example 2"). Also for this APD, p for avalanche multiplication
The layer 31 and the p ⁻ layer 32 for absorbing light are separated from each other, and the operation is equivalent to that of the reach-through APD described above.
A thin p ⁻ layer 32 having a high resistance is provided between the p layer 31 for forming a strong electric field and the cathode n layer 33, and a uniform strong electric field region is formed in this region. This prevents the p-layer 31 having a high impurity concentration and the cathode n-layer 33 from overlapping so as to suppress the variation in carrier concentration and to form the p-layer 3 for forming a strong electric field.
Even if the impurity concentration of 1 is increased, the tunnel effect is prevented from occurring, and the low voltage control of the avalanche breakdown is enabled. In addition, the presence of the n-type cathode layer 33 having a lower impurity concentration (0.1 Ω · cm to 1 Ω · cm) than the low-resistance n ⁺ -type cathode layer 34 allows the impurity concentration of the low-resistance n ⁺ -type cathode layer 34 to be increased. Maximum electric field E _max due to variations
Can be suppressed.

Further, another conventional technique is shown in FIG. Here, the sectional structure is n ⁺ np ^−.
Japanese Patent Laid-Open No. 4-256376 discloses an APD having a pp ^-- p ^-- p ⁺ structure and capable of forming a uniform avalanche multiplication electric field with good reproducibility and a method for manufacturing the same.
"Conventional example 3"). The sectional structure in this case is also substantially the same as that of FIG. 8, and the high resistance layer for light absorption is a p ^-- type silicon layer formed by the epitaxial growth method.

Separately from this, a semiconductor device as shown in FIG. 10A is disclosed in Japanese Patent Application Laid-Open No. 61-206261 as a technique for increasing the withstand voltage (hereinafter, "conventional example 4"). That). That is, the APD area is triple p
Enclosed with a mold guard ring to increase the breakdown voltage.

[0006]

DISCLOSURE OF THE INVENTION Problem to be Solved by the Invention
In PD, the thickness of the p ⁻ type epitaxial layer 22 cannot be increased. This is because as the thickness of the wafer increases, the strain on the wafer increases.
This is because growth exceeding m is difficult. Also, the specific resistance of the p ⁻ type epitaxial layer 22 cannot be sufficiently increased. Specifically, when the thickness of the epitaxial layer 22 is about 50 μm or less, the specific resistance also reaches a limit of about 200 Ωcm, and a value of about 100 Ωcm is usually adopted. Therefore, of the light with a wavelength of 0.4 μm to 1.2 μm that can be originally absorbed by silicon, the light with a wavelength of 0.9 μm or less can be absorbed by the epitaxial layer in this APD, and the light with a longer wavelength than that can have a quantum efficiency. Will be considerably reduced.

On the other hand, when an APD that uses a high resistance substrate, which is an FZ wafer, is manufactured by a method similar to the method for manufacturing the reach-through type APD described above, FIG.
According to this, since the specific resistance of the substrate 41 becomes 1 KΩ · cm or more, the depletion layer sufficiently expands, and
The sensitivity for long-wavelength light of 9 μm to 1.2 μm is increased. However, the applicable range of the impurity profile of the p-type strong electric field layer 42 is remarkably reduced, causing many problems such as insufficient breakdown voltage, reduction of multiplication factor, deterioration of gain uniformity, increase of noise, etc. You cannot get the characteristics.

Further, it is conceivable to adopt the structure (conventional example 2) designed as shown in FIG. 8 to obtain the above-described avalanche structure for detecting long wavelength light, but n ⁺ np ^- p
0.1 Ωcm to 1 Ω in p ^- p ⁺ structure epitaxial layer
Since the breakdown voltage of the junction formed between the low resistance n layer 33 set to the value of cm and the p diffusion layer 35 around the device is low, it is not possible to design a high operating voltage. Therefore, the depletion layer does not spread sufficiently and a strong electric field is not applied, so that high-speed and long-wavelength light (0.9 μm to 1.
APD for detection of 1 μm) cannot be realized.
Further, with such a structure, the specific resistance of the n layer 33 is increased to increase the n ⁻
In the case of a layer, the strong electric field region where avalanche occurs is n ^−.
Since it extends over both the layer 33 and the p ⁻ layer 32, the factor of variation doubles, and conversely the controllability deteriorates.

Further, in the APD according to the conventional example 3 of FIG.
Since it is necessary to perform avalanche operation at a low voltage, n
The p ⁻ layer 32 is provided below the layer 33, and the concentrations of the n layer 33 and the p layer 31 above and below the p ⁻ layer 32 are set high. Therefore, since the impurity concentration is high at both the junction between the n layer 33 and the peripheral p layer 35 separating the n layer 33, the electric field is increased and the breakdown voltage cannot be increased. In particular, since the surface side of the p layer 35 has the highest concentration, the withstand voltage cannot be increased in the peripheral portion of the cathode n layer 33.

Further, in the semiconductor device of FIG. 10 (a) according to the conventional example 4, the impurity profile in the AA 'cross section is as shown in FIG. 10 (b), and the p-type impurity concentration is near the surface. It is quite high. For this reason, the depletion layer is less likely to spread in the portion where the impurity concentration on the surface is high, so that a strong electric field is generated and breakdown occurs.

Therefore, an object of the present invention is to provide an APD having high sensitivity in a long wavelength band and capable of high speed response.

[0012]

In order to solve the above problems, the APD according to the present invention has a thickness of 200 μm to 30 μm.
A high resistance p-type silicon substrate having a specific resistance of 1 kΩ · cm or more made of a 0 μm FZ crystal, a p-type anode layer formed on the back surface of the high-resistance p-type silicon substrate, and a front surface side of the high-resistance p-type silicon substrate A high-resistance p-type silicon substrate, which is more highly doped than the high-resistance p-type silicon substrate formed above, and an n-type cathode layer formed on the p-type strong electric field formation layer. It is characterized in that it is a light receiving region.

Further, the high resistance p-type silicon substrate is thinned from the back surface at least in the light receiving region to have a thickness of 200 μm.
.About.300 .mu.m, and a p-type strong electric field forming layer is formed by doping a p-type impurity in the light receiving region on the surface side of the high-resistance p-type silicon substrate. An n-type epitaxial growth layer is formed on the surface, the light-receiving region portion forms an n-type cathode layer, and an n-type impurity is doped on the surface side of the n-type cathode layer to form an n-type cathode contact layer. Is desirable.

Further, a p-type isolation layer is formed in the n-type epitaxial growth layer so as to surround the light receiving region, and the p-type isolation layer extends from the surface of the n-type epitaxial growth layer into the high resistance p-type silicon substrate. Need to be present.

[0015]

According to the above construction, the thickness is 200 μm to 300 μm.
Since the high-resistance p-type silicon semiconductor substrate of μm serves as the light absorption layer, light is absorbed in a wide area deep from the light incident surface. Therefore, the long wavelength side (0.
The absorption rate at 9 μm to 1.2 μm) increases.

Further, since the p-type silicon semiconductor substrate is made of FZ crystal and has a high resistance of 1 kΩ · cm or more, the depletion layer is sufficiently spread by applying a high voltage to the APD, the capacitance is reduced, and a high-speed response is achieved by carrier electric field traveling. Will be possible.

Further, a p-type strong electric field forming layer is formed in the light-receiving region on the surface side of the high resistance p-type silicon substrate, and an n-type epitaxial growth layer is formed on these surfaces to form the n ^- type cathode. Since the n ⁺ -type cathode contact layer is formed on the surface side of the layer, a light-receiving region other than the periphery forms a strong electric field, and at the same time, it is possible to increase the breakdown voltage around the n-type cathode layer.

Further, a p-type isolation layer is formed in the n-type epitaxial growth layer so as to surround the light receiving region, and the p-type isolation layer extends from the surface of the n-type epitaxial growth layer into the high resistance p-type silicon substrate. Since the n-type cathode region is separately formed, the impurity concentration of the p-type separation layer can be suppressed to a low level to weaken the electric field and increase the breakdown voltage.

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

First, the structure of the APD according to the embodiment of the present invention (see FIG. 3) will be described with reference to FIGS. 1 and 2 according to its manufacturing method.

First, an ingot having an impurity concentration of 10 ¹³ cm ^-3 or less by FZ crystal growth is cut out and polished to obtain a substrate 1 which is a p ^-- type high resistance silicon wafer as shown in FIG. 1 (a). prepare. Next, as shown in FIG. 1B, a SiO ₂ film 2 is formed on the substrate 1, the SiO ₂ film 2 is patterned by lithography, and then the substrate 1 is doped with boron by ion implantation or the like. The avalanche multiplication p-layer 3 that is a strong electric field forming layer and the first isolation p-layer 4 for device isolation are formed in the same process.
The implantation amount of boron is about 1 × 10 ¹² cm ⁻² , and the surface peak concentration after doping is about 2 × 10 ¹⁶ cm ⁻³ .

Next, as shown in FIG. 1 (c), SiO ₂
The film 2 is removed to form a cathode n ⁻ layer 5 which is a uniform epitaxial layer having an impurity concentration of 2 × 10 ¹⁴ cm ⁻³ or less. It is necessary that the thickness of the n ⁻ layer 5 is thicker than that of the cathode contact n ⁺ layer 7 which will be formed later. Further, in the separation process of the cathode n ⁻ layer 5 by the p layer which is performed later, diffusion is performed at a low concentration. Therefore, when the cathode n ⁻ layer 5 is thick, the thermal process increases and affects the profile. Therefore, the cathode n ⁻ layer 5 is designed to have a thickness of about 3 to 5 μm.

Next, as shown in FIG. 1 (d), the cathode the n ^- SiO ₂ film 9 is formed on the layer 5, after patterning by lithography, cathode the n ^- to separate the layers 5, cathode n ^- the layer 5 by ion implantation or the like performs spreading of the second separating p-layer 6 of low concentration. At this time, the second isolation p-layer 6 is aligned with the position of the first isolation p-layer 4 so as to be connected while being diffused vertically, and the cathode n ⁻ layer 5 is separated from the surrounding elements by a pn junction. Insulate.

Next, as shown in FIG. 2A, the SiO ₂ film 9 above the p-layer 3 for avalanche multiplication is etched to reduce the resistance of the upper surface of the cathode n ⁻ layer 5.
The cathode contact n ⁺ layer 7 is formed by doping the n ⁻ layer 5 with impurities. At this time, the impurities to be doped are
Surface concentration is around 10 ²⁰ cm ^-2 , diffusion depth is 0.5 μm ~
It is set to about 1.0 μm. Further, a SiO ₂ film is formed at a predetermined height on the second p-layer 6 for separation, and is integrated with the already formed SiO ₂ film 9.

Next, since the entire substrate 1 having a high resistance of p ^-- type in the thickness direction serves as a light absorbing layer, the thickness of the substrate 1 can be changed depending on the thickness of the depletion layer, the response speed, the photosensitivity and the like. In order to carry out the adjustment, as shown in FIG. 2B, only the area corresponding to the light receiving portion of the substrate 1 is etched from the back surface. Other than this, as a means for adjusting the thickness of the substrate 1, there is a method of mechanically and chemically polishing the entire back surface of the substrate 1 to change the thickness. Further, a SiO ₂ film having a desired thickness is formed on the n ⁺ layer 7 and becomes integral with the already formed SiO ₂ film 9.

Next, as shown in FIG. 2C, in order to use the back surface of the substrate 1 as a cathode electrode, the back surface of the substrate 1 is doped with a high concentration of impurities to form ap ⁺ layer 8, and ohmic contact is formed. Make contact.

Finally, as shown in FIG. 3, a contact hole is formed in a part of the SiO ₂ film 9 on the n ⁺ layer 7, Al is buried in this contact hole, and, as shown in the figure, Al is removed. Forming a thin film, and forming the cathode electrode 1
Form 0. In addition, the p ⁺ layer 8 formed on the back surface of the substrate 1
The anode electrode 11 is formed in a desired region so that ohmic contact can be obtained. Further, a SiO ₂ film 12 is formed on the surface of the p ⁺ layer 8 immediately below the area corresponding to the light receiving portion. When incident on the surface, the Al film 13 formed around the cathode functions as a light shielding film. APD of this embodiment thus obtained is n ⁺ n ^- pp ^-
It will have a p ⁺ structure. FIG. 4 shows the n of this APD.
⁺ N ^- pp ^- p ⁺ structure is intended to show the electric field distribution and impurity concentration distribution, and FIG. (A) shows the electric field distribution, Fig. (B) is, n ⁺ n ^- pp ^- The p ⁺ structure is shown, and FIG. 7C shows the impurity concentration distribution. Cathode n
^- While the strong electric field region for avalanche multiplication is formed around a region of the layer 5, p ^- the entire thickness direction of the -type high resistance substrate 1, so-called depletion layer spreads that can function as a light absorbing layer You can see that

Next, the operation of the APD configured as above will be described. Light within the wavelength range (0.4 μm to 1.2 μm) from the visible light region to the infrared region is APD
When incident on the p ^- type high resistance substrate 1 which is a light absorption layer
The absorption of light occurs at the site, and electron-hole pairs are generated. These electrons and holes move in the depletion layer by an electric field given from the outside, and the electrons are injected into the cathode n ⁻ layer 5 where a strong electric field is formed, where an avalanche multiplication action occurs.
This is the operating principle of the reach-through type APD. As can be seen from this operating principle, the reach-through type APD is based on completely depleting the substrate 1 having a high absorption resistance of p ^-- type, which is a light absorption layer. Enables high-speed design determined by response.

The light received by the APD is 0.9 μm to 1.2 μm.
In the case of m near-infrared light, there are two conditions, that is, the p ⁻ type high resistance substrate 1 that is a light absorption layer has a thickness of 200 μm or more and that the substrate 1 is depleted entirely. is necessary. That is, it is necessary to increase the resistance of the substrate 1 and increase the operating voltage of the APD. By the way, the extension of the depletion layer from the n ⁺ p junction depends on the applied voltage and the specific resistance of the substrate 1. That is, the depletion layer width W is given by _{W = α (V / N A} ) 1/2 ... (1). Here, V is an applied voltage, N _A is the impurity concentration of p ⁻ , and α is a proportional constant. APD according to the present embodiment
Since the resistance value of the substrate 1 is a high resistance layer of 1 kΩ · cm or more, the depletion layer can be expanded to 200 μm or more at 400 V and to 300 μm at 800 V.

On the other hand, when the width of the depletion layer is expanded in this way, the increase rate ΔE of the electric field strength with respect to the increase of the applied voltage.
_{Since max} / ΔV becomes small and the change of the multiplication factor with respect to the fluctuation of the voltage becomes small, more stable characteristics can be obtained. However, conversely, when the impurity profile of the avalanche multiplication p-layer 3 that forms a strong electric field deviates from the design value and E _max (maximum electric field strength value) with respect to the set voltage VR (for example, 800 V) changes, the set voltage is set to 800 V. E _max cannot be adjusted even by shaking before and after. In other words, it is a major problem to accurately reproduce the impurity profile of the avalanche multiplication p-layer 3 that forms a strong electric field in a certain set voltage range (± 10% of the reference value, etc.) and suppress variations. This is also directly related to the uniformity characteristics when the effective area of the APD expands and becomes large in area.

In this embodiment, the avalanche multiplication p-layer 3 is used.
However, the total amount of impurities in the p-layer 3 for avalanche multiplication does not change even after the manufacturing process because it is bonded to the n ⁻ layer 5 for cathode buffer having a low impurity concentration, and the implantation amount is faithfully reflected. The characteristics can be obtained. Also,
Since the cathode n ⁻ layer 5 has a high resistance, the maximum electric field strength depends almost entirely on the amount of impurities in the avalanche multiplication p layer 3, but in the n ⁻ layer 5, this E _max is almost flattened. , The maximum electric field strength variation ΔE of the cathode n ⁻ layer 5 with respect to the dispersion of the n ⁺ layer 7 formed by diffusion
_max is extremely small. For example, the operating voltage of APD is 8
As a condition for the multiplication factor is 100 when set to ^{00V ± 50V, n + n -} pp - By the p ⁺ structure can be stabilized. In addition, the control, n ^-
It can be controlled only by the total amount of impurities implanted into the avalanche multiplication p-layer 3 below the layer 5. Also, n ⁺ n ^- p
With the p ^-- p ⁺ structure, the impurity profile from the junction where avalanche multiplication is performed to the avalanche multiplication p-layer 3 can be controlled stably, and the p-type avalanche multiplication p Layer profiles can be easily realized.

In the present embodiment, since the high resistance p ^-- type substrate 1 is entirely a light absorption layer, light is absorbed in a deep and wide area from the light incident surface, and the length of the absorption band of silicon is long. The absorption rate on the wavelength side (0.9 μm to 1.2 μm) increases.
Therefore, it is possible to remarkably improve the sensitivity on the long wavelength side (0.9 μm to 1.2 μm), where the conventional APD has poor sensitivity. For example, when the light wavelength is 1.06 μm, in the conventional APD, when the high resistance p ⁻ layer is about 30 μm, the quantum sensitivity efficiency is up to 17%, whereas in the present embodiment, the thickness of the substrate 1 is Is set to 300 μm, the quantum sensitivity efficiency can be up to 82%.

The standard thickness of the substrate 1 varies depending on the diameter of the wafer, but normally the thickness is 300 μm to 5 μm.
Since it is about 100 μm and can be reduced to 300 μm or less by etching, it is possible to expand the design range for the wavelength of light and the performance of APD. In this case, the light can be incident not only from the front surface but also from the back surface, and the short wavelength A for wavelengths 200 nm to 500 nm is targeted.
It can also support PD. Furthermore, the substrate 1 is FZ
Since manufacturing is performed using crystal growth, a high resistance of 1 kΩ · cm or more can be realized, so that a depletion layer is expanded by applying a high voltage to the APD, a low capacitance is achieved, and a high-speed response due to carrier electric field travel becomes possible. That is, if the depletion layer is expanded ten times, the junction capacitance is reduced to 1/10, and a large area can be easily achieved. For example, under a load condition of 50Ω, the operating range of an APD with a diameter of 10 mm is 100 MHz.
The above can be realized.

As a method for enabling operation at a high applied voltage, a low resistance n ⁺ layer 7 is surrounded by a cathode n ⁻ layer 5 as a strong electric field layer and self-aligned by epitaxial growth which is a common process. To manufacture. The n ^-
By setting the impurity concentration in the layer 5 to 2 × 10 ¹⁴ cm ⁻³ or less, a breakdown voltage of 1000 V or more can be obtained. This is also
It can be realized by interaction with the first and second p layers 4 and 6 for separation. Further, the cathode n ^- layer 5 is
Since the impurity concentration is low and uniform at the same time, stable high withstand voltage characteristics can be reproduced.

Further, the cathode n ⁻ layer 5 around the n ⁺ layer 7
The n ⁻ / n ⁺ -type cathode layer including the cathode guard ring is a p-type diffusion layer for the first and second p-type isolation layers.
It is formed by being separated by the layers 4 and 6. In order to realize a high breakdown voltage, the concentration of the cathode n ⁻ layer 5, which is the cathode guard ring, is low at the same time that the concentrations of the first and second separation p layers 4 and 6 are also low, so that the electric field is reduced. Can be weakened and high breakdown voltage can be achieved. Further, the concentration of the first and second separation p layers 4 and 6 is lowered, and further the first and second separation p layers 4 and 6 are formed. That is, as shown in FIG.
The stepwise electric field distribution can be obtained by forming the one columnar p-layer as a multi-layered p-layer having a diameter of 2 μm to 3 μm, which enables control of the breakdown voltage. Here, FIG. 5B shows the impurity cross-sectional profile of the APD according to the present embodiment.
Shown in. The impurity cross-sectional profile is shown in FIG.
It is in the AA 'cross section of (a). From this figure, it is understood that the APD according to the present example has a low impurity concentration peak due to the entire impurity doping, and therefore the depletion layer expands and the stepwise electric field strength expands. . Therefore, it can be seen that a higher breakdown voltage is realized as compared with the technique shown in Conventional Example 4.

Here, since the high-resistance n ⁻ layer is an epitaxial layer having a thickness of about 3 to 5 μm, a case of separating the n ⁻ layer by the p layer only by diffusion from the surface will be considered.
The impurity concentration on the surface becomes high, and the above effect cannot be obtained, resulting in poor withstand voltage. However, in this embodiment, a part of the first isolation p-layer 4 is raised from the substrate 1, and the raised portion is used to diffuse the second p-layer 4 from the surface.
Since the p-layer 6 for separation of the cathode n ⁻ layer 5 is formed,
Of the cathode n ⁻
The layers 5 are reliably separated. As a result, the first separation p
The concentration of the layer 4 can be reduced to 1 × 10 ¹⁷ cm ⁻³ or less, and the breakdown voltage can be increased by the stepwise electric field distribution described above. Therefore, in the present embodiment, the peripheral breakdown voltage of 1000 V or more, the n ⁻ layer 5 which is a uniform and highly controllable strong electric field layer, and 200 μ
The light absorption region and the depletion layer have a thickness of m or more.

In particular, comparing the APD according to this embodiment with the APD according to Conventional Example 3, the following can be said. That is, the APD according to the present embodiment does not have the p ⁻ layer of the APD according to Conventional Example 3 shown in FIG.
In the present embodiment, the portion of D which is a simple n layer is n.
^- differs significantly in that become the layer has a high resistance. Furthermore, in Conventional Example 3, as shown in FIG.
^{Since the} electric field strength is strong in the ⁻ layer, the avalanche effect is generated in the p ⁻ layer, whereas in the APD according to the present embodiment, the electric field strength is strong in the n ⁻ layer as shown in FIG. Therefore, the difference is that the avalanche effect is generated in the n ⁻ layer. Therefore, in Conventional Example 3, since the strong electric field is formed in the p ⁻ layer to perform the avalanche operation, it is necessary to manufacture the n layer with low resistance by epitaxial growth. Further, when the n layer has a low resistance, the breakdown voltage around the n layer becomes low, and it is impossible to design a high operating voltage. Therefore, the depletion layer does not spread sufficiently and long wavelength sensitivity cannot be obtained. Furthermore, even if the n-layer can be manufactured with high resistance, a strong electric field is formed across both the p ⁻ layer and the n-layer, and avalanche breakdown occurs in both layers, so it is very important to control the avalanche multiplication. Becomes difficult. On the other hand, A according to the present embodiment
In PD, p ^- there is no layer, n ^- forming only strong electric field in the layer, n ^- since the only cause avalanche multiplication layer facilitates control of the avalanche multiplication. Further, in the APD according to the present embodiment, a strong electric field is formed in the n ⁻ layer other than the periphery, and at the same time, the junction of the peripheral n ⁻ layer has an effect that the electric field is weak and the breakdown voltage can be increased, and a high operating voltage can be applied. Therefore, the depletion layer can be sufficiently widened, and long wavelength sensitivity can be obtained. Moreover, since the specific resistance of the p ⁻ layer can be set to 1 kΩ · cm or more, the depletion layer spreads, thereby improving the long wavelength sensitivity of 0.9 μm to 1.2 μm.

[0038]

As described in detail above, according to the APD of the present invention, a p-type silicon semiconductor substrate having a high resistance is used as the light absorbing layer and the light absorbing layer is formed in the entire thickness direction. Therefore, the absorptance increases at 0.9 μm to 1.2 μm, which is the long wavelength side of the absorption band of silicon. Therefore, it is possible to remarkably improve the absorption rate in the region where the conventional silicon photodiode has poor sensitivity.

Further, since the depletion layer spreads, it becomes possible to reduce the capacity and to achieve a high speed response by traveling the carrier electric field. Furthermore, providing a guard ring around the APD also has the effect of increasing the breakdown voltage.

[Brief description of drawings]

FIG. 1 is a diagram showing each step diagram in a manufacturing process of an avalanche photodiode according to the present embodiment.

FIG. 2 is a diagram showing each process chart in the manufacturing process of the avalanche photodiode according to the present embodiment.

FIG. 3 is a sectional view of an avalanche photodiode according to the present embodiment.

FIG. 4 is a diagram showing an electric field distribution and an impurity concentration distribution corresponding to the structure of the avalanche photodiode according to the present embodiment.

FIG. 5 is a diagram showing an impurity cross-sectional profile of the avalanche photodiode according to the present embodiment.

FIG. 6 is a diagram showing a structure of an avalanche photodiode according to a conventional example and a corresponding electric field distribution and impurity concentration distribution.

FIG. 7 is a diagram showing a general reach-through type avalanche photodiode according to Conventional Example 1.

FIG. 8 is a cross-sectional view of an avalanche photodiode according to Conventional Example 2.

FIG. 9 is a sectional view of an avalanche photodiode according to Conventional Example 3.

FIG. 10 is a diagram showing a cross-sectional view and an impurity profile of a semiconductor device according to a conventional example for the purpose of increasing the breakdown voltage.

FIG. 11 is a cross-sectional view of an avalanche photodiode manufactured by a conventional method.

[Explanation of symbols]

1 ... Substrate, ₂ , 9, 12 ... SiO ₂ film, 3 ... Avalanche multiplication p-layer, 4 ... First isolation p-layer, 5 ... n ^- layer, 6
... second p-layer for separation, 7 ... n ⁺ layer, 8 ... p ⁺ layer, 10 ...
Cathode electrode, 11 ... Anode electrode.

Claims (3)

[Claims] 1. A high resistance p-type silicon substrate having a specific resistance of 1 kΩ · cm or more made of an FZ crystal having a thickness of 200 μm to 300 μm, and a p-type anode layer formed on the back surface of the high resistance p-type silicon substrate. And a p-type strong electric field forming layer which is formed on the front surface side of the high resistance p-type silicon substrate and is more highly doped than the high resistance p-type silicon substrate, and an n-type formed on the p-type strong electric field forming layer. An avalanche photodiode comprising a cathode layer, wherein the high resistance p-type silicon substrate is used as a light receiving region. 2. The high-resistance p-type silicon substrate is thinned from the back surface to a thickness of 200 at least in the light receiving region.
μm to 300 μm, the light receiving region on the surface side of the high resistance p-type silicon substrate is doped with p-type impurities to form the p-type strong electric field forming layer, and the high-resistance p-type silicon substrate and the p-type strong electric field forming layer are formed. An n-type epitaxial growth layer is formed on the surface of the n-type strong electric field forming layer, and the light-receiving region portion forms the n-type cathode layer. The n-type impurity is doped on the surface side of the n-type cathode layer to form an n-type cathode layer. The avalanche photodiode according to claim 1, wherein a cathode contact layer is formed. 3. The n-type epitaxial growth layer comprises:
The p-type isolation layer is formed so as to surround the light receiving region, and the p-type isolation layer extends from the surface of the n-type epitaxial growth layer into the high-resistance p-type silicon substrate. The avalanche photodiode described.