JPH0773695A - Self test circuit for ram - Google Patents

Abstract

PURPOSE:To provide a self test circuit for a RAM capable of testing even a content corresponding to the address 0 of a test objective RAM. CONSTITUTION:Address pattern and data pattern with (m) bits and (n) bits (m, n are positive integers) are supplied from an LFSR for generating address and the LSFR for generating data to a testing RAM respectively, and the output data is compressed by the LFSR for compressing the data with (n) bits, and a signature is generated. Then, the signature is compared with an expected value signature, and the normal/defective condition of the RAM is decided. The LFSR 20 supplying the address pattern with (m+1) bit and the LFSR 30 (1 is a positive integer) supplying the data pattern with (n-1) bit are awaited, and the (m) bit of the LFSR 20 are connected to the address input terminal of the RAM 1, and the (n-1) bit of the LFSR 30 and the (1) bit of the LFSR 20 are connected to the data input terminal of the RAM 1 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a RAM self-test circuit, and more particularly to a RAM self-test circuit using a linear feedback shift register (hereinafter referred to as LFSR) for address generation and data generation.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional RAM self-test circuit. The RAM 1 has a structure in which the number of address inputs is m bits and the number of data inputs is n bits, and the data output is also n bits. The m-bit address input terminal of the RAM1 has an m-bit length LFSR2 for address generation.
And an n-bit data input terminal is connected to an n-bit data generation LFSR3. The n-bit data output terminal has an n-bit length LFS for data compression.
R4 is connected.

Next, the operation of the circuit shown in FIG. 2 will be described. In response to a clock signal from a test control circuit (not shown), the address generation LFSR2 and the data generation LFS.
R3 supplies the address pattern and the data pattern to the RAM1, respectively. LFSR4 for data compression is RAM
Compress the output data from 1 to generate a signature.
After the required number of clocks are applied, the finally generated signature is compared with the expected value signature that has been obtained in advance to test whether the RAM 1 is defective.

[0004]

However, in the conventional self-test circuit as shown in FIG. 2, an all-zero pattern is generated due to the nature of the address generating LFSR which is connected to the address input terminal and supplies the address pattern. There was a problem that it could not be done. Therefore, there is a problem that the contents of the RAM corresponding to the address 0 cannot be tested and the self-test cannot be completely performed.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a RAM self-test circuit capable of testing the contents corresponding to address 0 of the RAM under test. And

[0006]

According to the present invention, in response to a clock signal from a test control circuit, a linear feedback shift register (LFSR) for address generation and an LFSR for data generation respectively have m bits and n bits ( (m and n are positive integers respectively) are supplied to the test RAM, the output data is compressed and extracted from the n-bit data compression LFSR to generate the signature, and this signature is the expected value. In the RAM self-test circuit that determines the quality of the RAM by comparing with the signature, (m
The first LF supplying an address pattern of +1) bits
An SR and a second LFSR (l is a positive integer) for supplying a data pattern of (n-1) bits are prepared, and the first LFSR is provided.
M bits of the LFSR of the second LFSR to the address input terminal of the RAM, and the (n-1) bits of the second LFSR and the first
And 1 bit of the LFSR are connected to the data input terminals of the RAM.

[0007]

According to the present invention, the bit length of the LFSR for generating the address pattern is configured to be longer than the bit length of the address input terminal of the RAM under test, and the surplus bits are connected to the data input terminal of the RAM. Therefore, an all 0 pattern can be generated in the LFSR for generating the address pattern, and as a result, the contents of the RAM at the address 0 can be tested.

[0008]

1 is a block diagram of a RAM self-test circuit according to an embodiment of the present invention.
In the present invention, the bit lengths of the address generation LFSR 20 and the data generation LFSR 30 are configured as follows.

First, the bit length of the address generating LFSR 20 is configured as (m + 1) bits (l is a positive integer) longer than the number of bits m of the address input terminal of the test target RAM 1. Then, m bits of them are connected to the address connection terminals of the RAM 1, and the remaining 1 bits are connected to 1 of the n input terminals of the RAM 1.

Next, the bit length of the data generating LFSR 30 is configured as (n-1) bits shorter than the bit number n of the data input terminal of the RAM 1. Then, this is connected to the (n-1) terminals of the data input terminal. That is, in the embodiment shown in FIG. 1, the upper bits of the address generation LFSR 20 are connected to the data connection terminal of the RAM 1 by leaving only 1 left, and the remaining data input terminal receives data from the data generation LFSR 30 of (n-1) bit length. It is configured to input the input pattern.

FIG. 3 is a block circuit diagram showing an example of the circuit configuration of the address generating LFSR 20. Where m
An example in the case of + 1 = 5 bits is shown. In the case of a 5-bit length LFSR, as shown in the figure, it is composed of five flip-flops 32 to 36 and one exclusive OR gate 31. The position to connect the feedback loop is determined based on the primitive polynomial obtained by the code logic. With proper connection, 2 ⁵ -1 types of patterns excluding all 0s are sequentially generated in pseudo random numbers every time a clock is applied. can do.

In the embodiment shown in FIG. 3, the flip-flop 3
2 to 36 are connected in cascade, one input terminal of the exclusive OR gate 31 is connected to the Q terminal of the flip-flop 34, and the other input terminal is connected to the Q terminal of the flip-flop 36. Then, the output terminal of the exclusive OR gate 31 is input to the data input terminal of the flip-flop 32 to output the pattern output to the flip-flops 32 to 36.
It is configured to be obtained from the Q output terminal of. As a result, every time a clock signal from a test control circuit (not shown) is input to the clock input terminal, the flip-flops 32 to
31 types of patterns are output from 36 Q terminals.

According to this structure, the LFSR for generating the address pattern cannot generate the pattern of all 0 as usual, but the pattern of all 0 can be applied to the address of the RAM under test. That is, as an example,
Considering the case of l = 1 and m = 4, the address generation LF
This is because the SR20 cannot generate the all-zero pattern 00000 but can generate the pattern 10000, so that the lower 4-bit pattern 0000 at this time can be applied to the address of the RAM1. In the above embodiment, the case where the upper bits of the address generating LFSR 20 are left and connected to the data input terminal of the RAM 1 has been described, but the bits connected to the data input terminal need to be limited to the upper bits. There is no problem with the lower bits or the intermediate bits.

[0014]

As described above in detail with reference to the embodiments, in the present invention, the bit length of the address pattern generator is made longer than the input bit length of the RAM under test, and the surplus bits are input to the data of the RAM. Since it is connected to the terminal, the pattern of all 0s can be configured as an address input. Therefore, the contents of the RAM at address 0 can be tested. Further, there is an advantage that the bit length of the data pattern generator can be realized with a configuration shorter than the bit length of the data input terminal of the RAM under test.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention.

FIG. 2 is a block circuit diagram of a conventional self-test circuit.

FIG. 3 is a block circuit diagram showing a configuration example of an LFSR.

[Explanation of symbols]

 1 RAM 4 LFSR for data compression 20 LFSR for address generation 30 LFSR for data generation 31 Exclusive OR gate 32-36 flip-flop

Claims (1)

[Claims] 1. In response to a clock signal, R and m-bit and n-bit (m and n are positive integers) address patterns and data patterns are respectively read from a shift register for address generation and a shift register for data generation.
A first self-test circuit for a RAM, which supplies a data to an AM and compares the output data from the RAM with an expected value obtained in advance to judge whether the RAM is good or bad. Shift register and a second shift register (l is a positive integer) for supplying a data pattern of (n-1) bits, wherein m bits of the first shift register are address input terminals of the RAM. Of the second shift register (n-
A self test circuit for a RAM, characterized in that 1) bit and 1 bit of the first shift register are respectively connected to a data input terminal of the RAM.