JPH05126916A - Semiconductor integrated circuit with testing function - Google Patents

Abstract

PURPOSE:To judge the normal/defective state of a pseudo-random number generator and data compressing device by giving pseudo-random number data to the data compressing device and using their compressed results when self-testing is not performed. CONSTITUTION:The control of this semiconductor integrated circuit 1 at testing time is performed by using control signals A, B, and S outputted from a test control circuit 5 and the circuit 1 is controlled as a whole. Based on the control signal A, linear feedback shift register(LFSR) 3 for generating pseudo-random numbers outputs a pseudo-random number to a selector 6 which selects an LFSR 4 for compressing data in response to the control signal S. As a result, the pseudo-random number is directly inputted to the LFSR 4 for compressing data. The LFSR 4 compresses the pseudo-random number in response to the control signal B and outputs the compressed result to the outside of the circuit 1 at the end of self-testing. Therefore, the LSFRs 3 and 4 can be directly tested without operating a functional block 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit with a test function which realizes a self-test function by using a pseudo random number generator and a data compressor, and more particularly to a pseudo random number generator and a linear feedback shift register (data compression). Hereinafter, the present invention relates to a semiconductor integrated circuit with a test function using LFSR).

[0002]

2. Description of the Related Art Semiconductor integrated circuits are required to have high reliability and high density. Therefore, it is necessary to perform all tests for each function. If data is given from the outside to perform this test, the test time becomes long and the test cost increases. Therefore, recently, a test circuit for testing the semiconductor integrated circuit self-confidence is built in the same chip,
A method of performing a self test by this test circuit is adopted.

FIG. 11 is a block diagram of a semiconductor integrated circuit with a test function that realizes such a self-test function. Referring to FIG. 11, the semiconductor integrated circuit 1 includes a functional block 2 to be tested and a pseudo random number generating LFSR.
3, a data compression LFSR 4 and a test control circuit 5. The test control circuit 5 outputs control signals A and B for controlling the pseudo random number generation 3 and the data compression LFSR 4. The pseudo random number generating LFSR 3 responds to the control signal A from the test control circuit 5 to generate pseudo random number data as test data, and gives the generated pseudo random number data to the functional block 2. The functional block 2 is a block that processes various logic signals in accordance with predetermined logic to achieve various functions during normal operation. This functional block 2 processes the pseudo random number data from the pseudo random number generating LFSR 3 at the time of the test according to a predetermined logic. The data compression LFSR 4 is responsive to the control signal B from the test control circuit 5 to function block 2
Compress the test data processed by. As an example of the pseudo random number generating LFSR 3 and the data compressing LFSR 4 having such a function, a document (COMPUTER
Published by SCIENCE PRESS, M.S. ABRAMO
VICI, M .; A. BREUR, A .; D. FRIEDM
By AN, DIGITAL SYSTEMS TESTI
NGANDTESTABLE DESIGN p445
~ 447, p473-474).

FIG. 12 is a block diagram in which the pseudo random number generating LFSR described in the above document has a 4-bit structure.
FIG. 13 is a block diagram in which the data compression LFSR has a 4-bit configuration. With reference to FIG. 12, the pseudo random number generating LFSR 3 takes an exclusive OR of the outputs of the four flip-flops 50 connected in series, the first-stage flip-flop, and the third-stage flip-flop. And an exclusive OR gate 52.

In operation, each flip-flop 52 is inputted with a clock (not shown) for latching data, and is configured to shift to the next stage according to the change of the clock. When applying feedback to the preceding stage, a feedback signal is received by the exclusive OR gate 52 and output. The output position (generally called a tap) of a flip-flop to which feedback is applied can be generally obtained by a characteristic polynomial. By optimizing the position of this tap and the number of flip-flop stages, a pseudo-random number with a maximum period of 2 ^N -1 is generated. 12
In the case of the 4-bit configuration, a maximum of 2 ⁴ -1 pseudo random numbers can be generated, but 7 types of pseudo random numbers are generated because the tap positions are not optimized.

The initial value of each flip-flop 50 is set to "11".
Table 1 shows the pseudo-random numbers when the output is 10 ″ and each output is X1 to X4.

[0007]

[Table 1]

The pseudo random numbers shown in Table 1 are generated as follows. First, the initial value of each flip-flop 50 is set to "1.
110 ". Next, the value of each flip-flop is shifted to the next stage by the clock, and the exclusive OR gate 5
The values "1" and "1" of X1 and X3 are input to 2, and at the same time, the output "0" is input to the first stage flip-flop. As a result, the data changes to "0111". After that, similarly, each time a clock is input, a shift is performed to generate pseudo random numbers one after another.

FIG. 13 shows a data compressor constructed in the same way as in FIG. 12, and a data compressor which does not converge to a fixed value by optimizing the tap position can be constructed.

The operation of the semiconductor integrated circuit with a test function shown in FIGS. 11 to 13 will be described. First, during the self-test, the test control circuit 5 controls the entire integrated circuit 1. The control signal A causes the pseudo random number generating LFSR 3 to generate a pseudo random number. LF for data compression by control signal B
Data compression is performed in SR4. L for pseudo-random number generation
Each functional block 2 inside the integrated circuit 1 is operated using the pseudo random number of the FSR 3. The operation result of each functional block 2 is taken into the data compression LFSR by the control signal B, and the data is compressed here. After all the functional blocks 2 have been operated and data compression has been completed, the result of compression is output to the outside of the integrated circuit 1 to determine pass / fail. In this example, the compression result is output to the outside of the integrated circuit 1 as it is, but there is a case where a judgment circuit for comparing the expected value of the self test with the compression result is built in and the good / bad result is output to the outside.

FIG. 14 is a block diagram showing a semiconductor integrated circuit (microprocessor) using a plurality of multi-bit LFSRs. This microprocessor is based on literature (IC
CD86 processing p. 169-173
"BUILT IN SELF TEST OF T
HE8038 "). Referring to FIG.
PLA is a programmable logic array, BINARY
Is a binary counter, CROM is a ROM, ALU25
Is an arithmetic unit for comparison that compares the expected value with the actual compressed value, EA
The X register is a register that stores the comparison result in the ALU. In this configuration, three types of LFSR3 for generating pseudo random numbers (11 bits, 19 bits, 16 bits) and eight types of LFSR for data compression (16 bits × 16 bits) are used as a test circuit.
5, 18 bits, 19 bits, 37 bits), a test control circuit and a comparison arithmetic unit are provided. Since these test hardware occupies several percent to ten and several percent of the area of the semiconductor integrated circuit, defects in the test hardware itself cannot be ignored.

[0012]

In a microprocessor composed of a large number of complicated logic circuit blocks,
A test circuit using LFSR is built in to facilitate the test. In a microprocessor provided with 11 kinds of LFSRs and a control circuit as a test circuit like the conventional example,
The defect of the test circuit cannot be ignored, and the test of the test circuit itself is required. Conventionally, there has been a problem that a functional block must be operated by using a test circuit and indirectly check the normal operation of the test circuit.

Therefore, the present invention has been made in order to solve the above problems, and an object thereof is to realize a semiconductor integrated circuit capable of testing a test hardware.

[0014]

A semiconductor integrated circuit with a test function according to a first aspect of the present invention for achieving the above object comprises:
A functional block having a signal processing function, a pseudo random number generator for generating pseudo random number data, a data compressor for compressing processed data of the pseudo random number data by the functional block, the functional block, a pseudo random number generator and data compression A semiconductor integrated circuit with a test function including a test control circuit for controlling a signal generator, wherein pseudo random number data generated by the pseudo random number generator when the functional block is not tested is stored in the data compressor. It is characterized by including means for giving.

A second invention is a functional block having a signal processing function, a pseudo random number generator for generating pseudo random number data, a data compressor for compressing the processed data of the pseudo random number data by the functional block, Functional block,
What is claimed is: 1. A semiconductor integrated circuit with a test function, comprising: a pseudo random number generator; and a test control circuit for controlling a data compressor, wherein the pseudo random number generator generates a pseudo random number when the functional block is not tested. And a means for giving random number data to the test control circuit and a response data for the pseudo random number data of the test control circuit when the functional block is not tested. ..

[0016]

In the semiconductor integrated circuit with the test function according to the first aspect of the invention, when the functional block is not tested,
That is, since the pseudo random number data can be given to the data compressor when the self-test is not performed, it is possible to judge the pass / fail of the pseudo random number generator and the data compressor using the result of the data compression.

Further, in the second invention, since the pseudo random number data is given to the test control circuit and the response data to the pseudo random number data of the test control circuit is given to the data compressor when the self test is not performed, the data is compressed. The result can be used to judge pass / fail of the test control circuit.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The semiconductor integrated circuit with the test function shown in FIG.
What is different from the semiconductor integrated circuit with the test function is
The selector 6 is provided between the pseudo random number LFSR 3 and the functional block 2. The other circuits are the same as those in FIG. 11 and are denoted by the same reference numerals, and the description thereof will be appropriately omitted. In response to the select signal S from the test control circuit 5, the selector 6 selects a path for giving the data from the pseudo random number LFSR 3 directly to the LFSR 4.

Next, the operation of the semiconductor integrated circuit with a test function shown in FIG. 1 will be described. The control during the test is performed by the control signals A, B and S output from the test control circuit 5 to control the integrated circuit 1 as a whole. During the self-test,
In response to the control signal A, the pseudo random number generating LFSR 3 outputs a pseudo random number and inputs it to the selector 6. The selector 6 selects the functional block 2 side in response to the control signal S. Thereby, the pseudo random number is input to the functional block 2. After that, the functional block 2 operates using the pseudo random number as input data, and inputs the operation result to the data compression LFSR 4. The data compression LFSR 4 compresses the operation result of the functional block 2 in response to the control signal B, and outputs the compression result to the outside of the integrated circuit 1.

At the time of testing the test circuit, the control signal A outputs a pseudo random number from the pseudo random number generating LFSR 3,
Input to the selector 6. In response to the control signal S, the selector 6 selects the data compression LFSR 4 side. As a result, the pseudo random number is directly input to the data compression LFSR 4.
After that, the data compression LFSR 4 compresses the pseudo random number in response to the control signal B, and outputs the compression result to the outside of the integrated circuit 1 at the end of the self-test. As a result, the pseudo random number generation LF is operated without operating the functional block 2.
It is possible to directly test SR3 and LFSR4 for data compression.

FIG. 2 is a block diagram showing a second embodiment of the present invention. Referring to FIG. 2, the semiconductor integrated circuit with a test function is different from the semiconductor integrated circuit of FIG. 1 in that a bit compressor 7 is provided between selector 6 and data compression LFSR 4. In the bit compressor 7, the pseudo-random number generating LFSR 3 has a data length of N bits, and the data compressing LFSR 4 has a data length of M bits.
Used when> M.

In operation, when testing the test circuit, the N-bit pseudo-random number output from the selector 6 is input to the bit compressor 7. The bit compressor 7 includes a control circuit 5
In response to the control signal C from, the N-bit pseudo-random number given through the selector 7 is compressed into M bits and input to the data compression LFSR 4. Thereby, even if the bit lengths of the pseudo random number generating LFSR 3 and the data compressing LFSR 4 are different, it is possible to test each LFSR 3 and 4.

FIG. 3 shows an example in which an N-bit LFSR is used as the bit compressor 7 of FIG. FIG. 4 shows an example in which an LFSR that compresses 1-bit N-M + 1 pseudo random numbers out of N bits is used as the bit compressor of FIG. In the bit compressor of FIG. 4, the LFSR for compressing N−M + 1 bits is used.
And an M-1 bit pseudo random number can generate an M bit pseudo random number. That is, it is possible to compress only the difference in bit length.

FIG. 5 shows an example in which a plurality of exclusive OR gates are used as the bit compressor of FIG.

As is clear from the configurations of FIGS. 3 to 5, there are various modes as the bit compressor, and any configuration can be adopted as long as N bits can be compressed to M bits and randomness is not lost. Is.

In the embodiment of FIGS. 2 to 5, N>
Although the case of M is shown, when N <M, pseudo random number data with a long bit length is required.

FIG. 6 is a block diagram showing a third embodiment of the present invention. Referring to FIG. 6, the semiconductor integrated circuit with the test function is different from the semiconductor integrated circuit of FIG. 2 in that the bit compressor 7 is changed to "H" in response to a control signal D output from the control circuit 5. That is, a fixed value input circuit 8 for generating a fixed value of "" or "L" is provided.

In operation, when testing the test circuit, the N-bit pseudo random number data output from the selector 6 is input to the data compression LFSR 4. At the same time, in response to the control signal D, the fixed value input circuit 8 generates a fixed value of MN bits and inputs it to the data compression LFSR 4. As a result, data having a bit length corresponding to the number of input bits of the data compression LFSR 4 can be generated, so that not only the pseudo random number generation LFSR 3 but also the data compression LFS is generated.
The R4 test can be performed.

FIG. 7 is a circuit diagram showing an example of the fixed value input circuit 8 shown in FIG. This fixed value input circuit includes a plurality of P channel transistors TR1, a plurality of N channel transistors TR2, and an inverter 8a. The inverter 8a has its input terminal connected to receive the control signal T, and its output terminal connected to the gate of each P-channel transistor TR1. The source of each P-channel transistor TR1 is connected to the power supply voltage Vcc,
The drain electrode is connected to the data compression LFSR 4. Each N-channel transistor TR2 has its gate connected to receive the control signal D, its source grounded, and its drain connected to the data compression LFSR4.

In operation, when the control signal D is at "H" level, all of the P-channel transistor TR1 and the N-channel transistor TR2 are turned on,
The "H" level is output from the P-channel transistor TR1 and the "L" level is output from the N-channel transistor TR2. As a result, the fixed value input circuit 8
A fixed value of N bits can be generated. This M-
The N-bit fixed value is given to the data compression LFSR 4, and the data compression LFSR 4 compresses data consisting of the M-N bit fixed value and the N-bit pseudo random number data.

Incidentally, in FIG. 1, FIG. 2 and FIG.
The case of a pair of LFSRs has been described. However, even in the case of a plurality of pairs, the LFSR test may be performed in the same way. The test control circuit 5 may be controlled by an instruction of the microprocessor of the integrated circuit 1 or the like, or may be controlled by an input signal from the outside of the integrated circuit 1.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention. The semiconductor integrated circuit with a test function shown in FIG. 8 enables the test control circuit 5 to be tested. Referring to FIG. 8, the semiconductor integrated circuit with the test function is different from the semiconductor integrated circuit of FIG.
(1) A selector 16 is provided between the selector 6 and the test control circuit 5 ', and (2) A selector 26 for selecting the output data of the test control circuit 5'or the output data of the functional block 2 is provided. Is that,
(3) The test control circuit 5'includes a pair of LFSRs 3 and 4
That is, the control signals A and C for controlling and the control signals B, E and D for controlling the selectors 6, 16 and 26 are generated. Note that F is an internal signal of the control circuit 5 '. The other circuits are the same as those in FIG. 1, and the same reference numerals are given and the description thereof is appropriately omitted.

The selector 16 selects an external test control input 1T and an internally generated test control input 2T or a pseudo random number given through the selector 6 and inputs it to the test control circuit 5 '. The selector 26 selects the control signals A to E output from the test control circuit 5 ′ or the operation output of the functional block 2 and inputs them to the data compression LFSR 4.

Next, the operation of the semiconductor integrated circuit with a test function shown in FIG. 8 will be described. First, the control during the test is performed by the output control signals A to E from the test control circuit 5'to control the integrated circuit 1 as a whole. Control signal A during self-test
The pseudo random number generation LFSR 3 outputs a pseudo random number and inputs it to the selector 6. The selector 6 selects the functional block 2 side in response to the control signal B and inputs the pseudo random number to the functional block 2. The operation result of the functional block 2 in which the pseudo random number is input is selected by the selector 26 and input to the data compression LFSR 4. LFSR4 for data compression
Responds to the control signal C to compress the operation result and output the compression result to the outside of the integrated circuit 1 at the end of the self-test. The selector 16 selects the test control input values T and 2T in response to the control signal E and inputs them to the test control circuit 5.

At the time of testing the test circuit, the pseudo random number generating LFSR 3 generates pseudo random numbers in response to the control signal A. The generated pseudo random number is input to the selector 6. The selector 6 selects the test control circuit 5 side in response to the control signal B, and inputs the pseudo random number to the selector 16. The selector 16 selects a pseudo random number in response to the control signal E and inputs it to the test control circuit 5. The control signals A to E output from the test control circuit 5 are input to each test block including the LFSR3 for pseudo random number generation, and at the same time, the selector 26
Input the pseudo random number data into. Also, the test control circuit 5
The control signal F therein is also input to the selector 26. The selector 26 compresses the control signals A to F output from the control circuit 5 ′ in response to the control signal D and outputs the compression result to the integrated circuit 1.
To the outside of. By doing so, it becomes possible to directly test the pseudo random number generating LFSR 3, the data compressing LFSR 4, and the test control circuit 5 without operating the functional block 2. That is, at the time of testing the test circuit, a pseudo-random number is input to the test control circuit 5, and the control signals A to E which are the outputs of the test control circuit are data-compressed and confirmed, thereby realizing the test of the test hardware. There is.

In the embodiment of FIG. 8, the data length of the pseudo random number generating LFSR 3 and the input signal data length of the test control circuit 5'are the same, and the output signal data length of the test control circuit 5'and the data compression. The condition is that the data lengths of the LFSRs 4 for use are the same, but when the data lengths are different, it is necessary to provide a circuit for adjusting the data length as shown in FIG.

FIG. 9 is a block diagram showing the fifth embodiment of the present invention. This semiconductor integrated circuit with a test function is different from the semiconductor integrated circuit of FIG. 8 in that (1) the data length of the pseudo random number generating LFSR3 is N bits and the input signal data length of the test control circuit 5'is P bits, and N> P, the total data length of the control signals A to H is Q bits, the data length of the data compression LFSR 4 is M bits and Q> M, and (2) the selector 6 and the selector for compressing the data. A bit compression circuit 11 is provided between
That is, the data compression circuit 12 is provided between the selector 26 and the data compression LFSR 4.

In operation, when the test circuit is tested, the pseudo random number output from the selector 6 is input to the test control circuit 5. The bit compression circuit 7 compresses the N-bit pseudo random number into P bits in response to the control signal H, and the test control circuit 5
Enter in ´. The test control signals A to H having the total bit length Q output from the selector 26 are compressed into M bits by the bit compression circuit 17 and input to the data compression circuit 4.

As the bit compression circuits 11 and 12, the bit compression circuits shown in FIGS. 3 to 5 can be used.

In the fifth embodiment, the case where the data length relationship is N> P and Q> M is shown. Conversely, when N <P and Q <M, as shown in FIG. A circuit for adjusting the bit length is provided.

FIG. 10 is a block diagram showing a sixth embodiment of the present invention. The semiconductor integrated circuit with a test function is different from the integrated circuit shown in FIG. 9 in that the bit relationships are N <P and Q <M, and a fixed value input circuit 13 is provided instead of the bit compression circuit 11. That is, a fixed value input circuit 14 is provided instead of the bit compression circuit 12. The fixed value input circuit 13 generates a fixed value of P-N bits in response to the control signal J from the test control circuit 5 '. The fixed value input circuit 14 generates a fixed value of MQ bits in response to the control signal I from the test control circuit 5 '.

In operation, when testing the test circuit, the N-bit pseudo random number output from the selector 6 is input to the test control circuit 5 '. At the same time, in response to the control signal J, the fixed value of PN bits generated by the fixed value input circuit 7 is input to the test control circuit 5 '. As a result, the test control circuit 5'is provided with data corresponding to the input signal data length of the test control circuit 5 '. Test control circuit 5
Control signal A based on the P-bit data input to ‘
~ J is generated. The selector 10 selects the data A to F in response to the control signal D from the test control circuit 5 ', and supplies this to the data compression LFSR 4. At this time, the fixed value input circuit 14 receives the control signal I from the test control circuit 5 '.
In response to this, a fixed value of MQ bits is generated and given to the data compression LFSR 4. In this way, L for data compression
The data length given to FSR4 is M bits. The data compressed by the data compression LFSR 4 is output to the outside, and the output data is compared with the expected value to generate the pseudo random number generation LSFR 3 and the test control circuit 5.
'And the data compression LFSR 4 can be tested for pass / fail.

The fixed value input circuits 13 and 14
The fixed value input circuit shown in FIG.

As described above, even if the data length output from each test hardware is different, the test of the test circuit can be realized by matching the data lengths.

[0045]

As described above, according to the present invention, by effectively utilizing the LFSR provided for the test, the test circuit provided for the test can be directly tested by adding a small amount of hardware. It will be possible. Therefore,
This has the effect of improving the defect detection rate as compared with the conventional method in which the functional block is tested to indirectly confirm the normal operation of the test circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a bit compression circuit.

FIG. 4 is a block diagram showing an example of a bit compression circuit.

FIG. 5 is a block diagram showing an example of a bit compression circuit.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram of the fixed value input circuit of FIG.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a sixth embodiment of the present invention.

FIG. 11 is a block diagram of a conventional semiconductor integrated circuit with a test function.

FIG. 12 is a block diagram showing an example of a pseudo random number generating LFSR.

FIG. 13 is a block diagram showing an example of a data compression LFSR.

FIG. 14 is a configuration diagram of a conventional semiconductor integrated circuit with a test function.

[Explanation of symbols]

 1 Semiconductor integrated circuit with test function 2 Functional block 3 Pseudo-random number generation LFSR 4 Data compression LFSR 5,5 'Test control circuit 6,16,26 Selector 7,11,12 Bit compression circuit 8,13,14 Fixed value input circuit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 31, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 8

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art Semiconductor integrated circuits are required to have high reliability and high density. Therefore, it is necessary to perform all tests for each function. If data is given from the outside to perform this test, the test time becomes long and the test cost increases. Therefore, it built a test circuit for testing a semiconductor integrated circuit itself in the same chip recently,
A method of performing a self test by this test circuit is adopted.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

FIG. 11 is a block diagram of a semiconductor integrated circuit with a test function that realizes such a self-test function. Referring to FIG. 11, the semiconductor integrated circuit 1 includes a functional block 2 to be tested and a pseudo random number generating LFSR.
3, a data compression LFSR 4 and a test control circuit 5. The test control circuit 5 uses the LFSR 3 for pseudo random number generation.
And control signals A and B for controlling the data compression LFSR 4. LFSR3 for pseudo random number generation
Responds to the control signal A from the test control circuit 5, generates pseudo random number data as test data, and gives the generated pseudo random number data to the functional block 2. The functional block 2 is a block that, in a normal operation, processes various logic signals according to predetermined logic to achieve various functions. This functional block 2 processes the pseudo random number data from the pseudo random number generating LFSR 3 at the time of the test according to a predetermined logic. LFSR4 for data compression
Compresses the test data processed by the functional block 2 in response to the control signal B from the test control circuit 5.
As an example of the pseudo random number generating LFSR 3 and the data compressing LFSR 4 having such a function, a document (COMP
Published by UTERSCIENCE PRESS, M.I. AB
RAMOVICI, M .; A. BREU E R, A. D. F
RIEDMAN, DIGITAL SYSTEMS
ESTINGAND TESTABLE DESIGN
LFSR described in p445-447, p473-474).

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction content]

In operation, each flip-flop 52 is inputted with a clock (not shown) for latching data, and is configured to shift to the next stage according to the change of the clock. When applying feedback to the preceding stage, a feedback signal is received by the exclusive OR gate 52 and output. The output position (generally called a tap) of a flip-flop to which feedback is applied can be generally obtained by a characteristic polynomial. By optimizing the position of this tap and the number of flip-flop stages, a pseudo-random number with a maximum period of 2 ^N -1 (N is the number of LFSR stages) is generated. In the case of the 4-bit configuration of FIG. 12, a maximum of 2 ⁴ −1 pseudo random numbers can be generated, but 7 types of pseudo random numbers are generated because the tap positions are not optimized.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction content]

[0010] To explain the operation of the test function semiconductor integrated circuit shown in FIG 1. First, during the self-test, the test control circuit 5 controls the entire integrated circuit 1. The control signal A causes the pseudo random number generating LFSR 3 to generate a pseudo random number. Data compression is performed by the control signal B in the data compression LFSR 4. Each functional block 2 inside the integrated circuit 1 is operated by using the pseudo random number of the LFSR 3 for pseudo random number generation. The operation result of each functional block 2 is taken into the data compression LFSR by the control signal B, and the data is compressed here. After all the functional blocks 2 are operated and data compression is completed, the compression result is output to the outside of the integrated circuit 1,
Judge good / bad. In this example, the compression result is output as it is to the outside of the integrated circuit 1. However, there is a case where a judgment circuit for comparing the expected value of the self-test with the compression result is built in and the good / bad result is output to the outside.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

FIG. 14 is a block diagram showing a semiconductor integrated circuit (microprocessor) using a plurality of multi-bit LFSRs. This microprocessor is based on literature (IC
CD86 processing p. 169-173
"BUILT IN SELF TEST OF T
HE8038 6 ") are described in. With reference to the figure, PLA programmable logic array, BINA
RY is a binary counter, CROM is a ROM, ALU
25 is a comparator for comparing the expected value with the actual compressed value,
The EAX register is a register that stores the comparison result in the ALU. In this configuration, three types of LFSR3 for generating pseudo-random numbers (11 bits, 19 bits, 1
6 bits), 8 types of LFSRs for data compression (16 bits × 5, 18 bits, 19 bits, 37 bits), a test control circuit, and a comparison calculator. Since these test hardware occupies several percent to ten and several percent of the area of the semiconductor integrated circuit, defects in the test hardware itself cannot be ignored.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

At the time of testing the test circuit, the control signal A outputs a pseudo random number from the pseudo random number generating LFSR 3,
Input to the selector 6. In response to the control signal S, the selector 6 selects the data compression LFSR 4 side. As a result, the pseudo random number is directly input to the data compression LFSR 4.
Thereafter, the data compression LFSR 4 compresses the pseudo random number in response to the control signal B, and outputs the compression result to the outside of the integrated circuit 1 at the end of the test of the test circuit . As a result, the pseudo random number generating LFSR 3 and the data compressing LFSR 4 can be directly tested without operating the functional block 2.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

FIG. 8 is a block diagram showing a fourth embodiment of the present invention. The semiconductor integrated circuit with a test function shown in FIG. 8 enables the test control circuit 5 to be tested. Referring to FIG. 8, the semiconductor integrated circuit with the test function is different from the semiconductor integrated circuit of FIG.
(1) A selector 16 is provided between the selector 6 and the test control circuit 5 ', and (2) a selector 26 for selecting the output data of the test control circuit 5'or the output data of the functional block 2 is provided. Is that,
(3) The test control circuit 5'includes a pair of LFSRs 3 and 4
That is, the control signals A and C for controlling and the control signals B, E and D for controlling the selectors 6, 16 and 26 are generated. In addition, F is a test control circuit 5 '.
Is an internal signal of. The other circuits are the same as those in FIG. 1, and the same reference numerals are given and the description thereof is appropriately omitted.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction content]

Next, the operation of the semiconductor integrated circuit with a test function shown in FIG. 8 will be described. First, the control during the test is performed by the output control signals A to E from the test control circuit 5'to control the integrated circuit 1 as a whole. Control signal A during self-test
The pseudo random number generation LFSR 3 outputs a pseudo random number and inputs it to the selector 6. The selector 6 selects the functional block 2 side in response to the control signal B and inputs the pseudo random number to the functional block 2. The operation result of the functional block 2 in which the pseudo random number is input is selected by the selector 26 and input to the data compression LFSR 4. LFSR4 for data compression
Responds to the control signal C to compress the operation result and output the compression result to the outside of the integrated circuit 1 at the end of the self-test. Incidentally, the selector 16 is entered in response to select the test control input value 1 T and 2T to the test control circuit 5 'to the control signal E.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

At the time of testing the test circuit, the pseudo random number generating LFSR 3 generates pseudo random numbers in response to the control signal A. The generated pseudo random number is input to the selector 6. The selector 6 selects the test control circuit 5 ′ side in response to the control signal B and inputs the pseudo random number to the selector 16.
The selector 16 selects a pseudo random number in response to the control signal E and inputs it to the test control circuit 5 ' . Control signal A~E for output of the test control circuit 5 'inputs the pseudo-random data to the selector 26 and simultaneously input to each of the test blocks including a pseudo random number generating LFSR3. The control signal F of the test control circuit 5 'in is also input to the selector 26.
The selector 26 responds to the control signal D by the test control circuit 5
The control signals A to F outputted from ‘′ are compressed, and the compression result is outputted to the outside of the integrated circuit 1. This makes it possible to directly test the pseudo random number generating LFSR 3, the data compressing LFSR 4, and the test control circuit 5 ′ without operating the functional block 2. That is, during the testing of the test circuit 'type, the test control circuit 5' of the pseudo-random test control circuit 5 by checking the control signal A~E an output of data compression, the hardware test Test Has been realized.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

In the embodiment of FIG. 8, the data length of the pseudo random number generating LFSR 3 and the input signal data length of the test control circuit 5'are the same, and the output signal data length of the test control circuit 5'and the data compression. the data length of use LFSR4 is provided that is the same, but if the respective data lengths differ, it is necessary to provide a circuit to adjust the data length as shown in FIG.

[Procedure Amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0038

[Correction method] Change

[Correction content]

In operation, when the test circuit is tested, the pseudo random number output from the selector 6 is input to the test control circuit 5 ' . The bit compression circuit 7 responds to the control signal H with N
The pseudo random number of bits is compressed to P bits and input to the test control circuit 5 '. Further, the test control signals A to H having the total bit length Q output from the selector 26 are the bit compression circuits 17
The data is compressed to M bits and input to the data compression circuit 4.

Claims (8)

[Claims] 1. A functional block having a signal processing function,
A pseudo random number generator for generating pseudo random number data, a data compressor for compressing processed data of the pseudo random number data by the functional block, and a test control circuit for controlling the functional block, the pseudo random number generator and the data compressor. A semiconductor integrated circuit with a test function, comprising means for giving to the data compressor pseudo-random number data generated by the pseudo-random number generator when the functional block is not tested. Semiconductor integrated circuit with test function. 2. The pseudo-random number generator is a linear feedback shift register having N (N is a natural number) stages of flip-flops and an exclusive OR gate, and the data compressor is M (M is a natural number). 2. The semiconductor integrated circuit with a test function according to claim 1, wherein the semiconductor integrated circuit is a linear feedback shift register including a stage flip-flop and an exclusive OR gate. 3. The means for supplying the pseudo-random number data to the data compressor is connected between the pseudo-random number generator and the data compressor and the functional block, and is responsive to a control signal from the control circuit. 2. The semiconductor integrated circuit with a test function according to claim 1, further comprising means for selecting the data compressor. 4. A compression means for compressing the bit length of the pseudo random number generator to the bit length of the data compressor when the bit length of the pseudo random number generator is longer than the bit length of the data compressor. The semiconductor integrated circuit with a test function according to claim 1, further comprising: 5. A fixed value of the number of bits corresponding to the difference in bit length between the pseudo random number generator and the data compressor when the beat length of the pseudo random number generator is shorter than the beat length of the data compressor. 2. The semiconductor integrated circuit with a test function according to claim 1, further comprising means for supplying the data compressor. 6. A functional block having a signal processing function,
A pseudo random number generator for generating pseudo random number data, a data compressor for compressing processed data of the pseudo random number data by the functional block, and a test control circuit for controlling the functional block, the pseudo random number generator and the data compressor. A semiconductor integrated circuit with a test function, comprising means for supplying the test control circuit with pseudo random number data generated by the pseudo random number generator when the test of the functional block is not performed, A semiconductor integrated circuit with a test function, comprising means for supplying response data to the pseudo random number data of the test control circuit to the data compressor when a test is not performed. 7. The semiconductor integrated circuit with a test function according to claim 6, further comprising means for converting a bit length of the pseudo random number data into a bit length of an input signal of the test control circuit. 8. The semiconductor integrated circuit with a test function according to claim 6, further comprising means for converting a bit length of an output signal of said control circuit into a bit length of said data compressor.