JPH0771295B2 - Interframe coding transmission method - Google Patents

Description

The present invention relates to a coded transmission system for highly efficient coding and transmitting a television signal, and particularly when the influence of an error on a transmission line propagates to the next frame. The present invention relates to an interframe coding transmission method used.

[Conventional technology]

Conventionally, in this type of interframe coding transmission system, the basic configuration of the interframe encoder and the interframe decoder is that the coefficient to be multiplied by 1 in the prediction coefficient circuits 23 and 35 shown in FIG. However, if a transmission line error occurs, its effect will be propagated to the next frame and will not be permanently eliminated. Was being dealt with.

[Problems to be Solved by the Invention]

The above-mentioned conventional inter-frame coding transmission method is a method that sometimes uses intra-frame coding for transmission as a countermeasure when a transmission path error occurs, so even for an error that does not cause much visual problems. Since the intra-frame coding is performed, there is a drawback that the transmission efficiency is deteriorated.

The present invention is intended to eliminate such drawbacks of the conventional ones, and provides an interframe coding transmission method capable of eliminating the influence of an error occurring on a transmission path with almost no reduction in transmission efficiency.

[Means for Solving the Problems]

According to the present invention, the transmitting-side device (FIG. 1B) performs interframe coding of the image signal (FIG. 1516) and transmits the differential image signal (FIG. 1617 (1)) to the first transmission. Road (Fig. 1b 19b)
An interframe coding circuit (FIG. 1 in FIG. 16) for sending to the receiver, and the receiving side device (FIG. 1A) receives the differential image signal from the first transmission path. 1))
As an interframe coded transmission including an interframe decoding circuit (FIG. 8) that performs interframe decoding of the received differential image signal and outputs an interframe decoded signal (0908 in FIG. 1). In the system, the interframe coding circuit (FIG. 16) calculates the parity bit by bit for N (N is an integer of 2 or more) bits of the locally decoded output signal (FIG. 2624 in FIG. 2), The inter-frame decoding circuit includes a first parity arithmetic circuit (Fig. 2 Fig. 27) for sending out the parity calculated for each as a first parity signal to the first transmission line (Fig. 1b). (FIG. 1) calculates a parity bit by bit for N bits of the inter-frame decoded signal (0908 in FIG. 1), and calculates the parity calculated bit by bit as a second parity signal (first bit). Figure 0807) second output
And a second parity signal (0807) and a first transmission line (FIG. 1). 19b)
The first parity signal (0607 in FIG. 1) received from the first parity signal is compared to detect a parity error for each bit plane, and the weight of the parity error of the n-th bit (1 ≦ n ≦ N) is w. (N) (however, w (1) ≦ ... ≦ w
(N)), and whether or not there is an error in the nth bit (1 ≦ n ≦ N) is e (n) (however, when e (n) = 1, there is an error, and when e (n) = 0, there is no error. As) A predictive coefficient control circuit (first circuit) that generates a first predictive coefficient control signal (0703 in FIG. 1) and sends this first predictive coefficient control signal to the second transmission line (FIG. 19a). (1 Figure 7)
The interframe coding circuit (FIG. 16) receives the first prediction coefficient control signal from the second transmission line (FIG. 19a) as a first reception prediction coefficient control signal. (1116 in FIG. 1), if the magnitude of the first reception prediction coefficient control signal is 0, the prediction coefficient 1 is selected, and the magnitude of the first reception prediction coefficient control signal approaches 0. The closer the prediction coefficient is to 1, the prediction coefficient closer to 1 is selected, and the larger the magnitude of the first received prediction coefficient control signal is, the closer to 0 the prediction coefficient is selected. A prediction coefficient circuit (23) for outputting a result obtained by multiplying a prediction value (2423 in FIG. 2423) generated from a decoded output signal (2624 in FIG. 2) as a prediction signal (2321 in FIG. 2), and the reception prediction coefficient. The control signal (1116 in FIG. 1) is converted into the differential image signal (1617 (1) in FIG. 1).
And the delayed prediction coefficient control signal is delayed for a predetermined time so as to match the timing with the second prediction coefficient control signal (see FIG. 16).
17 (3)), and further includes a delay circuit (FIG. 25 in FIG. 2) for sending to the first transmission path (FIG. 19b in FIG. 1), the inter-frame decoding circuit (FIG. 8), The second predictive coefficient control signal is received from the first transmission line (FIG. 19b) as a second predictive coefficient control signal (0608 (2) in FIG. 2), and the second receive predictive coefficient control is performed. Signal magnitude is 0
If so, the prediction coefficient 1 is selected, and the closer the magnitude of the second reception prediction coefficient control signal is to 0, the closer the prediction coefficient to 1 is selected, and the magnitude of the second reception prediction coefficient control signal is selected. The larger the value is, the prediction coefficient closer to 0 is selected, and the selected prediction coefficient is used as the prediction value (FIG. 2 363 in FIG. 2) generated from the inter-frame decoded signal (FIG. 1 908).
An interframe coding transmission method is obtained which further includes a second prediction coefficient circuit (FIG. 35) that outputs the result obtained by multiplying 5) as a prediction signal (3533 in FIG. 2). .

〔Example〕

 Next, the present invention will be described with reference to examples.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which device A and device B are opposed to each other via transmission lines 19a and 19b.

In the same figure, consider the case where a transmission line error occurs in the transmission line 19b from the B side to the A side.

In the prediction coefficient control circuit 7, the second parity signal 0807 calculated in the inter-frame decoding circuit 8 and the first parity signal sent from the B-side inter-frame encoding circuit 16
0607 is compared in consideration of delay, and an error is detected for each bit plane of the image signal. Further, the parity error obtained for each bit plane is weighted differently for the upper bit and the lower bit, and the first prediction coefficient control signal 0703 calculated from the result is opposed via the transmission line 19a. It is transmitted to the interframe coding circuit 16 of the station B, and the prediction coefficient is controlled by the first prediction coefficient control signal 1116. Further, the first predictive coefficient control signal 1116 is output as a second predictive coefficient state signal 1617 (3) in the inter-frame encoding circuit 16 by delaying it with the differential image signal 1617 (1). It is transmitted in the opposite direction via 19b and the second
The prediction coefficient control signal 0608 (2) controls the prediction coefficient in the inter-frame decoding circuit 8. In this way, it is possible to control the prediction coefficient on both the transmitting side and the receiving side with respect to the error that has occurred in the transmission line 19b, and to apply a leak.

Even when a transmission line error occurs in the transmission line 19a in the reverse direction, the same operation as above is performed.

According to the present embodiment, the prediction coefficient is controlled to 1 in the state where no transmission path error occurs, and the inter-frame coding in which the frame memory output signal is directly the prediction signal is performed. On the other hand, if a transmission line error occurs,
Detects bit errors for each bit plane, weights each bit differently, and uses the result to multiply the frame memory output signal by a prediction coefficient of 1 or less to make a prediction signal and control it to leak Therefore, it is possible to efficiently suppress the influence of transmission path errors without substantially reducing the transmission efficiency.

FIG. 2 is a block diagram showing an example of the configuration on the device A side in the embodiment of FIG. 1, in which device B is connected to the transmission line interface circuit 30 via a transmission line and faces it. The figure consists of a transmitter and a receiver. In addition to the general interframe coding / decoding loop, the prediction coefficient circuit
23, 35, a delay circuit 25, parity operation circuits 27, 37, a prediction coefficient control circuit 34, and the like.

The prediction coefficient circuit 23 is controlled by the first prediction coefficient control signal 3123, and is an output signal 24 of the frame memory 24 which is an input signal.
23 is multiplied by a prediction coefficient to output a prediction signal 2321. The prediction coefficient circuit 35 is a similar circuit. The parity calculation circuit 27 calculates and outputs the parity for each bit of the locally decoded output signal 2624, and the parity calculation circuit 37 is also the same. The delay circuit 25 is a circuit for delaying the first prediction coefficient control signal 3123 and timing it with the differential image signal 2228. The prediction coefficient control circuit 34 compares the two parity signals 3734 and 3134, detects a transmission path error, calculates a prediction coefficient control signal according to the error weight, and outputs a first prediction coefficient control signal 3429. To do.

The operation when an error occurs on the transmission path from the device B side to the device A side will be described below.

In FIG. 2, the data 3031 sent from the opposite station (device B) side is input to the separation circuit 31, and the first prediction coefficient control signal 3123, the compressed image signal 3132, the parity signal 3134 and the second It is separated into the prediction coefficient control signal 3135.

First, the operation of the transmitter will be described. The separated first prediction coefficient control signal 3123 is input to the prediction coefficient circuit 23. The prediction coefficient circuit 23 receives the frame memory output signal 2423 as input, multiplies this by the prediction coefficient according to the prediction coefficient control signal 3123, and outputs the prediction signal 2321. The detailed operation of the prediction coefficient circuit 23 is the same as that of the prediction coefficient circuit 35 described later. Further, the first predictive coefficient control circuit 3123 is synchronized with the differential image signal 2228 by the delay circuit 25 and is transmitted to the partner station through the multiplexing circuit 29.

The operation of the transmitter described above is performed on the reverse line, that is, the transmission line.
This is the operation when an error occurs on 19a, and the transmission path 19b
Even when the above error occurs, the same operation as above is performed in the transmitting section on the opposite station (device B) side.

Next, the operation on the receiving side will be described. In the prediction coefficient control circuit 34, the first parity signal 3134, which is one frame period calculated for each bit plane of the image signal in the encoding circuit of the opposing device B, and the parity calculation circuit 37 The transmission path 19b is compared with the generated second parity signal 3734.
Detects the transmission path error that occurred above.

FIG. 3 is a block diagram of an example of the prediction coefficient control circuit 34. In the figure, the error bit detection circuit 40 compares the first parity signal 3134 and the second parity signal 3734 in consideration of the delay, and detects the presence or absence of an error for each bit plane on a frame-by-frame basis. . Further, in the weighting circuit 39, different weighting is performed depending on the presence or absence of an error in each bit plane, and as a result, the first prediction coefficient control signal
Outputs 3429. For example, as a simple example, in the case of an N-bit image signal, the weighting in the parity error of the nth bit (1 ≦ n ≦ N) is w (n) (however, w (1) ≦ w
(2) ≤ ... ≤ w (N-1) ≤ w (N)), and the presence or absence of an error in the nth bit (1 ≤ n ≤ N) is e (n) (however, e (n) = 1). , And there is no error when e (n) = 0), the prediction coefficient control signal C which is the output can be defined as follows.

The first prediction coefficient control circuit 3429 is multiplexed with the data on the transmission side by the multiplexing circuit 29 and transmitted to the prediction coefficient circuit 23 of the interframe coding circuit of the partner station. Further, as described above, the transmitted first predictive coefficient control signal controls the predictive coefficient of the partner station and is again transmitted to the local station as the second predictive coefficient control signal 3135. In the prediction coefficient circuit 35, the output signal 3635 of the frame memory 36 is multiplied by the prediction coefficient according to the second prediction coefficient control signal 3135, and the prediction signal 3533 is output.

FIG. 4 shows a prediction coefficient value (α) for the prediction coefficient control signal (C) as an example of the prediction coefficient circuit 35. In the example of the figure, when the prediction coefficient control signal C is C ₁ or less, the prediction coefficient is set to 1, the output signal 3635 of the frame memory 36 is set to the prediction signal 3533 as it is, and the prediction coefficient control signal C is set to C ₁ When it exceeds, the prediction coefficient is set to a small value of 1 or less as the value increases, and the leak is strongly applied. That is, when a relatively high-order bit error occurs, the prediction coefficient is set to a small value of 1 or less to strongly leak, and the low-bit error is set to 1 and the bit error is ignored, or If the value is less than or equal to 1, the value is close to 1, and control is performed to weaken the leak.

The above-described operation is the same when a reverse transmission path error occurs.

〔The invention's effect〕

As described above, in the present invention, the prediction coefficient is set to 1 in the state where no transmission line error occurs, and when the transmission line error occurs, the error is detected for each bit,
By controlling both the transmitting side and the receiving side so that a strong leak is applied to errors in the upper bits and a weak leak is applied to errors in the lower bits, it occurs on the transmission path with almost no decrease in transmission efficiency. The effect of this error can be eliminated, and as a result, the image quality can be improved.

[Brief description of drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of the apparatus A of FIG. 1, and FIG. 3 is a block of an example of the prediction coefficient control circuit of FIG. Figure, 4th
The figure is a diagram showing an example of the operation of the prediction coefficient circuit. A, B …… Interframe coding transmission device, 19 (a, b) …… Transmission path, 1,15 …… Input terminal, 9,14 …… Output terminal, 2,16 …… Interframe coding circuit, 8,12 …… Interframe decoding circuit, 3,17
...... Multiplexing circuit, 6,11 …… Separation circuit, 7,13 …… Prediction coefficient control circuit, 20 …… Input terminal, 38 …… Output terminal, 21 …… Subtractor,
22 …… Quantization circuit, 23,35 …… Prediction coefficient circuit, 24,36 …… Frame memory, 26,33 …… Adder, 27,37 …… Parity arithmetic circuit, 28 …… Variable length coding circuit, 29 …… Multiplexing circuit, 30…
Transmission line interface circuit, 31 separation circuit, 32 variable length decoding circuit, 34 prediction coefficient control circuit, 25 delay circuit, 39 weighting circuit, 40 error bit detection circuit.

Claims (1)

[Claims] 1. A transmission side apparatus (FIG. 1B) performs interframe coding of an image signal (FIG. 1516 of FIG. 1), and a difference image signal (1617 (1) of FIG. 1) is transmitted to a first transmission line. The inter-frame coding circuit (Fig. 1 16) for sending to (Fig. 1 19b), the receiving side device (Fig. 1A) receives the differential image signal from the first transmission line. (Fig. 1 0608 (1))
As an interframe coded transmission including an interframe decoding circuit (FIG. 8) that performs interframe decoding of the received differential image signal and outputs an interframe decoded signal (0908 in FIG. 1). In the system, the interframe coding circuit (FIG. 16) calculates the parity bit by bit for N (N is an integer of 2 or more) bits of the locally decoded output signal (FIG. 2624 in FIG. 2), The inter-frame decoding circuit includes a first parity arithmetic circuit (Fig. 2 Fig. 27) for sending out the parity calculated for each as a first parity signal to the first transmission line (Fig. 1b). (FIG. 1) calculates a parity bit by bit for N bits of the inter-frame decoded signal (0908 in FIG. 1), and calculates the parity calculated bit by bit as a second parity signal (first bit). Figure 0807) second output
And a second parity signal (0807) and a first transmission line (FIG. 1). 19b)
The first parity signal (0607 in FIG. 1) received from the first parity signal is compared to detect a parity error for each bit plane, and the weight of the parity error of the n-th bit (1 ≦ n ≦ N) is w. (N) (however, w (1) ≦ ... ≦ w
(N)), and whether or not there is an error in the nth bit (1 ≦ n ≦ N) is e (n) (however, when e (n) = 1, there is an error, and when e (n) = 0, there is no error. As) A predictive coefficient control circuit (first circuit) that generates a first predictive coefficient control signal (0703 in FIG. 1) and sends this first predictive coefficient control signal to the second transmission line (FIG. 19a). (1 Figure 7)
The interframe coding circuit (FIG. 16) receives the first prediction coefficient control signal from the second transmission line (FIG. 19a) as a first reception prediction coefficient control signal. (1116 in FIG. 1), if the magnitude of the first reception prediction coefficient control signal is 0, the prediction coefficient 1 is selected, and the magnitude of the first reception prediction coefficient control signal approaches 0. The closer the prediction coefficient is to 1, the prediction coefficient closer to 1 is selected, and the larger the magnitude of the first received prediction coefficient control signal is, the closer to 0 the prediction coefficient is selected. A prediction coefficient circuit (23) for outputting a result obtained by multiplying a prediction value (2423 in FIG. 2423) generated from a decoded output signal (2624 in FIG. 2) as a prediction signal (2321 in FIG. 2), and the reception prediction coefficient. The control signal (1116 in FIG. 1) is converted into the differential image signal (1617 (1) in FIG. 1).
And the delayed prediction coefficient control signal is delayed for a predetermined time so as to match the timing with the second prediction coefficient control signal (see FIG. 16).
17 (3)), and further includes a delay circuit (FIG. 25 in FIG. 2) for sending to the first transmission path (FIG. 19b in FIG. 1), the inter-frame decoding circuit (FIG. 8), The second prediction coefficient control signal is received from the first transmission path (FIG. 19b) as a second reception prediction coefficient control signal (0608 (2) in FIG. 2), and the second reception prediction coefficient is received. If the magnitude of the control signal is 0, the prediction coefficient 1 is selected, and as the magnitude of the second received prediction coefficient control signal is closer to 0, the prediction coefficient closer to 1 is selected, and the second prediction coefficient is selected. The larger the size of the reception prediction coefficient control signal, the closer the prediction coefficient to 0 is selected, and the selected prediction coefficient is the prediction value (0908) generated from the inter-frame decoded signal (FIG. 1908). Fig. 2
3635) is further included, and a second prediction coefficient circuit (FIG. 35 in FIG. 2) for outputting the result of multiplication as a prediction signal (3533 in FIG. 2) is further included.