JPH02105690A - Inter-frame encoding transmission system - Google Patents

Abstract

PURPOSE:To efficiently suppress the influence exerted by a transmission line error without scarcely lowering the transmission efficiency by detecting a bit error at every plane, when the transmission line error is generated, executing different weighting to each bit, and controlling a prediction coefficient by using its result. CONSTITUTION:An error bit detecting circuit 40 compares a first and a second party signal 3134, 3734 by taking a delay into consideration, detects whether an error exists or not at every bit plane by one frame unit. Also, in a weighting circuit 39, different weighting is executed in accordance with whether an error exists or not in each bit plane, and as a result, a first prediction coefficient control signal 3429 is outputted. That is, when an error of a comparatively high order bit is generated, the prediction coefficient is set to a small value of <='1', and a leak is applied strongly. As for an error of a low order error, it is controlled so that a bit disregarded by setting the prediction coefficient to '1', or the leak is applied weakly by setting said coefficient to a value being <='1' and near '1'.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a coding transmission system for highly efficient coding and transmission of television signals, and particularly for cases where the effects of errors on the transmission path propagate to the next frame. This article relates to the interframe coding transmission method used.

[Conventional technology]

Conventionally, this type of interframe coding transmission method.

The basic configuration of the interframe encoder and interframe decoder is the case where the coefficient multiplied by 9 is fixed to 1 in the prediction coefficient circuit 23゜35 shown in Fig. 2, and when a transmission path error occurs. In this case, the effect propagates to the next frame and is not permanently eliminated, so intraframe coding has been used to deal with such transmission path errors.

[Problem to be solved by the invention]

The conventional interframe coding transmission method mentioned above is as follows.

As a countermeasure in the event of a transmission path error, the system sometimes uses intra-frame coding for transmission, so even if the error is not a visual problem, intra-frame coding is performed, resulting in poor transmission efficiency. There was a drawback.

The present invention aims to eliminate these drawbacks of the conventional methods and provides an entire interframe coding transmission system that can completely eliminate the effects of errors occurring on the transmission path without substantially reducing transmission efficiency.

[Means to solve the problem]

The interframe coding transmission method of the present invention calculates all the .elJ's of the N-bit decoded signal, and
A function to output this as a security signal, and a function to predict the predicted value multiplied by a prediction coefficient of 1 or less than 1 according to the first prediction coefficient control signal sent from the opposing device via the transmission line. an interframe encoding circuit including a function of converting the first prediction coefficient control signal into a signal, and a function of outputting the first prediction coefficient control signal as a second prediction coefficient control signal in order to send the first prediction coefficient control signal back to the opposite side.

A function that calculates the parity value of the N-bit decoded signal and outputs it as a second parity signal, and a preset σill value of 1=! according to the second prediction coefficient control signal. or an interframe decoding circuit that includes a function of making a prediction signal multiplied by a prediction coefficient of 1 or less.

the second reception signal and the first reception signal;
A prediction coefficient control circuit having an oil absorption function, which detects an error for each bit plane by comparing it with the A signal, weights the error, and outputs the entire first prediction coefficient control signal according to the result.

It is characterized by having all.

〔Example〕

Next, the present invention will be explained with reference to examples.

Is Fig. 1 a block diagram of an embodiment of the present invention? In this figure, device A and device B face each other via transmission paths 19a and 19b.

In the figure, consider the case where a transmission line error occurs in the transmission line 19b from the B side to the A side.

The prediction coefficient control circuit 7 uses the second noise signal 0807 calculated in the interframe decoding circuit 8 and the B
The first parity signal 0607 sent from the interframe encoding circuit 16 on the side is compared with consideration of delay, and errors are detected for each bit plane of the nine image signals. moreover,
The resulting error for each bitplane is weighted differently for the upper bits and lower bits, and the first prediction coefficient control signal 0703 calculated as a result is transmitted to the transmission path 19a (i- The first prediction coefficient control signal 1116 is transmitted to the interframe encoding circuit 16 of the opposite station B, and the first prediction coefficient control signal 1116 controls the prediction coefficient. In the converting circuit 16, the differential image signal 1617(1) and the delay are combined and outputted as a second prediction coefficient state signal 1617(3), which is transmitted in the opposite direction via the transmission path 19bi, and is output as a second prediction coefficient control signal. 060 s (2) controls the pre-ff1ll thread count (mu1) in the interframe decoding circuit 8. In this way, both the transmitting side and the receiving side can respond to errors occurring in the transmission path 19b. You can control prediction coefficients and apply leakage.

Even if a transmission path error occurs in the transmission path 19a in the opposite direction, the same operation as described above is performed.

According to this embodiment, in a state where no transmission path error occurs, the prediction coefficients are allocated to IK.

Interframe encoding is performed in which the frame memory output signal becomes a predicted signal as it is. On the other hand, when an error occurs in the transmission path, all pit errors for each bitplane are detected, each bit is weighted differently, and the resulting sound is used to multiply the frame memory output signal by a prediction coefficient of 1 or less. This is because the leakage is controlled as a predictive signal.

It becomes possible to efficiently suppress the influence of transmission path errors without substantially lowering transmission efficiency.

FIG. 2 is a block diagram showing an example of the configuration of device A in the embodiment of FIG. 1, in which device B is connected to and faces the transmission path interface circuit 30 via a transmission path. The figure is composed of a transmitter and a receiver, and in addition to a general interframe encoding/decoding loop, a prediction coefficient circuit 23, a 35° delay circuit 25.・E property calculation circuit 2
7.37 and a prediction coefficient control circuit 34.

The prediction coefficient circuit 23 is controlled by the first prediction coefficient control signal 3123, and outputs the prediction signal 23 to the output signal 2423 of the frame memory 24, which is the input signal.
The prediction coefficient circuit 35 is a similar circuit. The parity calculation circuit 27 calculates and outputs the entire parity for each bit of the locally decoded output signal 2624, and the parity calculation circuit 37 is similar.

The delay circuit 25 is a circuit for delaying the first prediction coefficient control signal 3123 and timing with the difference image signal 2228. The prediction coefficient control circuit 34 compares all the two parity signals 3734 and 3134, detects a transmission path error, calculates all the prediction coefficient control signals according to the weight of the error, and outputs the first prediction coefficient control signal 3429. It is something to do.

Below, the operation when an error occurs on the transmission path from the device B side to the device A side will be explained.

In FIG. 2, data 3031 sent from the opposite station (apparatus B) III is input to the separation circuit 31, and first prediction coefficient control signals 3123. Compressed image signal 3132
m /% +) tee signal 3134 and a second prediction coefficient control signal 3135.

First, the operation of the transmitter will be described. The separated first prediction coefficient control signal 3123 is input to the prediction coefficient circuit 23. The prediction coefficient circuit 23 outputs a frame memo signal 2423'.
e input, and to this the prediction coefficient: 1ilJ control signal 31
23 and outputs a prediction signal 2321. The detailed operation of this prediction coefficient circuit 23 is the same as that of the prediction coefficient circuit 35 described later. Further, this first prediction coefficient control signal 3123 is transmitted by the delay circuit 25 to the other station through all the multiplexing circuits 29 in synchronization with the differential image signal 2228.

The operation of the transmitter described above is for the reverse line, that is.

Even if an error occurs on the transmission path 19b, the opposite station (device B
) side performs the same operation as above.

Next, the operation on the receiving side will be explained. In the prediction coefficient control circuit 34, the first value J? is calculated for one frame period for each bit plane of nine image signals by the encoding circuit of the opposing device B. The parity signal 3134 is compared with the second A' parity signal 3734 calculated by the parity calculation circuit 37 to detect a low transmission path error occurring on the transmission path 19b.

FIG. 3 is a block diagram of an example of the prediction coefficient control circuit 34. In the same figure, the error bit detection circuit 40 detects a first no-critity signal 3134 and a second no-critity signal 3134.
734 in consideration of delay, and detect the presence or absence of errors for each bit plane in frame units. 9 more
A circuit 39 performs different weighting depending on the presence or absence of an error in each bit plane, and outputs a first prediction coefficient control signal 3429 as a result. for example.

As a simple example, in the case of an N-bit image signal, the weighting in the parity error of the 0th bit (1≦n≦N) 't W (n) (however, w(1)5w(2)≦・
・・・・・・5w(N-1)≦W(N)), and whether or not there is an error in the 0th bit (1≦n≦N) Total e(n) (However, when e(n) = l There is an error, e (n
) = O, there is no error), then the prediction coefficient control signal C, which is the output thereof, can be defined as follows.

C=Σ e(n)w(n) l This first prediction coefficient control signal 3429 is multiplexed by the multiplexing circuit 2
At step 9, the data is multiplexed with data on the transmitting side and transmitted to the prediction coefficient circuit 23 of the interframe coding circuit of the other station. moreover,
As described above, the transmitted first prediction coefficient control signal controls all the prediction coefficients of the other station, and is again transmitted to the own station as the second prediction coefficient control signal 3135. In the prediction coefficient circuit 35, the output signal 3635 of the frame memory 36 is multiplied by a prediction coefficient according to the second prediction i11+1 coefficient control signal 3135, and a prediction signal 3533 is output.

FIG. 4 shows a prediction coefficient value @ for the prediction coefficient control signal C) as an example of the prediction coefficient circuit 35.

In the example shown in the figure, when the prediction coefficient control signal C is less than or equal to 01, the prediction coefficient is set to 1, the output signal 3635t of the frame memory 36 is used as the prediction signal 3533, and the prediction coefficient control signal C exceeds C1. In this case, as the value increases, the prediction coefficient is set to a smaller value of 1 or less, thereby applying stronger leakage. That is, when a relatively high-order bit error occurs, the prediction coefficients are set to a small value of 1 or less, and leakage is strongly applied.

For lower bit errors, control is performed such that the prediction coefficient is set to 1 and the bit error is ignored, or the prediction coefficient is set to a value less than or equal to 1 and close to 1 to weakly apply leakage.

The operations described above are similar even when a transmission path error occurs in the reverse direction.

〔Effect of the invention〕

As explained above, in the present invention, all prediction coefficients are set to 1 when no transmission path error occurs, and when a transmission path error occurs, the error is detected bit by bit,
By controlling both the transmitter and the receiver 111 to apply a strong leak to errors in the upper bits and a weak leak to errors in the lower bits, transmission can be achieved with almost no reduction in transmission efficiency. This has the effect of eliminating the effects of errors that occur on the road, and improving image quality as a result.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention. Figure 2 is a block diagram showing an example of the configuration of device A in Figure 1, Figure 3 is a block diagram of an example of the prediction coefficient control circuit in Figure 2, and Figure 4 shows the operation of the prediction coefficient circuit. It is a figure showing an example. A, B... Interframe coding transmission device, 19 (a
. b)...Transmission line, 1.15...Input terminal, 9.14
... Output terminal, 2.16... Interframe encoding circuit, 8°12... Interframe decoding circuit, 3, 1.
7... Multiplexing circuit, 6.11... Separation circuit, 7.1
3... Prediction coefficient control circuit, 20... Input terminal, 38
...Output terminal. 21... Subtractor, 22... Quantization circuit, 23.35
...Prediction coefficient circuit, 24.36...Frame memory. 26.33...Adder, 27.37...Parity-
Arithmetic circuit, 28... Variable length encoding circuit, 29... Multiplexing circuit, 30... Transmission line interface circuit, 31
...Separation circuit, 32...Variable length decoding circuit, 34.
...Prediction coefficient control circuit, 25...Delay circuit, 39...
- Weighting is a circuit, 40... error bit detection circuit. Fig. 3 Coefficient control signal (C)

Claims (1)

[Claims] 1. A function of calculating the parity of an N-bit decoded signal and outputting it as a first parity signal, and a first prediction coefficient sent from an opposing device via a transmission path. A function of multiplying a predicted value by a prediction coefficient of 1 or 1 or less according to the control signal as a prediction signal, and a second prediction coefficient control signal for sending the first prediction coefficient control signal back to the opposite side. an interframe encoding circuit including a function to output the parity of the N-bit decoded signal; a function to calculate the parity of the N-bit decoded signal and output it as a second parity signal; an interframe decoding circuit including a function of multiplying a predicted value by a prediction coefficient of 1 or 1 or less as a predicted signal; and a bit plane by comparing the second parity signal and the first parity signal. a prediction coefficient control circuit having a function of detecting a parity error at each time, weighting the parity error, and outputting the first prediction coefficient control signal according to the result; Coded transmission method.