JPH0771151B2 - Time-division switch speech path test method - Google Patents

Description

The present invention relates to a time-division switch communication path test system.

[Conventional technology]

Conventionally, in this type of time-division switch communication test system, a plurality of terminals (for example, telephones) are connected to the terminal interface section of the time-division switch communication path, and these are mutually connected to pass data or voice. It was to confirm the normality of the communication path.

[Problems to be solved by the invention]

In the above-mentioned conventional time-division switch speech path test method, the speech path is tested by performing communication between a plurality of terminals, so it is very large to test all the time-slot channels of the time-division switch. There was a problem that labor and time were required. For example, the communication path test of a 512 × 512 time division switch is 512 channels on the input side and 512 channels on the output side.
All combinations of channels, ie 512 x 512 = 262.14
You have to do about 4 ways.

[Means for solving problems]

According to the present invention, a clock signal synchronized with a time slot of a time divisional switch is connected to an input side highway selection switch for connecting to each input side highway of the time divisional switch and each output side highway of the time divisional switch. A counter, an AND circuit having the carry signal of each counter as an input, a flip-flop for judging the test result having the output of the AND circuit as a data input and the synchronizing signal of the time division switch as a clock input, and this flip-flop A test result display section connected to the output of the input side highway selecting switch, and operating the input side highway selection switch to input a clock signal synchronized with the time slot of the time divisional switch to one of the input side highways, and selecting the input signal. Highway data obtained by connecting the highway data to all the outgoing highways. A time-division switch channel test method is obtained in which data is connected to the clock terminals of the respective counters, and the AND circuit takes the logical product of the carry signals of all the counters and inputs the logical product to the flip-flops. EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the time-division switch speech path testing method of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation in FIG.

In FIG. 1, the time-division switch communication path test method is as follows. An entrance-side highway selection switch 9 connected to each entrance-side highway 5 of the time-division switch communication path unit 1 and each exit-side highway 6 of the time-division switch communication path unit 1. Counter connected to 10
0, ~ 115 and carry signal CA ₀ , of each counter 100, ~ 115
~ CA ₁₅ as an input, AND circuit 11, the output of AND circuit 11 as a data input, and the frame-head synchronization signal FH of the time division switch as a clock input for the test result judgment, and the output of flip-flop 12 Is connected to the cathode side of the photodiode 13 for displaying the test results
With. The time-division switch communication path unit 1 is composed of a multiplexer 3, a time-division switch 2, and a demultiplexer 4 and has an input side of 512 and an output side of 512.
A power supply V _CC is supplied to the anode side of the through a resistor.
Further, the frame head synchronization signal FH is as shown in FIG.
This is a signal with a cycle of 125 μs. Furthermore, the clock CP1M is 512 × 51
The clock CP1M can be used as highway data of the time-division switch 2 because it is synchronized with the time-division switch 2 of 2 and its 1/2 cycle is equal to the change cycle of the data input to the multiplexer 3.

Next, the operation of this embodiment will be described with reference to FIGS.

The incoming highway selection switch 9 determines one of the incoming highways 5 (SR ₀ , to SR ₁₅ ) to which the clock CP1M should be input.
Under general control of the CPU, this selected input highway is channel-corresponding to all output highways 6 (here, 16 highways (SS ₀ , ~ SS ₁₅ )), that is, input highway 5 (SR _n ) Channels CH0, CH1, ... of output highway 6 (SS ₀ , ... SS ₁₅ ) channels CH0, CH1, respectively
Connect according to. Whether or not to invert the phase of the output 16 highways 6 on the output side is determined by the type selection switches TI7 and TII8. This is a type selection switch between the clock CP1M and the input side highway selection switch 9 so that the highway channel data input to the time division switch speech path unit 1 can be selected as type I "01010101" or type II "10101010". Because TI7 and T II 8 are placed, it is necessary to invert or not invert the outgoing highway data according to the above types I and II in order to match the phase of the test result judgment.

The 16 outgoing highway data CTRCP ₀ ,
~ CTRCP ₁₅ is outgoing highway 6 (SS ₀ , ~ SS ₁₅ )
It is input to the CP terminals of the counters 100 and 115 for each. If the time division switch speech path unit 1 is working normally, all 16 counters 100, 115 are frame head synchronization signal F.
Since it has been loaded with “0” in advance by H, carry signals CA ₀ , to CA ₁₅ are output at the same time. The carry signals CA _{0 to} CA ₁₅ are input to the AND circuit 11, and the test result normal signal is output at the same timing as the output of the carry signals CA _{0 to} CA ₁₅ . When this is held by the flip-flop 12 and the output is given to the photodiode 13, the photodiode 13 is turned on to indicate that the test result is normal. If the time-division switch communication path unit 1 is abnormal, the AND circuit 11 does not output a signal, and it is clear that the photodiode 13 does not light.

Next, change the incoming side highway selection switch and perform similar speech path tests sequentially using another incoming side highway,
If each of the 16 incoming highways 5 (SR ₀ , ~ SR ₁₅ ) is tested for the above type I and type II, it is possible to confirm the normality of the combination of all time slot channels of the time division switch 2. it can.

〔The invention's effect〕

As described above, according to the present invention, the clock signal synchronized with the time slot of the time divisional switch is connected to each input side highway of the time divisional switch and each output side highway of the time divisional switch. Counters, an AND circuit that receives the carry signal of each counter as an input, a flip-flop for determining the test result that uses the output of the AND circuit as a data input, and the synchronization signal of the time-division switch as a clock input, and this flip-flop. Equipped with a test result display connected to the output of the
The input side highway selection switch is operated to input the clock signal synchronized with the time slot of the time division switch to one of the input side highways, and the selected highway data is connected to all the output side highways to obtain it. The highway data is connected to the clock terminal of each counter, the AND circuit inputs the logical product of the carry signals of all the counters to the flip-flop, and the test judgment is performed by the flip-flop for the test judgment. Moreover, it has the effect that the normality of the speech paths of all the time slot channels of the time division switch can be tested.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a time division switch speech path test system of the present invention, and FIGS. 2 and 3 are time charts for explaining the operation in FIG. 1 ... Time-division switch Call path section, 2 ... Time-division switch, 3 ... Multiplexer, 4 ... Demultiplexer,
5 …… Ingress highway, 6 …… Exit highway, 7,8…
… Type selection switch, 9 …… Incoming highway selection switch, 11 …… AND circuit, 12 …… Flip-flop, 13
…… Photodiode, 100, 115 …… Counter.

Claims (1)

[Claims] 1. An input side highway selection switch for connecting a clock signal synchronized with a time slot of the time division switch to each input side highway of the time division switch, and a counter connected to each output side highway of the time division switch. An AND circuit that receives each counter carry signal as an input, a flip-flop for determining a test result that uses the output of this AND circuit as a data input, and the synchronization signal of the time-division switch as a clock input, and the output of this flip-flop. A test result display unit connected to the input side highway, and operating the input side highway selection switch to input a clock signal synchronized with the time slot of the time division switch to one of the input side highways, and selecting the selected one. Highway data obtained by connecting the highway data to all the outgoing highways. The connected to the clock terminal of each counter, the AND circuit division switch speech path test method when, characterized in that input to the flip-flop takes the logical product of the carry signal of the full counter the.