JPH0423634A - Line error rate monitor device - Google Patents

Abstract

PURPOSE:To measure a bit error rate very accurately by providing a bit pattern insertion/withdrawal section inserting/withdrawing a prescribed bit pattern to/from an idle channel of a line and monitoring the line error rate with bit error rate measurement based on the extracted bit pattern. CONSTITUTION:A multiplex data sent from a line interface section 3 in a time division multiplexer 2a(2b) is inputted to a bit pattern insertion/withdrawal section 7a via a path selection section 9a to insert a bit pattern generated by a bit error rate monitor section 8a to an idle channel of a high speed digital private line 1a. A line error rate monitor 6b(6a) extracts a bit pattern received and inserted by the bit pattern insertion/withdrawal section and sends the extracted bit pattern to the bit error rate monitor section 8. The bit error rate monitor section 8 measures a bit error rate at all times based on the received bit pattern to monitor a line error rate and sends the result of monitor to a control section 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line error rate monitoring device for monitoring line quality of lines such as high-speed digital private lines and public network lines in wired digital communications.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional line error rate monitoring device. In the figure, numeral 1 is a high-speed digital private line whose line error rate is monitored, and 2a and 2b are time division multiplexing devices connected oppositely by this high-speed digital private line 1.

Reference numeral 3 denotes a line interface section located within this time division multiplexing device 2a (2b) and providing an interface with the high-speed digital dedicated line 1, and 4 also located within the time division multiplexing device 2a (2b). , a terminal interface unit that interfaces with a connected terminal device. 5a
, 5b are modem testers which are connected to the terminal interface section 4 of each time division multiplexing device 2a or 2b and serve as a line error rate monitoring device for monitoring the line error rate of the high-speed digital private line 1.

Next, the operation will be explained. High-speed digital dedicated 111
When it becomes necessary to monitor the line error rate, the terminal devices connected to the respective terminal interface sections 4 in the opposing time division multiplexers 2a, 2b are replaced with modem testers 5a, 5b. Next, one of the modem testers 5a (5b) detects the Sheradou noise pattern (
p 5eudou-Noise pattern below,
(referred to as a P/N pattern). This P/N pattern is multiplexed by the time division multiplexer 2a (2b),
The signal is sent from the line interface section 3 to the high-speed digital private line 1.

In the opposing time division multiplexing device 2b (2a), the line interface section 3 receives it, and the separated P/N pattern is sent from the terminal interface section 4 to the modem tester 5b (
5a). The modem tester 5b (5a) monitors the line error rate of the high-speed digital private line 1 by measuring the bit error rate of the received P/N pattern.

[Problem to be solved by the invention]

Since the conventional line error rate monitoring device is configured as described above, when it becomes necessary to monitor the line error rate, each of the opposing time division multiplexers 'la, 2b
The terminal device connected to the terminal interface unit 4 is connected to a modem tester 5a, which is a line error rate monitoring device.
5b, it is not only difficult to constantly monitor the line error rate, but also because the P/N pattern can only be inserted in a part of the line (high-speed digital line 1). There were also issues such as the accuracy of bit error rate measurement data being poor.

This invention was made to solve the above-mentioned problems, and aims to provide a line error rate monitoring device that can constantly monitor line error rates and improve the accuracy of measurement data. .

[Means to solve the problem]

The line error rate monitoring device according to the present invention includes a bit pattern insertion/extraction unit for inserting and extracting a predetermined bit pattern into and out of a vacant channel of a line, corresponding to each of a plurality of lines; a bit error rate monitoring section that measures the bit error rate based on the bit pattern extracted from the bit pattern; and a route selection section that selects and connects one of the bit pattern insertion/extraction sections to the line interface section of the time division multiplexer. It has been established that

[For production]

The bit pattern insertion/extraction unit in this invention inserts a predetermined bit pattern generated by the bit error rate monitoring unit into an empty channel of the line to which it is connected, and extracts the bit pattern inserted by the opposing device to generate a bit error rate. The bit error rate monitoring unit monitors the line error rate by measuring the bit error rate based on the received bit pattern, and if deterioration of the line error rate is detected, the bit error rate monitoring unit By changing the connection of the line interface section of the time division multiplexer to another line, the line error rate can be constantly monitored.Furthermore, if a line with a degraded line error rate is connected, bit errors will be added to all channels. A line error rate monitoring device is provided which is capable of inserting a bit pattern from a rate monitoring unit and also improves the accuracy of measurement data of a bit error rate.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 2a and 2b are time division multiplexing devices, and 3 is a line interface section, which are the same or equivalent parts as those in the conventional system denoted by the same reference numerals in FIG. 3, and detailed explanations thereof will be omitted.

1a and 1b are high-speed digital dedicated lines that interconnect the time division multiplexers 2a and 2b, with one used as a working system and the other as a protection system. It is equivalent to a digital leased line. Also,
5a and 5b are the line interface section 3 of each time division multiplexer 2a (2b) and the high-speed digital dedicated lines 1a and 1.
This is a line error rate monitoring device placed between the

7a and 7b are the line error rate monitoring devices 5a.

6b, a predetermined bit pattern is inserted into an empty channel of the high-speed digital dedicated line 1a (1b) prepared in accordance with the ratio of each of the high-speed digital dedicated lines 1a, 1b, and the corresponding high-speed digital dedicated line 1a (1b) is inserted. This is a bit pattern insertion/extraction unit that extracts the bit pattern (turn) that has been inserted.

8a and 8b generate a bit pattern to be inserted into the vacant channel of the high-speed digital dedicated line 1a (1b) by the bit pattern insertion/extraction unit 7a (7b), and also generate a bit pattern extracted by the bit pattern insertion/extraction unit 7a (7b). This is a bit error rate monitoring unit that measures the bit error rate based on the bit error rate. Reference numerals 9a and 9b represent strategy selection units that select one of the plurality of bit pattern insertion/extraction units 7a (7b) and connect it to the line interface unit 3 of the time division multiplexer 2a (2b). 10 is a line error rate monitoring device 6a (6
b) A control section that performs overall control.

Next, the operation will be explained. Here, the plurality of high-speed digital private lines ja, 1b are connected to the time division multiplexing device 2a, for example, the high-speed digital private line 1a is used as a working system.
It is assumed that the high-speed digital dedicated line 1b is used for transmitting multiplexed data exchanged between the high-speed digital private line 1b and the other high-speed digital private line 1b is on standby as a standby system.

In that case, in each line error rate monitoring device 6a (6b), the route selection unit 9a is turned on under the control of the control unit 10.
The strategy selection unit 9b is turned off, and the bit pattern insertion/extraction unit 7a for the active high-speed digital dedicated line 1a is connected to the line interface unit 3 of the time division multiplexer 2a (2b). Therefore, the multiplexed data transmitted from the line interface unit 3 in the time division multiplexer 2a (2b) is input to the bit pattern insertion/extraction unit 7a via the route selection unit 9a. The bit pattern insertion/extraction section 7a inserts the bit pattern generated by the bit error rate monitoring section 8a into an empty channel of the high-speed digital private line 1a under the control of the control section 10.

Line error rate monitoring device 6b (6
In a), the bit pattern insertion/extraction section 7a receives the bit pattern, extracts the inserted bit pattern, and sends the extracted bit pattern to the bit error rate monitoring section 8a. The bit error rate monitoring section 8a constantly measures the bit error rate based on the received bit pattern, monitors the line error rate, and sends the monitoring results to the control section 10.

Further, the remaining multiplexed data from which the bit pattern has been extracted is sent to and received by the line interface section 3 of the time division multiplexer 2b (2a) via the route selection section 9a which is turned on.

Here, when it is detected that the bit error rate of the active high-speed digital dedicated line 1a has become high, the control unit 1
0 controls the route selection units 9a and 9b, and selects the route selection unit 9a.
is turned on, and the route selection section 9b is turned off. From this K, the high-speed digital private line 1b becomes the working system and transmits multiplexed data exchanged between the time division multiplexers 2a and 2b, and the high-speed digital private line 1a becomes the backup system.

In this case, as in the case described above, the bit pattern insertion/extraction unit 7 is inserted into the vacant channel of the high-speed digital private line 1b.
The bit pattern from the bit error rate monitoring section 8b is inserted by b, and the line error rate is constantly monitored. Furthermore, in the high-speed digital private line 1a that has been switched to the backup system, the bit pattern generated by the bit error rate monitoring unit 8a is inserted into all channels under the control of the control unit 10, thereby making the bit error rate more accurate. is measured.

In the above embodiment, a case has been described in which all the lines are high-speed digital dedicated lines, but some of them may be public network lines. FIG. 2 is a block diagram showing such an embodiment, and the same parts in the figure are given the same reference numerals as in FIG. 1 or 3 to avoid redundant explanation.

Further, 11 is a public network line as the line, and 12
is a public network automatic calling unit that automatically calls this public network line 11.

When the bit error rate of the high-speed digital leased line 10 currently being used as an active system becomes high, the control unit 10 activates the public network automatic calling unit 12 to connect to the public network line 11 and wait for a certain period of time to detect the bit error. Perform rate measurements. As a result, if the line quality of the public network line 11 is normal, the route selection units 9a and 9b are controlled, and the time division multiplexing device 2a (2
The line interface section 3 of b) is connected to the bit pattern insertion/extraction section 7b. Thereafter, as in the case of the embodiment shown in FIG. 1, multiplexed data is transmitted while monitoring the line error rate of this public network line 110.

On the other hand, as in the case of the embodiment shown in FIG. 1, if the bit error rate of the high-speed digital dedicated line 1 becomes lower, in which pit patterns are inserted into all channels to measure the bit error rate accurately, Multiplexed data is transmitted by switching the high-speed digital dedicated line 1 to the working system and the public network line 11 to the protection system. By using the line in this way, there is a problem with the line.

Advantages of being able to reduce costs [Effects of the invention] As described above, according to this invention, it is possible to support multiple lines,
A pit pattern insertion/extraction unit that inserts and extracts a predetermined bit pattern into an empty channel of the line is prepared, and the line error rate is monitored by measuring the bit error rate based on the bit pattern extracted by this bit pattern insertion/extraction unit. Since the system is configured to control the strategy selection section and change the connection of the line interface section of the time division multiplexer to the backup line when the rate deteriorates, it not only becomes possible to constantly monitor the line error rate. , it becomes possible to insert a predetermined bit pattern into all channels of a line where the line error rate has deteriorated, and it is possible to obtain a line error rate monitoring device that can measure the bit error rate extremely accurately. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a line error rate monitoring device according to an embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the invention, and FIG. 3 is a block diagram showing a conventional line error rate monitoring device. It is a block diagram. 1.1a and 1b are lines (high-speed digital dedicated line), 2a
, 2b is a time division multiplexing device, 3 is a line interface section, 5a and 5b are line error rate monitoring devices, 7a and 7b
8a is a bit pattern insertion/extraction part. 8b is a bit error rate monitoring section, 9a and 9b are route selection sections, and 11 is a line (public network line). In addition, the same symbols in the figures indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation (2 others)

Claims (1)

[Claims] A predetermined bit pattern is inserted into an empty channel of the line, and a predetermined bit pattern is inserted into an empty channel of the line, and a predetermined bit pattern is inserted into an empty channel of the line. a bit pattern insertion/extraction unit for extracting a bit pattern; generating the bit pattern to be inserted in the bit pattern insertion/extraction unit; and measuring a bit error rate based on the bit pattern extracted by the bit pattern insertion/extraction unit. A line error rate monitoring device comprising: a bit error rate monitoring unit; and a route selection unit that selects one of the bit pattern insertion/extraction units and connects it to a line interface unit of the time division multiplexing device.