JPH0770675B2 - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0770675B2 JPH0770675B2 JP60218340A JP21834085A JPH0770675B2 JP H0770675 B2 JPH0770675 B2 JP H0770675B2 JP 60218340 A JP60218340 A JP 60218340A JP 21834085 A JP21834085 A JP 21834085A JP H0770675 B2 JPH0770675 B2 JP H0770675B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring pattern
- chips
- package
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06551—Conductive connections on the side of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/1627—Disposition stacked type assemblies, e.g. stacked multi-cavities
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置およびその製造方法に係り、特
に、半導体チツプのパッケージへの実装方法に関する。Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a method for mounting a semiconductor chip on a package.
近年、半導体機器の小形化と共に、半導体メモリの高集
積化への要求が高まってきており、その集積度は３年間
に４倍というペースで向上する傾向にある。In recent years, along with miniaturization of semiconductor devices, there has been an increasing demand for higher integration of semiconductor memories, and the degree of integration tends to improve at a pace of four times in three years.
このような要求に答えるべく多大な努力がはらわれてい
るが、最も重要なのは、電子機器内に設けられるICボー
ド上に組み込む際の実装密度（すなわち半導体チップの
ICボード上での単位面積当りの実装数）を高めることで
あり、そうすることによって更に機器全体の高集積化の
実現が可能となる。Although great efforts have been made to meet such demands, the most important thing is the packaging density (that is, semiconductor chip
It is to increase the number of mountings per unit area on the IC board), and by doing so, it is possible to realize higher integration of the entire device.
その１つの手段としてICパッケージ内でのチップの実装
における高集積化が考えられる。As one of the means, high integration in mounting the chip in the IC package can be considered.
このため、ICパッケージ内の半導体チップを高密度に実
装すべくいろいろな方法が考えられている。通常、ICパ
ッケージ内に半導体チップを実装する方法としては、第
５図に示すように、パッケージ11内に設けられたくぼみ
12に半導体チップ13を１個水平な状態で載置し、平面的
に実装する方法が広く用いられている。Therefore, various methods have been considered for mounting the semiconductor chips in the IC package at high density. Usually, as a method of mounting a semiconductor chip in an IC package, as shown in FIG.
A method of mounting one semiconductor chip 13 on 12 in a horizontal state and mounting it in a plane is widely used.
しかし、この方法では、１パッケージ,1チップであり、
実装面積としてはかなり無駄をしていることになる。However, with this method, one package, one chip,
This means that the mounting area is wasted.
そこで改善策の１つとして、第６図に示すように、パッ
ケージ21の両面に２個のくぼみ22,22′を設け、背中合
わせに２個の半導体チップ23,23′を固着し、ワイヤＷ
によってボンディングする実装方法も提案されてはいる
が、この方法でも実装密度は２倍になるだけで、充分な
改善とはいい難いという問題があった。Therefore, as one of the improvement measures, as shown in FIG. 6, two recesses 22 and 22 'are provided on both sides of the package 21, two semiconductor chips 23 and 23' are fixed back to back, and the wire W
Although a mounting method of bonding has been proposed by this method, there is a problem that this method only doubles the mounting density and cannot be said to be a sufficient improvement.
本発明は、前記実情に鑑みてなされたもので、信頼性を
維持しつつ実装密度を格段に向上させることを目的とす
る。The present invention has been made in view of the above circumstances, and an object thereof is to significantly improve the packaging density while maintaining reliability.
そこで本発明では、パッケージ内に形成された配線パタ
ーンに対して電気的に接続されるように半導体チップを
前記配線パターン上に立て、前記配線パターン上から、
半導体チップ主表面上のパッド表面までバンプで覆うこ
とによって、固着せしめるようにしている。Therefore, in the present invention, the semiconductor chip is erected on the wiring pattern so as to be electrically connected to the wiring pattern formed in the package, and from the wiring pattern,
The pad surface on the main surface of the semiconductor chip is covered with bumps so as to be fixed.
すなわち本願発明は、パッケージ内にチップを立てて搭
載するものであり、また接続に際しても、電極はチップ
の主表面に形成しておき、配線パターン上に形成された
バンプを用いてバンプ層がこの電極を覆うように溶融さ
せることにより電気的および機械的接続を達成するもの
である。That is, according to the present invention, a chip is mounted upright in a package, and at the time of connection, the electrodes are formed on the main surface of the chip, and the bump layer is formed by using bumps formed on the wiring pattern. The electrical and mechanical connection is achieved by melting the electrodes to cover them.
また望ましくは、パッケージ内には複数のチップが互い
に平行となるように配列されている。Further, preferably, a plurality of chips are arranged in the package so as to be parallel to each other.
さらに望ましくは、パッケージは前記配線パターンに接
続され、前記パッケージから外方に導出せしめられたリ
ードを具備している。More preferably, the package is provided with a lead connected to the wiring pattern and led out from the package.
さらに望ましくは、前記チップを、複数のメモリチップ
で構成すれば、実装密度が高いため、小型でメモリ容量
の大きなメモリを提供することができる。More preferably, if the chip is composed of a plurality of memory chips, the packaging density is high, so that a small-sized memory having a large memory capacity can be provided.
さらに望ましくは、前記チップを複数のメモリチップで
構成し、各メモリチップ毎にリード選択用のリードを割
り当てるようにすれば、回路構成も簡略化され、集積度
が大幅に増大する。More preferably, if the chip is composed of a plurality of memory chips and leads for lead selection are assigned to each memory chip, the circuit configuration is simplified and the degree of integration is greatly increased.
さらに望ましくは、前記チップを、内部に判断回路を具
備した複数のメモリチップとし、各チップ毎に前記リー
ドが割り当てられ、さらに各メモリチップが共通して接
続されたリードを具備し、前記各メモリチップに共通し
て接続されたリードからチップ選択信号が入力されると
前記判断回路で判断して特定のメモリチップが選択的に
駆動されるように構成すれば、集積度が向上してメモリ
容量が大幅に増大する上、配線基板上の配線パターンも
簡略化することができる。More preferably, the chip is a plurality of memory chips each having a determination circuit therein, the leads are assigned to each chip, and the memory chips include leads to which the memory chips are commonly connected. If the determination circuit determines that the chip selection signal is input from the leads commonly connected to the chip and the specific memory chip is selectively driven, the integration degree is improved and the memory capacity is increased. And the wiring pattern on the wiring board can be simplified.
さらに本願発明の方法では、チップ搭載領域にバンプが
形成された配線パターンとこれに電気的に接続されるリ
ードとを備えたリード構成体を用意する工程と、主表面
上の一端部にパッドを配列したチップを用意する工程
と、前記リード構成体の前記配線パターン上に、立てた
状態でチップを載置し、加熱することによりバンプによ
って前記チップを前記配線パターン上に融着せしめる工
程と、前記リードを除く全体をパッケージ内に封止する
工程とを含むことを特徴とする。Further, in the method of the present invention, a step of preparing a lead structure provided with a wiring pattern having bumps formed in a chip mounting area and leads electrically connected to the wiring pattern, and a pad at one end on the main surface are provided. A step of preparing the arranged chips, a step of mounting the chips in an upright state on the wiring pattern of the lead structure, and heating the chips to fuse the chips onto the wiring pattern by heating, And a step of encapsulating the whole body excluding the leads in a package.
すなわち、本願発明は、配線パターンのチップ搭載領域
にバンプを形成しておき、このバンプ上に主表面上の一
端部にパッドを配列したチップをたてた状態で搭載し
て、加熱することによりバンプを前記チップの主表面の
パッド上まで覆うようにし、前記チップの電気的接続と
機械的接続とを一度に達成するようにしたこのである。That is, according to the invention of the present application, bumps are formed in the chip mounting area of the wiring pattern, a chip having pads arranged at one end on the main surface is mounted on the bumps, and the chip is mounted and heated. In this structure, the bumps are covered up to the pads on the main surface of the chip so that electrical connection and mechanical connection of the chip can be achieved at one time.
すなわち、この方法では半導体チップは立てた状態であ
るため小面積で多数個実装でき、大幅に実装密度を向上
せしめ得る上、パッケージ内に形成された配線パターン
に対して電気的に接続をしたい部分にハンダバンプを形
成し、固着と電気的接続の両方を同時に達成するように
すればよいため、接続が極めて容易となる。In other words, in this method, since the semiconductor chips are in an upright state, a large number of semiconductor chips can be mounted in a small area, the mounting density can be greatly improved, and the portion to be electrically connected to the wiring pattern formed in the package is desired. Since the solder bumps may be formed on both of them to achieve both fixing and electrical connection at the same time, the connection becomes extremely easy.
例えば、従来のICパッケージ面積内に10個の半導体チッ
プを立てて実装すれば10倍の実装密度を実現することが
可能である。For example, if 10 semiconductor chips are erected and mounted in the conventional IC package area, it is possible to realize a 10 times mounting density.
本発明によれば、実装密度が大幅に向上する上、ハンダ
バンプにより、チップの固着おびボンディングによるチ
ップとパッケージ内の配線パターンとの接続が同時に達
成でき、作業性が良い。According to the present invention, the mounting density is significantly improved, and the solder bumps can simultaneously achieve the connection between the chip and the wiring pattern in the package by the fixing and bonding of the chip, resulting in good workability.
また、信頼性についても、従来のレベルを維持すること
ができる。Also, the reliability can be maintained at the conventional level.
以下、本発明の実施例について図面を参照しつつ詳細に
説明する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は、５個の半導体チップを立てて実装した半導体
装置の封止前の状態を示す図である。FIG. 1 is a diagram showing a state before sealing a semiconductor device in which five semiconductor chips are vertically mounted.
この半導体装置は、プラスチック製のパッケージ１と６
本の２列のリードピン３と、このパッケージの主面に形
成された凹部４に符合して該リードピン３と一体的に形
成された配線パターン５と、該配線パターン５上の所定
の位置にハンダバンプ６によって立てた状態で電気的に
接続されると共に、安定良く固着せしめられた５枚のチ
ップ２とから構成されており、通常は、キャップ（図示
せず）によって封止されるようになっている。This semiconductor device has plastic packages 1 and 6
Two rows of lead pins 3 of the book, a wiring pattern 5 formed integrally with the lead pins 3 corresponding to the recesses 4 formed on the main surface of the package, and solder bumps at predetermined positions on the wiring pattern 5. It is composed of five chips 2 which are electrically connected in an upright state by 6 and are firmly fixed to each other. Normally, they are sealed by a cap (not shown). There is.
なお、各半導体チップ２は、第２図に示す如くボンディ
ングパッド2Pが１方の辺に配列されるようにパターン設
計がなされている。Each semiconductor chip 2 is designed so that the bonding pads 2P are arranged on one side as shown in FIG.
また、リードピン３に接続されている配線パターンは、
第３図に示す如く、リードピンと共にリードフレームと
して打ち抜き加工により形成したものをパッケージ１に
挟み込み、パッケージ１の凹部４に符合するように形成
されており、所定の位置でチップのボンディングパッド
2Pとハンダバンプ６を介して接続される。The wiring pattern connected to the lead pin 3 is
As shown in FIG. 3, a lead frame, which is formed by punching together with lead pins, is sandwiched in the package 1 and formed so as to match the recess 4 of the package 1, and the chip bonding pad is formed at a predetermined position.
2P and solder bump 6 are connected.
かかる配線パターンにより半導体チップ間、半導体チッ
プとリードピン間が所望に接続され、集積度が向上した
と同等の効果が得られる。チップはいかなる種類のチッ
プの取り合せも可能であるが、チップの選択が必要な場
合、例えばdRAMのチップを並べてチップの数倍の容量を
実現するような場合は、各チップ毎にアドレス用のリー
ドピンを割り当てればよい。また、チップ毎に判断回路
を設け、共通のリードピンからチップ選択信号を入力す
ることもできる。With such a wiring pattern, the semiconductor chips, and the semiconductor chip and the lead pins are connected as desired, and the same effect as that in which the degree of integration is improved can be obtained. The chips can be any kind of chips, but when it is necessary to select chips, for example, when arranging dRAM chips to achieve a capacity several times that of the chips, read pins for addressing each chip. Should be assigned. It is also possible to provide a judgment circuit for each chip and input a chip selection signal from a common lead pin.
接続部は、第４図に拡大図を示す如く、ハンダバンプ６
によって配線パターン５上にチップ２が立てられた状態
となっている。As shown in the enlarged view of FIG.
Thus, the chip 2 is set up on the wiring pattern 5.
実装に際しては、リードピンと配線パターンとを一体的
に打ち抜き加工によって形成したリードフレームを作製
し、まず、パッケージ内の凹部に配線パターンが符合す
るように、パッケージにリードフレームを固着する。At the time of mounting, a lead frame in which a lead pin and a wiring pattern are integrally formed by punching is manufactured, and first, the lead frame is fixed to the package so that the wiring pattern matches the recess in the package.
この後、該配線パターンの所定の位置にハンダバンプを
形成し、順次５枚のチップを載せ、加熱によって該配線
パターンも融着する。Thereafter, solder bumps are formed at predetermined positions on the wiring pattern, five chips are sequentially mounted, and the wiring pattern is also fused by heating.
そして最後に、キャップをかぶせ、封止する。And finally, a cap is put on and sealed.
このようにして形成された半導体装置は、チップを立て
た状態で実装できるため、大幅に実装密度が向上する。The semiconductor device thus formed can be mounted in a state where the chips are erected, so that the mounting density is significantly improved.
また、ワイヤボンディングが不要となり、すべてハンダ
バンプによりボンディングであるため、信頼性が低下す
ることもない。In addition, since wire bonding is not necessary and all the bonding is performed by solder bumps, reliability is not deteriorated.
なお、ハンダバンプによって接続を行なう位置の配線パ
ターンは少し太くしておいた方がよい。The wiring pattern at the position where the connection is made by the solder bump should be made slightly thicker.
また、チップは一つずつまたは全部一度に機械アームに
よって立てた形でセットしても良いし、スペーサ等によ
って所定の間隔を維持しつつ全部一体的にセットし、後
でスペーサを除去するようにすることも可能である。フ
ィルムキャリア方式を用いて実装し、これをパッケージ
内に設置するようにしてもよい。In addition, the chips may be set one by one or all at once in the form of standing upright by a mechanical arm, or all the chips may be set integrally while maintaining a predetermined interval with a spacer and the spacers may be removed later. It is also possible to do so. You may make it mount using a film carrier system and install this in a package.
更に、配線パターンは、必ずしもリードフレームと一体
的に形成する必要はなく、配線基板のようなものを用い
てもよい。Furthermore, the wiring pattern does not necessarily have to be formed integrally with the lead frame, and a wiring board or the like may be used.
第１図は、本発明実施例（封止前）の半導体装置を示す
図、第２図は、同半導体装置で用いられる半導体チップ
のボンディングパッドの状態を示す図、第３図は、同装
置で用いられる配線パターンを示す図、第４図は、接続
部の状態を示す図、第５図および第６図は、従来例の半
導体装置を示す図である。 １……パッケージ、２……チップ、2P……ボンディング
パッド、３……リードピン、４……凹部、５……配線パ
ターン、６……ハンダバンプ、11……パッケージ、12…
…凹部、13……半導体チップ、21……パッケージ、22,2
2′……くぼみ、23,23′……半導体チップ。FIG. 1 is a diagram showing a semiconductor device of an embodiment of the present invention (before sealing), FIG. 2 is a diagram showing a state of a bonding pad of a semiconductor chip used in the semiconductor device, and FIG. 3 is the device. FIG. 4 is a diagram showing a wiring pattern used in FIG. 4, FIG. 4 is a diagram showing a state of a connection portion, and FIGS. 5 and 6 are diagrams showing a conventional semiconductor device. 1 ... Package, 2 ... Chip, 2P ... Bonding pad, 3 ... Lead pin, 4 ... Recess, 5 ... Wiring pattern, 6 ... Solder bump, 11 ... Package, 12 ...
… Concave, 13 …… Semiconductor chip, 21 …… Package, 22,2
2 '... Dimples, 23,23' ... Semiconductor chips.
Claims (7)
配線パターンと、 前記配線パターン上のチップ搭載領域に形成されたバン
プと、 チップの主表面上の端部にパッドを有するチップとを具
備し、 前記チップは前記パッドを前記配線パターン側に位置せ
しめるように前記配線パターン上に立てられ、かつ、 前記バンプが前記チップ搭載領域上から前記パッド表面
まで覆うことによって前記パッケージ内で前記配線パタ
ーンとの電気的接続及び機械的接続がされるようにした
ことを特徴とする半導体装置。1. A package having external electrodes, a wiring pattern arranged in the package and connected to the external electrodes, bumps formed in a chip mounting region on the wiring pattern, and on a main surface of the chip. A chip having a pad at an end of the chip, the chip being erected on the wiring pattern so as to position the pad on the wiring pattern side, and the bump from the chip mounting region to the pad surface. The semiconductor device is characterized in that it is electrically and mechanically connected to the wiring pattern in the package by covering the wiring pattern.
互いに平行となるように配列されていることを特徴とす
る特許請求の範囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, wherein a plurality of the chips are arranged in the package so as to be parallel to each other.
に導出せしめられたリードであることを特徴とする特許
請求の範囲第１項記載の半導体装置。3. The semiconductor device according to claim 1, wherein the external electrode is a lead led out from the package.
成されていることを特徴とする特許請求の範囲第１項記
載の半導体装置。4. The semiconductor device according to claim 1, wherein the chip is composed of a plurality of memory chips.
ら構成され、各メモリチップ毎にリード選択用のリード
が割り当てられていることを特徴とする特許請求の範囲
第３項記載の半導体装置。5. The semiconductor device according to claim 3, wherein the chip is composed of a plurality of memory cell chips, and a lead for lead selection is assigned to each memory chip.
数のメモリチップであり、各チップ毎に前記リードが割
り当てられ、さらに各メモリチップが共通して接続され
たリードを具備し、前記各メモリチップに共通して接続
されたリードからチップ選択信号が入力されると前記判
断回路で判断して特定のメモリチップが選択的に駆動さ
れるように構成されていることを特徴とする特許請求の
範囲第３項記載の半導体装置。6. The chip is a plurality of memory chips each having a determination circuit therein, the leads are assigned to each chip, and each memory chip further includes a lead commonly connected to each of the chips. A specific memory chip is configured to be selectively driven by the determination circuit determining that a chip selection signal is input from a lead commonly connected to the memory chips. The semiconductor device according to the third aspect.
パターンとこれに電気的に接続されるリードとを備えた
リード構成体を用意する工程と、 チップの主表面上の一端部にパッドを配列したチップを
用意する工程と、 前記パッドを前記配線パターン側に位置せしめるように
前記チップを前記リード構成体の前記配線パターン上に
立てた状態で載置し、加熱することによりバンプによっ
て前記チップを前記配線パターン上に融着せしめる工程
と、 前記リードを除く全体をパッケージ内に封止する工程と
を含むことを特徴とする半導体装置の製造方法。7. A step of preparing a lead structure provided with a wiring pattern having bumps formed in a chip mounting area and leads electrically connected to the wiring pattern, and a pad being provided at one end on a main surface of the chip. A step of preparing the arranged chips, and placing the chips in an upright state on the wiring pattern of the lead structure so that the pads are positioned on the wiring pattern side, and heating the chips to bump the chips. A method of manufacturing a semiconductor device, comprising: a step of fusion-bonding the same to the wiring pattern; and a step of sealing the entire part excluding the leads in a package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60218340A JPH0770675B2 (en) | 1985-09-30 | 1985-09-30 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60218340A JPH0770675B2 (en) | 1985-09-30 | 1985-09-30 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6276753A JPS6276753A (en) | 1987-04-08 |
| JPH0770675B2 true JPH0770675B2 (en) | 1995-07-31 |
Family
ID=16718331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60218340A Expired - Fee Related JPH0770675B2 (en) | 1985-09-30 | 1985-09-30 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0770675B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01283939A (en) * | 1988-05-11 | 1989-11-15 | Hitachi Ltd | Semiconductor chip and substrate and electronic apparatus constituted with these parts |
| FR2688628A1 (en) * | 1992-03-13 | 1993-09-17 | Commissariat Energie Atomique | Three-dimensional assembly of electronic components using microwires and blobs of solder, and method of producing this assembly |
| FR2709870B1 (en) * | 1993-09-06 | 1995-10-13 | Commissariat Energie Atomique | Method of three-dimensional assembly of electronic components by microfilm loops and soldering elements. |
| US5567654A (en) * | 1994-09-28 | 1996-10-22 | International Business Machines Corporation | Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58118132A (en) * | 1981-12-30 | 1983-07-14 | Matsushita Electric Ind Co Ltd | Electrode connection of combined thick film element |
-
1985
- 1985-09-30 JP JP60218340A patent/JPH0770675B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6276753A (en) | 1987-04-08 |
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