JPH0770575B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of aligning a semiconductor device manufactured by using a reduction projection type exposure apparatus.

2. Description of the Related Art In recent years, as semiconductor devices have been highly integrated, the alignment accuracy of semiconductor devices has been required to be higher.

The alignment of the conventional semiconductor device will be described below.

FIG. 5 shows the arrangement of the mask alignment position displacement amount reading marks in the alignment of the conventional semiconductor device. In FIG. 5, reference numeral 1 is a one-shot exposure area in reduction projection exposure. Reference numeral 2 is a chip area, and 3 is a mask alignment position deviation amount reading mark.

FIG. 6 shows a conventional procedure for aligning a semiconductor device. After the start, the first mask alignment is performed, the amount of misalignment is read by the mask alignment misalignment amount reading mark in the chip, the amount of misalignment is corrected, and the next second mask is aligned. Then, a series of mask alignment is completed.

Problems to be Solved by the Invention However, in the above-mentioned conventional method, it is possible to accurately correct the positional deviation of the offset factor that is simply shifted in parallel, but when the positional deviation of the reticle rotation factor occurs, As shown in FIG. 7, even if the position of the mask alignment position displacement amount reading mark can be accurately aligned, a large amount of displacement occurs in the one-shot exposure area, and the displacement amount cannot be read. It had drawbacks.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to accurately read and correct the positional deviation amount due to the reticle rotation factor during mask alignment to improve the alignment accuracy of the semiconductor device.

Means for Solving the Problems In order to achieve this object, a semiconductor device of the present invention has a pair of mask alignment position deviation amount read marks approximately diagonally to a rectangle of a one-shot exposure region of reduction projection exposure. It is a thing.

Effect According to the present invention, it is possible to accurately read the positional deviation amount due to the reticle rotation factor by the mask alignment positional deviation amount read marks at two diagonal positions on the rectangular plane, and the positional deviation amount is fed back to the subsequent mask alignment. By doing so, it is possible to correct the positional deviation due to the reticle rotation factor and improve the alignment accuracy of the semiconductor device.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, showing an arrangement of mask alignment position deviation amount read marks. That is, in FIG. 1, 1 is a one-shot exposure area. Reference numeral 2 is a unit chip area, and 3 is a mask alignment position shift amount read mark. FIG. 2 specifically shows a detailed pattern of the mask alignment position shift amount read mark in the semiconductor device according to the first embodiment of the present invention. A detailed pattern in the same mark 3 indicated by a broken line frame, 5 is a main scale, 6 is a subscale, and 7 is a vernier pattern in the x-axis direction. 8 is a vernier pattern in the y-axis direction. FIG. 2 shows a part of the chip.

The alignment procedure of the semiconductor device configured as described above will be described below. FIG. 3 is a procedure diagram for alignment of the semiconductor device of the present invention. The misalignment is read from each of the two mask alignment misalignment amount reading marks 3 arranged at diagonally opposite positions of the one-shot exposure area 2, and it is determined whether or not there is any misalignment due to the reticle rotation factor. If there is not, the positional shift due to the offset factor is corrected and mask matching is executed. If there is a positional deviation due to the reticle rotation factor, the reticle is aligned again, the positional deviation due to the reticle rotation factor is corrected, and mask alignment is executed. Then, the misregistration amount is read again, it is confirmed that there is no misalignment due to the reticle rotation factor, the misalignment due to the offset factor is corrected, and mask alignment is executed.

As described above, according to the present embodiment, by providing the mask alignment misalignment reading marks at the diagonally diagonal positions of the one-shot exposure area, it becomes possible to correct the misalignment due to the reticle rotation factor, and improve the alignment accuracy. Can be improved.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a plan view of the semiconductor device according to the second embodiment of the present invention, showing the arrangement of the mask alignment position deviation amount read marks. In FIG. 4, 1 is a one-shot exposure area, 2
Indicates a unit chip area, and 3 indicates a mask alignment position shift amount reading mark. In this way, the second embodiment has a pair of mask alignment position deviation amount read marks at the diagonal positions of each rectangular chip. By arranging the mask alignment position deviation amount reading marks on the diagonal of the chip, the marks are inevitably arranged in pairs on the diagonal of the rectangular surface of the one-shot exposure area. The operation and effect are similar to those of the first embodiment.

EFFECTS OF THE INVENTION As described above, according to the present invention, the position of the reticle rotation factor is provided by providing the mask alignment position deviation amount read mark at the position of the rectangular diagonal surface of the one-shot exposure area of the reduction projection type exposure apparatus. The deviation can be corrected, and the alignment accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a plan pattern diagram specifically showing details of a mask alignment position shift amount read mark, and FIG. 3 is a procedure of alignment. FIG. 4 is a plan view of a semiconductor device according to a second embodiment of the present invention, FIG. 5 is a plan view of a conventional semiconductor device, FIG. 6 is a procedure diagram for alignment of a conventional semiconductor device, and FIG. FIG. 4 is an explanatory view of the principle of positional displacement. 1 ... 1 shot exposure area, 2 ... 1 chip area, 3 ...
... Mask alignment position shift amount reading mark, 5 ... main scale, 6 ... subscale, 7 ... x-axis direction vernier pattern, 8
... y-axis direction vernier pattern.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/68 F

Claims (1)

[Claims] 1. A pair of mask alignment positions are located on a semiconductor chip surface on which a mask is aligned by using a reduction projection type exposure system, at approximately diagonal positions of a rectangle of a one-shot exposure area in the exposure system. A semiconductor device having a quantity reading mark.