JPH0770233B2 - Writing and erasing method of nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a writing and erasing method for a nonvolatile semiconductor memory device.

[Prior Art] FIG. 3 is a block diagram showing a schematic configuration and signal exchange in a nonvolatile semiconductor memory device.
50 is a memory array, 51 is a row gate, 52 is a data input / output buffer, 53 is a column decoder, 54 is a row decoder, 55 is a control circuit, 56 is an address signal, 57 is an external control signal, 58 is a column decoder output, 59 Is a row decoder output, 60 is a row gate control signal, 61 is a data input / output buffer control signal, 62 is a data input / output signal, 63 is a word line, 64 is a bit line, and 65 is a memory cell.

FIG. 4 shows a part of the inside of the memory array 50 shown in FIG. 3, and is the 1987 IEEE International Solid State Circuits Conference.
d-State Circuits Conference) Digest page 76-77
FIG. 5 is an operation explanatory diagram showing a simple equivalent circuit of the conventional nonvolatile semiconductor memory device shown in page and write and erase voltages of each electrode, and FIG. 5 is used in FIG. FIG. 3 is a cross-sectional view showing the structure of a memory transistor that is installed. In FIG. 4, Q5 to Q8 are transistors having a floating gate, and a part of the second layer gate, that is, the control gate, extends to the source side. 15 is a non-selected bit line, 16 is a selected bit line, 17 is a common source line, 18 is a selected word line, 19 is a non-selected word line,
V _PP2 is a positive voltage from an external input. Further, in FIG. 5, 20 is a drain electrode, 21 is a control gate electrode, 22 is a source electrode, 23 is a control gate formed of polysilicon, 24 is a floating gate in an electrically floating state, and 25 is about 200Å. Is a thin oxide film, 26 is a drain diffusion region, 27 is a source diffusion region, and 28 is a substrate. The bit lines 15 and 16 in FIG. 4 are connected to the drain electrode 20 of each memory transistor, the word lines 18 and 19 are connected to the control gate electrode 21 of each memory transistor, and the source line 17 is the source of each memory transistor. electrode
Connected to 22.

Next, the operation will be described. The writing method in this conventional example is to write "1" to all memory cells at the time of erasing,
At the time of writing, "0" is written only to the bit to be written. First, the erase operation will be described. By setting all the bit lines 15 and 16 to a high voltage (hereinafter abbreviated as V _PP2 ) and setting all the word lines 18 and 19 to 0 V, between the floating gate 24 and the drain diffusion region 26 in FIG. A high electric field is generated. At this time, the electrons accumulated in the floating gate 24 are extracted to the drain diffusion region 26 through the thin oxide film 25 by the tunnel phenomenon. In this state, the floating gate 24 is in a depleted state of electrons, so that the threshold voltage of the memory transistor seen from the control gate 23 becomes lower than that before the erase operation.
This state is called an erased state and is set to logic "1".

Next, the write operation will be described. The writing method is EPRO
Same as programming in M, with selected bit line 16 at V _PP2 , unselected bit line 15 at 0 V, selected word line 18 at V _PP2 , unselected word line 19 at 0 V, common source line at By setting to 0V, V _PP2 is applied to the word line and V _{PP is applied to} the bit line.
Writing is performed to transistor Q7 to which _PP 2 is applied. At this time, the drain diffusion region 26 of the transistor Q7
Hot electrons are generated in the vicinity, are accelerated by V _PP2 applied to the control gate 23, and are injected into the floating gate 24. In this state, the floating gate 24 is in the state of accumulating electrons, so the threshold voltage of the memory transistor seen from the control gate 23 is
It becomes higher than that before the writing operation. This state is called a write state and is set to logic "0".

This conventional example does not need to be erased by ultraviolet rays like EPROM, and can be electrically erased while mounted on the board.
The feature is that the chip area can be reduced because the memory cell can be configured with one transistor instead of using two transistors as in EPROM.

[Problems to be Solved by the Invention] The conventional writing and erasing methods for the non-volatile semiconductor memory device have been performed as described above, and since writing is performed by injecting hot electrons, therefore, a high voltage for internal boosting is required. However, it has no current drive capability, and therefore requires a high voltage (V _PP2 ) from an external input. Therefore, there is a drawback that a 5V single power supply operation cannot be performed by a high voltage due to internal boosting like other circuits. Further, since writing is performed by hot electron injection, a current flows through the thin oxide film 25, causing deterioration, and therefore, there is a problem that the number of times of erasing and writing is small (about 10 ³ times).

The present invention has been made to solve the above-mentioned conventional problems. It is possible to operate a single 5V power supply with a high voltage by an internal booster, and it is possible to increase the number of erase and write operations. An object of the present invention is to provide a writing and erasing method for a nonvolatile semiconductor memory device capable of stably maintaining a high voltage due to internal boosting.

[Means for Solving the Problems] In the writing and erasing method of the nonvolatile semiconductor memory device according to the present invention, a thin first insulating layer is formed on a substrate having a drain diffusion region and a source diffusion region in the substrate. A plurality of memory transistors having a control gate via a second insulating film, and a floating gate electrically floating through the plurality of memory transistors. A plurality of memory transistors that are arranged in a plurality of column directions are connected to the same word line in each row direction, and control gates of a plurality of memory transistors that are arranged in the same row direction are connected to the same word line. Each drain diffusion region of the memory transistors is connected to the same bit line, and each source diffusion region of all the plurality of memory transistors is connected to a common source line, All the word lines are connected to a first voltage generating means for applying a signal voltage for writing or erasing a memory transistor by utilizing a tunnel phenomenon, and all the bit lines are connected to the first voltage generating means. After connecting to the second voltage generating means for providing the signal voltage for writing or erasing the memory transistor by utilizing the tunnel phenomenon in cooperation with the voltage generated by the voltage generating means, all of the plurality of memory cells are connected. Bit line first
Of the floating gates of all of the plurality of memory transistors by simultaneously applying a DC voltage of a value of 1 to the plurality of word lines and simultaneously applying a DC voltage of an internally boosted second value larger than the first value to all of the plurality of word lines. An electron is injected from each of the drain diffusion regions by a tunnel phenomenon to create an erased state, and a first word line among the plurality of word lines is connected to the control gate of the memory transistor to be written. And a third value of the DC voltage between the first value and the second value are applied to the other word lines, and at the same time, the write operation of the plurality of bit lines is performed. By applying the internally boosted DC voltage of the second value to the bit line connected to the drain diffusion region of the memory transistor to be formed, and applying the DC voltage of the third value to the other bit lines. It is intended to make a write state by electrons stored in the floating gate of only the memory transistor to be writing is withdrawn by a tunnel effect.

[Operation] In the writing and erasing method of the nonvolatile semiconductor memory device according to the present invention, all the bit lines have the first
The DC voltage of the value of
An internally boosted second value of DC current greater than the value of is given. As a result, electrons are injected into the floating gates of all the memory transistors from the respective drain diffusion regions by the tunnel phenomenon, and erasing is performed.

On the other hand, in the following cases, among the plurality of word lines, the word line connected to the control gate of the memory transistor to be written is supplied with the first value of the DC voltage, and the other word lines are supplied with the first value. A DC voltage having a third value, which is a value between the second value and the second value, is applied, and at the same time, among the plurality of bit lines,
The internally boosted second value DC voltage is applied to the bit line connected to the drain diffusion region of the memory transistor to be written, and the third value DC voltage is applied to the other bit lines.

As a result, electrons connected to the floating gate of only the memory transistor to be written are extracted by the tunnel phenomenon, and writing is performed.

In this way, the tunnel phenomenon in erasing and writing is obtained by utilizing the high voltage due to the internal boosting, so that 5V single power supply operation becomes possible. In addition, since only the tunnel phenomenon is used in erasing and writing, the deterioration of the thin first insulating film can be further reduced, which enables erasing and writing a large number of times.

Further, by applying a DC voltage of the third value to the bit line connected to the other memory transistor of the memory transistor to be written at the time of writing, the internally boosted DC value of the second value at the time of writing It is possible to keep the voltage level stable. The reason is as follows.

Of the memory transistors connected to the word line to which the DC voltage of the third value is applied during writing, the second
The memory transistor connected to the bit line to which the DC voltage of the value of is applied is turned on, whereby
The voltage on the common source line rises.

In that case, since the DC voltage of the third value is applied to the bit line connected to the other memory transistor connected to the word line, the bit is transmitted from the common source line through those transistors. No leakage current flows through the wire.

Therefore, the level of the boosted second value of the DC voltage at the time of writing does not decrease and is kept stable.

[Embodiment of the Invention] FIG. 1 is an operation explanatory view showing a simple equivalent circuit and a write voltage of each electrode according to an embodiment of the present invention.
The figure is a cross-sectional view showing the structure of the memory transistor used in FIG. In FIG. 1, Q1 to Q4 are transistors having a floating gate and a thin oxide film region in the overlapping portion of the floating gate and drain, and the second layer gate, that is, a part of the control gate extends to the source side. ing. 1 is an unselected bit line, 2 is a selected bit line, 3 is a source line common to all cells, 4 is a selected word line, 5 is an unselected word line,
V _PP1 is a positive voltage due to internal boosting, and 1/2 V _PP1 is a positive voltage which is about half that of V _PP1 . Further, in FIG. 2, 6 is an aluminum drain electrode, 7 is a polysilicon control gate electrode, 8 is an aluminum source electrode, 9 is a control gate made of polysilicon, and 10 is an electricity made of polysilicon. A floating gate in a floating state, 11 is a thin silicon oxide film having a thickness of about 100 Å, 12 is a drain diffusion region, 13 is a source diffusion region, and 14 is a silicon substrate. Bit lines 1 and 2 in FIG. 1 are connected to the drain electrode 6 of each memory transistor, word lines 4 and 5 are connected to the control electrode 7 of each memory transistor, and source line 3 is the source electrode of each memory transistor. 8 is connected.

Next, the operation will be described. Here, in the conventional example, the state in which electrons are extracted from the floating gate is the erased state, and the state in which electrons are injected into the floating gate is the written state. However, this definition may be either, and in the present invention, a state in which electrons are injected into the floating gate is an erased state, and a state in which electrons are extracted from the floating gate is a written state.

First, the erase operation will be described. Bit lines 1 and 2 are 0V
Then, by setting the word lines 4 and 5 to V _PP1 , the second
Drain diffusion region 12 and floating gate in the figure
A high electric field is generated between 10 and 10. At this time, electrons tunnel through the thin oxide film 11 and are injected from the drain diffusion region 12 into the floating gate 10. In this state, the floating gate 10 is in an electron accumulation state,
The threshold voltage of the memory transistor viewed from the control gate 7 is higher than that before the erase operation. This state is called an erased state and is set to logic "1".

Next, the write operation will be described. The selected bit line 2 is V _PP1 , the unselected bit line 1 is about half the voltage of V _PP1 (hereinafter abbreviated as 1/2 V _PP1 ), the selected word line 4 is 0 V,
By making the unselected word line 5 1/2 V _PP1 and the common source line 3 floating, the write operation is performed only for the transistor Q3 to which 0 V is applied to the word line and V _PP1 is applied to the bit line. At this time, a high electric field is generated between the drain diffusion region 12 of the transistor Q3 and the floating gate 10, electrons tunnel through the thin oxide film 11, and the electrons accumulated in the floating gate 10 are extracted to the drain diffusion region 12. Floating gate 10 in this state
Becomes a depletion state of electrons, the threshold voltage of the memory transistor seen from the control gate 9 becomes lower than that before the writing operation. This state is called a write state and is set to logic "0". In addition, unselected memory transistors Q1 and Q
For 2 and Q4, the tunnel current is considered to be negligibly small because the electric field applied to the floating gate 10 and the drain diffusion region 12 is about half that of the written memory transistor Q3. There is no change in value voltage.

When writing, unselected memory transistor 94 and
When 1 / 2V _PP1 is applied to each control gate 7 when 92 is in the written state (state where the threshold voltage is low), both memory transistors 94 and 92 are turned on.

By turning on the first memory transistor 94, the common source line 3 becomes a voltage close to 1 / 2V _PP1 . This is because charging is performed through the route of the leading bit line 2 to which V _PP1 is applied → the memory transistor Q4 → the common source line 3. In that case, if unselected bit line 1
Is much lower than 0V or 1 / 2V _PP1 , a leak current flows through the path of common source line 3 → memory transistor Q2 → non-selected bit line 1.

When such leakage current flows, the internal boosted V _PP1
The level of will decrease. The reason is as follows. That is, V _PP1 is internally boosted,
Specifically, it is generated from an internal booster circuit (not shown). The boosted voltage generated by the internal booster circuit is
Generally, since the current supply capability is low, the voltage level will drop even with a slight leak current.

Therefore, when such leakage current flows,
Since the level of V _PP1 is lowered, the write operation cannot be performed.

Therefore, it is necessary to supply to the non-selected bit line 1 a voltage that acts to eliminate the path through which such a leak current flows.

In this embodiment, in the unselected bit line 1 at the time of writing
By applying 1 / 2V _PP1 , the leak current path can be eliminated. Therefore, the level of internally boosted V _PP1 at the time of writing can be stably maintained.

In this embodiment, it is desirable to use the memory transistor having the structure shown in FIG. 2, but the reason is as follows. That is, when writing is performed using the tunnel phenomenon, the threshold voltage is determined by the electric field applied to the tunnel oxide film during writing. On the other hand, the capacitance ratio (the ratio between the capacitance between the control gate 9 and the floating gate 10 and the capacitance between the floating gate 10 and the drain diffusion region 12 in FIG. 2) is used to determine the electric field. It is desirable to be constant. However, in the memory transistor having the structure shown in FIG. 5, the capacitance between the floating gate 24 and the drain diffusion region 26 is determined by the lateral diffusion length of the drain diffusion region 26, which is difficult to control. On the other hand, the memory transistor shown in FIG.
By using 11, it is possible to obtain the necessary capacitance value with good controllability, and thus obtain a stable threshold voltage.

[Effects of the Invention] As described above, according to the present invention, since erasing and writing can be performed by the tunnel phenomenon, a high voltage of external input is not required, and the number of times of erasing and writing can be improved. It is possible to perform a large number of operations, and it is possible to obtain a writing and erasing method for a nonvolatile semiconductor memory device which is easier to use and has excellent durability.

In addition, at the time of writing, to prevent leakage current from the non-selected memory transistor to the non-selected bit line,
Since the intermediate voltage is applied to the non-selected bit lines, the internally boosted high voltage can be stably maintained during writing.

[Brief description of drawings]

FIG. 1 is an operation explanatory view showing a simple equivalent circuit of a nonvolatile semiconductor memory device showing one embodiment of the present invention and a write and erase voltage applied to each electrode, and FIG. FIG. 3 is a cross-sectional view showing a structure of a memory transistor used in one embodiment, FIG. 3 is a block diagram showing a schematic configuration and signal exchange of a current semiconductor memory device, and FIG. FIG. 5 is an operation explanatory diagram showing a simple equivalent circuit of a conventional nonvolatile semiconductor memory device and a write and erase voltage applied to each electrode. FIG. 5 is a memory transistor used in the conventional nonvolatile semiconductor memory device. It is a cross-sectional view showing the structure of. In the figure, 1 is an unselected bit line, 2 is a selected bit line, 3 is a source line common to all cells, 4 is a selected word line, 5 is an unselected word line, 6 is a drain electrode, and 7 is a drain electrode.
Is a control gate electrode, 8 is a source electrode, 9 is a control gate, 10 is a floating gate, 11 is a thin oxide film, 12 is a drain diffusion region, 13 is a source diffusion region,
14 is a substrate, 15 is an unselected bit line, 16 is a selected bit line, 17 is a source line common to all cells, 18 is a selected word line, 19 is an unselected word line, 20 is a drain electrode, 21 is a control gate electrode, 22 is a source electrode, 23 is a control gate, 24 is a floating gate, 25 is a thin oxide film, 26 is a drain diffusion region, 27 is a source diffusion region, 28
Is a substrate, 29 is an oxide film, 50 is a memory array, 51 is a row gate, 52 is a data input / output buffer, 53 is a column decoder, 54 is a row decoder, 55 is a control circuit, 56 is an address signal, and 57 is an external control signal. , 58 is a column decoder output, 59 is a row decoder output, 60 is a row gate control signal, 61 is a data input / output buffer control signal, 62 is a data input / output signal, 63 is a word line, 64 is a bit line, and 65 is a memory cell. , Q1 to Q8 are memory transistors, V _PP1 and V _PP2 are positive voltages, and 1/2 V _PP1 is about a half positive voltage.

 ─────────────────────────────────────────────────── --Continued from the front page (56) References JP 61-99997 (JP, A) JP 58-115691 (JP, A) Nikkei Electronics, No. 241 (1980-6-23), Nikkei McGraw-Hill Company, P. 198-P. 207

Claims (8)

[Claims] 1. A drain diffusion region and a source diffusion region are provided in a substrate, a floating gate electrically floating is provided on the substrate through a thin first insulating film, and a first floating gate is provided on the floating gate. A step of preparing a plurality of memory transistors having control gates through two insulating films, the plurality of memory transistors being arranged in a plurality of row directions and a plurality of column directions, each row direction being in the same row direction. Connecting the respective control gates of the plurality of memory transistors arranged in a row to the same word line, and connecting the drain diffusion regions of the plurality of memory transistors arranged in the same column direction to the same bit line in each column direction, Connecting the source diffusions of each of the plurality of memory transistors to a common source line, and connecting each of the plurality of word lines to a memory transistor. First to give the writing or erasing of the static signal voltage for using tunneling
And connecting each of all the plurality of bit lines with the voltage generated by the first voltage generating means to write or erase the memory transistor using a tunnel phenomenon. Connecting to a second voltage generating means for providing a signal voltage for performing;
By applying a direct current voltage of a first value to all of the plurality of bit lines and simultaneously applying a direct current voltage of an internally boosted second value greater than the first value to all of the plurality of word lines. , A step of creating an erased state by injecting electrons from each drain diffusion region into each floating gate of each of the plurality of memory transistors by a tunnel phenomenon, and A direct current voltage of the first value is applied to a word line connected to the control gate of a memory transistor to be formed, and another word line has a value between the first value and the second value. The current voltage of the third value is applied, and at the same time, the first boosted internal voltage is applied to the bit line connected to the drain diffusion region of the memory transistor to be written among the plurality of bit lines. Given DC voltage value, and by providing a DC voltage of said third value to another bit line,
A writing and erasing method for a non-volatile semiconductor memory device, comprising a step of creating a written state by extracting electrons accumulated in a floating gate of only the memory transistor to be written by a tunnel phenomenon. 2. The writing and erasing method of a nonvolatile semiconductor recording device according to claim 1, wherein the first voltage generating means includes a row decoder means. 3. The writing and erasing method for a nonvolatile semiconductor memory device according to claim 1, wherein said second voltage generating means is a column decoder means. 4. The method for writing and erasing data in a nonvolatile semiconductor memory device according to claim 1, wherein the first value is a value of ground potential. 5. The method of writing and erasing in a nonvolatile semiconductor memory device according to claim 1, wherein the second value is a positive value due to internal boosting. 6. The writing of the nonvolatile semiconductor memory device according to claim 1, wherein the third value is about 1/2 of the second value. And erasing method. 7. A method for writing and erasing a nonvolatile semiconductor memory device according to claim 1, wherein the first and second insulating films are silicon dioxide films. 8. The method for writing and erasing a nonvolatile semiconductor memory device according to claim 1, wherein the substrate is a silicon substrate.