JPH09115291A - Semiconductor nonvolatile memory and its write method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the occurrence of hot electron when a memory cell is written and to prevent erroneous write due to that. SOLUTION: In a memory array connecting control gates of memory cells 1, 3 to word line WL1 , the control gates of the memory cells 2, 4 to the word line WL2 , sources and drains of the memory cells 1, 2, 3, 4 to source lines SL1 , SL2 and bit lines BL1 , BL2 respectively arranged vertically to the word lines WL1 , WL2 , the write is performed by three steps that is, first, all word lines WL1 , WL2 are raised to intermediate potential, then a non-selection bit line BL2 is raised to the intermediate potential, and finally a selection word line WL1 is raised to high potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor non-volatile memory device for writing data by giving and receiving charges to and from a charge storage layer and a writing method thereof.

[0002]

2. Description of the Related Art In recent years, with the spread of portable information terminal equipment and the like, there is an increasing need for a large-capacity flash memory as an external storage device.

FIG. 4 is a simplified cross-sectional view showing the structure of a commonly used flash memory and its equivalent circuit diagram. In FIG. 4, 10 is a control gate, 11 is a floating gate, 12 is a gate oxide film, 13 is a source diffusion layer, 14 is a drain diffusion layer, and 15 is a silicon substrate. Here, for example, the silicon substrate 15 is made of p-type silicon, and the source diffusion layer 13 and the drain diffusion layer 14 are made of n-type silicon. Since the floating gate 11 is electrically insulated from the surroundings, once electrons are injected into the floating gate 11, they are held almost semipermanently.

In order to reduce the voltage of rewriting operation of the flash memory and improve the reliability, electrons are injected into the floating gate 11 and electrons are emitted from the floating gate 11 by using an FN (Fowler) which uses the entire channel region of the memory cell. -Nordheim) The method of tunneling is effective.

FIG. 5 is a circuit diagram of a memory array composed of the memory cells shown in FIG. 4, and is a circuit diagram showing a bias state at the time of writing to the memory cells. 5, reference numerals 1, 2, 3, and 4 denote memory cells having the same structure as that of FIG. 4A, WL ₁ and WL ₂ denote word lines, and BL ₁ and BL.
Reference numeral ₂ is a bit line, and SL ₁ and SL ₂ are source lines.

The control gates of the memory cells 1 and 3 are connected to the word line WL _1, and the control gates of the memory cells 2 and 4 are connected to the word line WL ₂ . The sources of the memory cells 1 and 2 are connected to the source line SL ₁ , and the drains of the memory cells 1 and 2 are connected to the bit line BL ₁ . The sources of the memory cells 3 and 4 are the source lines S.
Is connected to L _2, the drain of the memory cell 3 and the memory cell 4 are connected to the bit line BL _2. Further, the bit lines BL ₁ and BL ₂ are arranged in parallel with the source lines SL ₁ and SL _2, and these signal lines are arranged perpendicularly to the word lines WL ₁ and WL ₂ .

In the memory array configured as described above, when writing data to a memory cell, a positive high voltage is applied to the word line connected to the control gate of the selected memory cell to control the unselected memory cell. An intermediate level voltage between the positive high voltage and the ground potential is applied to the word line connected to the gate, and the source line and the bit line connected to the selected memory cell are held at the ground potential,
This is performed by applying an intermediate level voltage to the source line and the bit line connected to the non-selected memory cell.

Here, the write operation will be described with the memory cell 1 as the selected memory cell, for example.
When writing to the memory cell 1, as shown in FIG. 5, a positive high voltage, for example, a voltage of 15 to 20 V is applied to the word line WL ₁ connected to the control gate of the memory cell 1, and another word is written. An intermediate level voltage, for example, a voltage of 7 to 10 V is applied to the line WL ₂ , the source line SL ₁ connected to the source of the memory cell 1 is set to the floating state, and the drain of the memory cell 1 is connected. A voltage of 0V is applied to the bit line BL ₁ , and an intermediate level voltage, for example, a voltage of 7 to 10V is applied to the source line SL ₂ and the bit line BL ₂ .

In the bias state described above, a high voltage of 15 to 20 V is applied to the control gate of the selected memory cell 1, the source of the memory cell 1 is in a floating state, and the voltage of 0 V is applied to the drain of the memory cell 1. Applied, through the channel region of the memory cell 1,
Electrons are injected into the floating gate of the memory cell 1 by FN tunneling, and the memory cell 1 is written.

In this case, the same word line W as the memory cell 1 is used.
A high voltage of 15 to 20 V is applied to the control gate of the memory cell 3 connected to L ₁ as well.
Since an intermediate voltage of 7 to 10 V is applied to the bit line BL _{2 of} , the erroneous writing of the memory cell 3 is prevented.

Further, the unselected word line WL ₂ is also 7-10.
Since the intermediate voltage of V is applied, electrons are extracted from the floating gate of the non-selected memory cell 4 to the bit line BL ₂ set to the intermediate potential, that is, erroneous erasing of the memory cell 4 is prevented.

As described above, when writing to the memory cell 1, the source lines SL ₁ and SL ₂ are separated from the ground wiring and set to the floating state. Therefore, at the time of writing, the source lines SL ₁ and SL ₂
Are charged to the same potential as the corresponding bit lines BL ₁ and BL ₂ . By the way, the above-mentioned potential setting is performed in two steps as shown in FIG.

FIG. 6 is a time chart showing the potential change of each signal line in the write operation of the memory cell 1 described above. FIG. 6A shows the potential of the word line WL ₁ , FIG.
Is the potential of the word line WL ₂ , and FIG. 6C shows the bit line BL _1.
6 (d) is the potential of the bit line BL ₂ ,
(E) shows the potential of the source line SL ₂ .

As shown in FIGS. 6A, 6B and 6D, all the word lines WL in the selected memory array.
₁ , WL ₂ and unselected bit line BL ₂ are simultaneously raised to an intermediate potential, for example, a potential of 7 to 10V, and then the selected word line WL ₁ is further raised to a high potential of 15 to 20V. , Voltage is applied to each signal line. Further, as shown in (c) and (e) of FIG. 6, the selected bit line BL ₁ is always held at the ground potential and the unselected source line SL ₂ is unselected bit line B during the write operation.
It is charged to the same potential as L ₂ .

[0015]

However, in the above-described conventional write timing, the first step, that is, the non-selected bit line BL ₂ and the word line W is performed.
When L ₁ and WL ₂ are simultaneously activated, the memory cell 3
A transient current flows from the unselected bit line BL ₂ to the unselected source line SL ₂ via the memory cell 4 and the source line SL ₂
Are charged to the same potential as the bit line BL ₁ . At this time, there is a problem that hot electrons are generated in the memory cells 3 and 4 and erroneous writing occurs in the memory cells 3 and 4.

The present invention has been made in view of such circumstances, and an object thereof is a semiconductor nonvolatile memory device capable of suppressing generation of hot electrons at the time of writing to a memory cell and preventing erroneous writing based on the hot electrons. It is to provide the writing method.

[0017]

In order to achieve the above object, according to the present invention, a plurality of memory cells having a charge storage layer are arranged in rows and columns, and the control gates of the memory cells in the same row are connected to a common word line. A semiconductor nonvolatile memory device in which diffusion layers of connected memory cells in the same column are connected to a common bit line, and all word lines are set to a first potential and a second potential higher than this when writing. After being held at the intermediate potential between and, the non-selected bit lines are held at the intermediate potential, and only the selected word line is held at the second potential.

Further, in the present invention, a plurality of memory cells having charge storage layers are arranged in a matrix, control gates of memory cells in the same row are connected to a common word line, and diffusion layers of memory cells in the same column are connected. Is a method for writing to a semiconductor nonvolatile memory device connected to a common bit line, wherein all word lines are set to an intermediate potential between a first potential and a second potential higher than the first potential, and then unselected. The bit line is set to the intermediate potential, then only the selected word line is set to the second potential, and charges are injected into the charge storage layer of the selected memory cell to perform writing.

Further, in the present invention, the setting time to the intermediate potential of the non-selected bit line is set longer than the setting time to the intermediate potential and the second potential of the word line.

According to the present invention, all the word lines in the selected memory array are raised to the intermediate potential and then the non-selected bit lines are raised. As a result, the electric field in the vicinity of the drain of the non-selected memory cell can be relaxed, and the generation of hot electrons can be reduced. Furthermore, by slowly raising the non-selected bit lines, the potential difference between the bit line and the source line that occurs transiently can be reduced, the amount of hot electrons generated can be reduced, and erroneous writing to non-selected memory cells due to hot electrons. Can be prevented.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of a memory array comprising a semiconductor nonvolatile memory device according to the present invention, showing a bias state at the time of writing. In FIG. 1, 1, 2, 3, 4
Is a memory cell, WL ₁ and WL ₂ are word lines, BL ₁ and B
L ₂ is a bit line, and SL ₁ and SL ₂ are source lines, respectively.

The control gates of the memory cells 1 and 3 are connected to the word line WL _1, and the control gates of the memory cells 2 and 4 are connected to the word line WL ₂ . The sources of the cells 1 and 2 are connected to the source line SL ₁ , and the drains of the memory cells 1 and 2 are connected to the bit line BL ₁ . The sources of the memory cells 3 and 4 are connected to the source line SL ₂ , and the drains of the memory cells 3 and 4 are connected to the bit line BL ₂ . Furthermore, the bit line BL
₁ and BL ₂ are arranged in parallel with the source lines SL ₁ and SL _2, and these signal lines are arranged perpendicularly to the word lines WL ₁ and WL ₂ .

FIG. 1 shows the bias state of each signal line of the memory array when, for example, the memory cell 1 is selected and a write operation is performed on it. As shown in the figure, when writing to the memory cell 1,
A positive high voltage, for example, a voltage of 15 to 20 V, is applied to the word line WL ₁ connected to the control gate of
An intermediate level voltage, for example, 7 is applied to the other word line WL _2.
A voltage of -10 V is applied, the source line SL ₁ connected to the source of the memory cell 1 is set to the floating state, and the bit line BL connected to the drain of the memory cell 1 is set.
A voltage of 0V is applied to ₁ , and the source line SL ₂ and the bit line BL ₂ each have an intermediate level voltage, for example, 7V.
A voltage of -10V is applied.

In the bias state described above, a high voltage of 15 to 20 V is applied to the control gate of the selected memory cell 1, the source of the memory cell 1 is in a floating state, and the drain of the memory cell 1 is at a voltage of 0 V. Is applied through the channel region of the memory cell 1,
Electrons are injected into the floating gate of the memory cell 1 by FN tunneling, and the memory cell 1 is written. Then, the potential setting at the time of writing is the following 3
It is performed by steps.

FIG. 2 is a time chart of each signal line in the write operation of the memory cell 1 described above. The write operation of the memory cell will be described below with reference to the time chart of FIG. FIG. 2A shows a word line WL
₁ potential, FIG. 2B shows the word line WL ₂ potential, FIG.
2C shows the potential of the bit line BL ₁ , FIG. 2D shows the potential of the bit line BL ₂ , and FIG. 2E shows the potential of the source line SL ₂ .

The write operation of the memory cell will be described below with reference to the time chart of FIG. First, as shown in FIGS. 2A and 2B, the write operation is started at time t ₀ , and all the word lines WL ₁ and WL ₂ in the selected memory array are simultaneously set to an intermediate potential, for example, The potential is raised to 7-10V.

Then, as shown in FIG. 2D, time t
_A little later than ₀ , at time t ₁ , the non-selected bit line BL ₂ is also raised to the intermediate potential, for example, the potential of 7 to 10V.

Further after that, at time t ₂ , the selected word line WL ₁ has a higher potential, for example, 1
It is raised to 5 to 20V.

Through the above three steps, a predetermined voltage is applied to each signal line, and the memory cell 1 is written. Further, as shown in (c) and (e) of FIG. 2, during the write operation, the selected bit line BL ₁ is held at the ground potential, and the unselected source line SL ₂ is at the same potential as the unselected bit line BL _2. Be charged.

In the write operation of such a memory cell, the word line WL ₂ is already raised to the intermediate potential before the non-selected bit line BL ₂ is raised to the intermediate potential, and the unselected memory cell 3 and the memory cell are In 4,
Generation of hot electrons due to the charge current is suppressed, and erroneous writing associated therewith is prevented.

The effect of reducing hot electrons when writing is performed in the above-described three-step sequence will be described.

The amount I _h of hot electrons generated in the memory cell can be expressed by the following equation.

[Formula 1] I _h = α · I _ds = α · dq / dt (1)

Here, I _ds is the value of the current that flows when the source of the memory cell is charged. α is the generation efficiency of hot electrons, which depends on the electric field strength near the drain of the memory cell. When the charge amount of the source is a constant value Q _s , the total charge amount H of hot electrons generated is given by the following equation.

(Equation 2)

In the conventional write sequence shown in the time chart of FIG. 6, all word lines WL ₁ and WL ₂ of the selected memory array and unselected bit lines BL _{2 are} selected.
Are simultaneously raised to substantially the same potential, so that in the memory cell 3 and the memory cell 4, the vicinity of the drain is in a pinch-off state, a high electric field region is formed, and hot electron generation efficiency is increased.

On the other hand, in the sequence of the first embodiment shown in FIG. 2, the word lines WL ₁ and WL ₂ have already risen to the intermediate potential when the unselected bit line BL ₂ has risen to the intermediate potential. Therefore, the memory cell 3
In the memory cell 4, a channel is formed on the entire surface of the region under the floating, and the electric field is substantially uniform from the drain to the source. Therefore, the electric field near the drain is relaxed, and hot electrons are less likely to be generated.

Further, since the driving capability of the transistor is high, the source line SL ₂ is quickly charged, and the transient potential difference from the bit line BL ₂ is smaller than that in the conventional writing. As a result, the electric field of the channel is further relaxed, so that the generation efficiency of hot electrons is further suppressed. For the reason described above, in the present embodiment, generation of hot electrons in the non-selected memory cells is suppressed, and erroneous writing in the memory cells based on the hot electrons is prevented.

As described above, according to this embodiment, the control gates of the memory cells 1 and 3 are connected to the word line WL _1, and the control gates of the memory cells 2 and 4 are connected to the word line WL ₂ . Memory cells 1, 2,
Sources and drains of 3 and 4 are word lines WL, respectively.
_1, WL ₂ and vertically disposed source lines SL _1, SL ₂
In the memory array connected to the bit lines BL ₁ and BL ₂ , when performing the write operation to the selected memory cell, first, all the word lines WL ₁ and WL ₂ are raised to the intermediate potential, and then the non-selected Since writing is performed in 3 steps of raising the bit line BL ₂ to an intermediate potential and finally raising the selected word line to a high potential, generation of hot electrons in the non-selected memory cells 3 and 4 is suppressed, and The erroneous writing of the memory cell based on it is prevented.

Second Embodiment FIG. 3 is a diagram showing a second embodiment of the semiconductor nonvolatile memory device according to the present invention, and is a time chart showing the potential of each signal line at the time of writing a memory cell. FIG.
3A shows the potential of the word line WL ₁ , FIG. 3B shows the potential of the word line WL ₂ , FIG. 3C shows the potential of the bit line BL ₁ , and FIG. 3D shows the potential of the bit line BL ₂ . FIG. 3E shows the potential of the source line SL ₂ .

In the second embodiment, similarly to the first embodiment described above, when writing to the memory cell 1 shown in FIG. 1, the potential of each signal line is set in three steps. Be seen. Hereinafter, referring to the time chart of FIG. 3,
The write operation of the memory cell 1 will be described. First,
As shown in FIGS. 3A and 3B, the write operation is started at time t ₀ , and all the word lines WL ₁ and WL ₂ in the selected memory array are simultaneously subjected to the intermediate potential, for example, 7 to. It is raised to a potential of 10V.

Then, as shown in FIG. 3D, time t
_A little later than ₀ , at time t ₁ , the non-selected bit line BL ₂ is also raised to the intermediate potential, for example, the potential of 7 to 10V.

After a further delay, at time t ₂ , the selected word line WL ₁ has a higher potential, for example, 1
It is raised to 5 to 20V.

Through the above three steps, a predetermined voltage is applied to each signal line, and writing is performed on the memory cell 1. However, in the second embodiment, the second step, that is, the step of raising the non-selected bit line BL ₂ to the intermediate potential is performed more slowly than the other steps. It takes more than double the time and takes place at a slow start-up speed.

By doing so, the non-selected bit line B
The potential difference between L ₂ and the non-selected source line SL ₂ is further reduced, and the electric field near the drains of the non-selected memory cells 3 and 4 is further relaxed. Occasionally, the occurrence of hot electro is further suppressed, and the effect of preventing erroneous writing can be further improved.

[0044]

As described above, according to the semiconductor nonvolatile memory device and the method of writing the same of the present invention, it is possible to suppress the generation of hot electrons at the time of writing to a memory cell and prevent erroneous writing based on this. There is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory array including a semiconductor nonvolatile memory device according to the present invention.

FIG. 2 is a time chart of memory writing according to the first embodiment of the present invention.

FIG. 3 is a time chart of memory writing according to the second embodiment of the present invention.

FIG. 4 is a simplified cross-sectional view and circuit diagram of a flash memory.

FIG. 5 is a circuit diagram showing a write state of a conventional memory array.

FIG. 6 is a time chart of conventional memory writing.

[Explanation of symbols]

1, 2, 3, 4 ... Memory cells BL ₁ , BL ₂ ... Bit lines WL ₁ , WL ₂ ... Word lines SL ₁ , SL ₂ ... Source lines

Claims (3)

[Claims] 1. A plurality of memory cells having charge storage layers are arranged in a matrix, control gates of memory cells in the same row are connected to a common word line, and diffusion layers of memory cells in the same column are a common bit. A semiconductor non-volatile memory device connected to a line, wherein during writing, all word lines are held at an intermediate potential between a first potential and a second potential higher than this potential, and then unselected bit lines are A semiconductor nonvolatile memory device which holds only a selected word line at a second potential in a state of being held at the intermediate potential. 2. A plurality of memory cells having charge storage layers are arranged in a matrix, control gates of memory cells in the same row are connected to a common word line, and diffusion layers of memory cells in the same column are a common bit. A method of writing to a semiconductor non-volatile memory device connected to lines, wherein all word lines are set to an intermediate potential between a first potential and a second potential higher than the first potential, and then non-selected bit lines are set. A semiconductor non-volatile memory device that performs writing by setting the intermediate potential and then setting only the selected word line to the second potential and injecting charges into the charge storage layer of the selected memory cell Writing method. 3. The method for writing to a semiconductor nonvolatile memory device according to claim 2, wherein the setting time to the intermediate potential of the non-selected bit line is set longer than the setting time to the intermediate potential and the second potential of the word line. .