JPH0831963A - Non-volatile semiconductor storage - Google Patents

Abstract

PURPOSE:To reliably rewrite data without causing excessive erasure by setting the threshold voltage of a memory cell when a floating gate is in neutral state to a value between both threshold values when the memory cell is erased and is written. CONSTITUTION:A floating gate memory cell where a floating gate and a control gate are formed is provided on the channel region of a semiconductor substrate. The threshold voltage when the floating gate is in neutral state 'initial' is set to a value between a threshold voltage when the memory cell is in erased state '0' and that when the memory cell is in writing state '1'. For example, the threshold value in the writing state '1' and the erasure state '0' are set to approximately 7V and 2V, respectively, and the threshold value when the floating gate is in the neutral state 'initial' is set to approximately 4V, thus drastically reducing the number of memory cells in excessive erasure state and reliably achieving rewriting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an EEPROM (Electr
(ically Erasable and Programmable Read Only Memory)
And other non-volatile semiconductor memory devices.

[0002]

2. Description of the Related Art An EEPROM is capable of electrically writing and erasing data stored in a memory cell and has a non-volatile property such that the data is not permanently erased even when the power is turned off. Among such EEPROMs, in a flash type EEPROM (hereinafter, referred to as “flash memory”) in which data is erased in a unit of all bits or in units of blocks, one memory cell is MO.
Since it can be configured with only one S-transistor, it is an ultraviolet erasable EPROM (Erasable and Programmable Read Only).
It has the advantage that it can be highly integrated to the same extent as Memory). The structure and operation of the conventional flash memory will be described below with reference to FIGS. 4, 5 and 6.

FIG. 4 is a schematic sectional view showing the structure of a memory cell of a conventional flash memory having a two-layer stack gate structure. In FIG. 4, in the surface region of the P-type silicon substrate 1, a pair of N ⁺ impurity diffusion layers, that is, a source 6 and a drain 7, which face each other with a channel region 8 in between, are formed. Incidentally, the structure of the source N ⁺ impurity diffusion layer the N ^- and and drains of the structure N ^+-called source-drain asymmetry structure as the impurity diffusion layer is surrounded by P ⁺ impurity diffusion layer as to be surrounded by the impurity diffusion layer As a cell, there is a cell in which hot carrier writing in the drain is performed at a sufficiently high speed and punch through is prevented, and the source has a high breakdown voltage structure.

A tunnel oxide film 2 which is a SiO ₂ film having a thickness of about 10 nm is formed on the channel region 8, and a floating gate 3 made of a polysilicon film containing an N-type impurity is formed on the tunnel oxide film 2. . Then, on the floating gate 3, there is an insulating film 4 which is an ONO film having a three-layer structure of, for example, a SiO ₂ film, a Si ₃ N ₄ film and a SiO ₂ film and having a film thickness of about 25 nm in terms of an oxide film. The control gate 5 made of a polysilicon film containing an N-type impurity is formed via the.

Next, the rewriting operation of this flash memory will be described.

First, to write data in the memory cell shown in FIG. 4, V _cg = 12 V, V _d = 6 V, V _s = V _sub
Bias to = 0V respectively. Note that V _cg is a voltage applied to the control gate 5, V _d is a drain voltage, V _s is a source voltage, and V _sub is a substrate potential. Then, the channel region 8
At the same time, electrons of minority carriers are induced to conduct between the source 6 and the drain 7, and the electrons accelerated in the pinch-off region near the drain of the channel region 8 become hot electrons and are injected into the floating gate 3. As a result, excess electrons are accumulated in the floating gate 3, the threshold voltage of the memory cell, which was, for example, about 2V in the initial state immediately after manufacturing or the electrically erased state is changed to about 7V, and the memory cell is programmed. It becomes the state (“1”).

Next, in order to erase the data stored in the memory cell, V _s = 12 V and V _cg = V _sub = 0 V are biased respectively, and V _d is floated (open state). Then, the excess electrons accumulated in the floating gate 3 pass through the tunnel oxide film 2 in the overlapping portion between the source 6 and the floating gate 3 and a current (tunnel current) resulting from the Fowler-Nordheim tunneling phenomenon. Is pulled out to the source 6. As a result, the threshold voltage of the memory cell changes from about 7V to about 2V, and the memory cell enters the erased state (“0”).

Next, in order to read the data stored in the memory cell, V _cg = 5 V, V _d = 1 V, so that hot electron injection into the floating gate 3 does not occur.
Bias to V _s = V _sub = 0V respectively. Then, it is determined whether the memory cell is in the written state or the erased state depending on the presence or absence of the drain current.

FIG. 5 shows that the four memory cells shown in FIG.
FIG. 9 is an equivalent circuit diagram of a memory cell array when connected to an R type. In FIG. 5, the sources of the four memory cells 51 to 54 are connected to a common source line 59. Also,
The drains of the memory cells 51 and 52 are connected to the bit line 55, and the drains of the memory cells 53 and 54 are connected to the bit line 56. In addition, the memory cell 5
The control gates of 1 and 53 are connected to the word line 57, and the control gates of the memory cells 52 and 54 are connected to the word line 58.

Therefore, in FIG. 5, for example, in order to write data in the memory cell 53, the word line 57 has 12 bits.
V, 6V to bit line 56, word line 58 and bit line 55
0 V is applied to the source line 59 and the source line 59, and the substrate is grounded. Further, for example, in order to read the data stored in the memory cell 53, 5V is applied to the word line 57, 1V is applied to the bit line 56, 0V is applied to each of the word line 58, the bit line 55, and the source line 59, and the substrate is applied. Ground.
Further, at the time of erasing, 12V is applied to the source line 59, 0V is applied to each of the word lines 57 and 58, and the bit line 5
Float 5 and 56, respectively, and ground the substrate.
This causes the four memory cells 51-54 to be biased to the same voltage state so that these memory cells 51-54
Are erased all at once.

[0011]

In order to collectively erase the four memory cells 51 to 54 in FIG. 5, the four memory cells 51 to 54 are biased to the same voltage state. The tunnel current density for each of the memory cells 51 to 54 is the variation of the film quality of the tunnel oxide film 2, the variation of the unevenness of the bottom surface of the floating gate 3, the variation of the processed shape of the memory cell, the variation of the voltage value applied to each memory cell. It does not necessarily become a constant value due to such reasons.

This will be described in detail with reference to FIG. FIG. _6A is a graph showing the relationship between the voltage (gate voltage) V _cg applied to the control gate 5 of each memory cell shown in FIG. 4 and the drain current I _d , which is obtained at the rising of the drain current. The gate voltage indicates the threshold voltage of the memory cell. FIG. 6B shows the distribution of threshold voltages in all the memory cells in the written state (“1”) and the erased state (“0”).

As shown in FIG. 6A, in the memory cell of the conventional flash memory, the floating gate 3 is electrically neutral without excess electrons and holes existing immediately after the manufacturing. Threshold voltage of the memory cell in the initial state or the state when ultraviolet erasing is performed (referred to as "neutral state" or "initial" in the present invention) and the threshold in the electrically erased state of the memory cell. The value voltage and the value voltage are equal. For this reason, the problem of excessive erasing of memory cells, which will be described below, has been remarkable.

That is, in the memory cell of the conventional flash memory, since the target threshold voltage after electrical erasing is the same as the threshold voltage in the neutral state, the floating gate 3
From the electron to the source 6, the floating gate 3 reaches a target threshold voltage after electrical erasing in a state where the floating gate 3 is electrically neutral. However, when the bias V _s is further applied to the source 6 in this state, the floating gate 3 is moved to an electrically positively charged state this time, and the impurities in the N-type polysilicon forming the floating gate 3 are changed. , For example, the electron density becomes lower than the donor density initially determined by the chemical composition of phosphorus, that is, the holes become excessive, and finally the holes are determined by the electric field distribution. Saturates at a certain value. As a result, the threshold voltage of the memory cell becomes smaller than the target threshold voltage in the electrically erased state, and in some cases, the threshold voltage is 0 V as shown in FIG. Some memory cells will be below (over-erased state).

The existence of such over-erased memory cells causes the following problems. That is, in the memory cell block shown in FIG. 5, for example, when the memory cell 54 is over-erased, the memory cells 5 located on the same bit line 56 are
When data is written to 3, the selected word line 57 is applied with 12V, the selected bit line 56 is applied with 6V, the non-selected word line 58 is applied with 0V, and the non-selected bit line 55 is applied with 0V. However, at that time, since the threshold voltage of the over-erased memory cell 54 on the selected bit line 56 is 0 V or less, conduction occurs between the source and drain of the memory cell 54 and a current flows. As a result, the potential of the selected bit line 56 drops to 6 V or less, and there is a problem that sufficient writing cannot be performed in the memory cell 53 that needs to be written.

Similarly, when data is read from the memory cells 53 located on the same bit line 56 when the memory cell 54 is in the over-erased state, 5V is applied to the selected word line 57 and 1V is applied to the selected bit line 56. 0V is applied to the selected word line 58, and 0V is applied to the non-selected bit line 55. However, at that time, since the threshold voltage of the over-erased memory cell 54 on the selected bit line 56 is 0 V or less, conduction occurs between the source and drain of the memory cell 54 and a current flows. As a result, it cannot be distinguished which of the memory cell 53 and the memory cell 54 is turned on, and correct reading is impossible.

Therefore, an object of the present invention is to provide a non-volatile semiconductor memory device capable of rewriting and reading data with high reliability without causing a problem of excessive erasing.

[0018]

In order to solve the above problems, according to the present invention, a second conductivity type semiconductor substrate having a pair of first conductivity type impurity diffusion layers opposed to each other across a channel region is formed. In a nonvolatile semiconductor memory device having a floating gate type memory cell in which a first insulating film, a floating gate, a second insulating film and a control gate are sequentially formed on the channel region of The threshold voltage of the memory cell in the state is set to a value between the threshold voltage in the erased state and the threshold voltage in the written state.

In one aspect of the present invention, the threshold voltage of the memory cell when the floating gate is in a neutral state is controlled by introducing a second conductivity type impurity into the channel region.

In one aspect of the present invention, the threshold voltage in the erased state of the memory cell is smaller than the threshold voltage in the written state.

According to one aspect of the present invention, the threshold voltage in the erased state of the memory cell is larger than the threshold voltage in the written state.

[0022]

In the present invention, the threshold voltage of a memory cell when the floating gate is in a neutral state (initial state immediately after manufacturing or ultraviolet erased state) is the same as when the floating gate is in an erased state (that is, an electrically erased state). By setting the value between the threshold voltage and the threshold voltage in the written state, it is possible to rewrite each memory cell without depending so much on the variation of the tunnel current density.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment in which the present invention is applied to a flash memory will be described below with reference to FIGS. The external appearance of the memory cell of the flash memory according to the embodiment of the present invention is substantially the same as the memory cell of the conventional flash memory shown in FIG. 4, and therefore detailed description thereof will be omitted. In the following description, the same reference numerals as those used in FIG. 4 are used to indicate each part of the memory cell. Since the circuit diagram shown in FIG. 5 can be applied to the embodiment of the present invention as it is, FIG. 5 will be used as it is in the following description of the embodiment of the present invention.

First, the characteristics of the memory cells constituting the flash memory of this embodiment will be described with reference to FIG. FIG. 1A is a graph showing the relationship between the gate voltage V _cg and the drain current I _d of the memory cell of the flash memory of the present embodiment. The gate voltage at the rising of the drain current is the threshold voltage of the memory cell. It shows the voltage. FIG.
(B) shows the distribution of the threshold voltage in the write state (“1”) and the erase state (“0”) of the memory cell of the flash memory of this embodiment.

In the flash memory of this embodiment, as shown in FIG.
As shown in (a), the threshold voltage in the written state (“1”) is about 7 V, the threshold voltage in the erased state (“0”) is about 2 V, and the floating gate is in the neutral state (initiated).
The threshold voltage in the case of al) is set to about 4V, respectively. At this time, the threshold voltage in the neutral state is changed to the threshold voltage in the erased state from the viewpoint of preventing the occurrence of over-erased memory cells with high reliability and obtaining a more reliable flash memory. More than 1V higher, and
It is preferably lower than the average value of the threshold voltage in the written state and the threshold voltage in the erased state.

In the flash memory of this embodiment,
In order to set the threshold voltage of the memory cell when the floating gate is in the neutral state as described above, impurities of the same conductivity type as the silicon substrate are introduced at a higher concentration on the surface of the silicon substrate in the channel region of the memory cell. To do. FIG. 2 is a graph showing the impurity concentration profiles in the vicinity of the substrate surface of the memory cells of the flash memory of the present embodiment and the conventional flash memory. The solid line shows the case of the present embodiment and the broken line shows the case of the conventional case. As is clear from FIG. 2, the impurity concentration on the surface of the silicon substrate was about 5.0 × 10 ¹⁶ cm ⁻³ in the past, but in the present embodiment, the impurity concentration on the surface of the silicon substrate is 8.0. It is set to approximately 10 ¹⁶ cm ^-3 . In the case of the present embodiment, as the depth from the surface of the silicon substrate becomes deeper, the impurity concentration gradually decreases while maintaining a slightly higher concentration than before, and the impurity concentration becomes 2.0 or more at a depth of about 3.0 μm or more. It becomes constant at about 10 ¹⁵ cm ^-3 .

FIG. 3 is a block diagram showing the circuit configuration of the flash memory of this embodiment. In FIG. 3, the word lines connected to the control gates of the memory cells forming the memory cell array 31 are connected to the row decoder 32, and the bit lines connected to the drains of the memory cells are connected to the column decoder 33. The source line connected to the source of each memory cell is connected to the source switch 34.

A write voltage generating circuit 35 for generating a voltage applied to the control gate and drain when writing data to the selected memory cell is connected to the row decoder 32 and the column decoder 33. An erase voltage generating circuit 36 that generates a voltage applied to the control gate and the source when erasing the data of the selected memory cell is connected to the row decoder 32 and the source switch 34. A mode control circuit 37 is connected to the write voltage generation circuit 35 and the erase voltage generation circuit 36 to select each of writing, erasing and reading modes according to the mode control signal.

The address buffer 38 is provided in the row decoder 32.
And a column decoder 33, and selects a word line and a bit line according to an input address signal. The sense amplifier 39 connected to the column decoder 33 is
The read result is output to the input / output buffer 40.

In FIG. 3, the row decoder 32, the column decoder 33, and the write voltage generating circuit 35 constitute write voltage applying means. The write voltage generation circuit 35 is
When receiving a write command from the mode control circuit 37, 12V for applying to the control gate of the memory cell
And a voltage of 6V to be applied to the drain. Then, the voltage is applied to the selected memory cell via the row decoder 32 and the column decoder 33 according to the instruction from the address buffer 38. In addition, the row decoder 32, the source switch 34, and the erase voltage generation circuit 36.
Constitutes an erase voltage applying means. When the erase voltage generation circuit 36 receives the erase command from the mode control circuit 37, the erase voltage generation circuit 36 applies 12 V to the source of the memory cell.
Generate the voltage of. Then, the above voltage is applied to the common source line through the source switch 34.

Next, the operation of the memory cell of the flash memory of this embodiment will be described with reference to FIG. Since the write and read operations in this embodiment may be the same as those in the above-mentioned conventional example, detailed description thereof will be omitted, and only the erase operation will be described.

To erase the data stored in the memory cell of the flash memory of this embodiment, V _s = 12V, V
Bias is made to _cg = V _sub = 0V and V _d is made floating (open state). And sauce 6
Electrons are extracted from the floating gate 3 to the source 6 by the tunnel current through the tunnel oxide film 2 in the overlapping portion between the floating gate 3 and the floating gate 3.

At this time, in the memory cell of the present embodiment, the target threshold voltage after electrical erasing is about 2V lower than the threshold voltage in the neutral state, so Fowler-Nordheim is set. Tunneling causes electrons to be drawn from the floating gate to the source, lowering the threshold voltage to the electrically neutral state of the floating gate, then the floating gate transitions to a positively charged state, with hole density When it saturates at a constant value, it just settles at the target threshold voltage, that is, 2V. The positive charge amount in the saturated state, which is determined by this hole density, is
Factors that strongly depend on the initial donor density determined by the impurity density in the floating gate and are dominant in the tunnel current density in the tunnel oxide film (tunnel oxide film quality, unevenness on the bottom surface of the floating gate, variations in memory cell processing shape) , Variation in voltage value applied to each memory cell, etc.). Therefore, as shown in FIG. 1B, the threshold voltage of the memory cell of the flash memory according to the present embodiment after electrical erasure is concentrated in a narrow range centered on 2 V, as shown in FIG. It does not have the wide distribution shown. Also, the problem of overerasure does not occur.

As described above, in the present embodiment, the threshold voltage in the written state ("1") is about 7V,
The threshold voltage in the erased state (“0”) is about 2V,
By setting the threshold voltage in the neutral state (initial) of the floating gate to about 4V, respectively, the threshold voltage in the erased state can be distributed in a narrow range around 2V. Therefore, there is no over-erased memory cell whose threshold voltage is 0 V or less in the erased state,
As a result, for example, in a NOR type memory cell block as shown in FIG. 5, the source-drain of the over-erased memory cell unexpectedly conducts, so that electrons are sufficiently injected into the floating gate of the memory cell to be written. In addition, it does not happen that neither the memory cell to be read or the over-erased memory cell has been turned on and correct reading cannot be performed.

In the flash memory of the above-described embodiment, the threshold voltage in the written state is about 7V, the threshold voltage in the erased state is about 2V, and the threshold voltage in the neutral state of the floating gate is about 4V. However, the present invention is not limited to this, and the threshold voltage in the neutral state is set to a value between the threshold voltage in the erased state and the threshold voltage in the written state. The threshold voltage is 0 V in the erased state
It is possible to significantly reduce the following memory cells in the over-erased state.

Further, in the above embodiment, the state in which the threshold voltage of the memory cell is increased is the write state, and the state in which the threshold voltage is low is the erased state. On the contrary, the state in which the threshold voltage of the memory cell is high is set. May be an erased state, and a state in which the threshold voltage of the memory cell is low may be a written state. In the latter case, “excessive erasing” in this specification may be read as “excessive writing”. Further, data erasing of the memory cell is performed by a gate negative voltage method, for example, V _cg = −8V,
Alternatively, the bias may be applied to V _s = 5V and V _sub = 0V, and V _d may be floating.

Further, in the above-described embodiment, the writing is performed by hot electron injection and the erasing is performed by the Fowler-Nordheim tunneling phenomenon, respectively. However, writing and erasing are performed by hot hole injection and a composite phenomenon of these physical phenomena. However, the present invention is applicable.

[0038]

According to the present invention, the threshold voltage of the memory cell when the floating gate is in the neutral state is between the threshold voltage in the erased state and the threshold voltage in the written state of the memory cell. Since the value is set, the variation in the threshold voltage in the erased state (electrically erased state) can be reduced, and the memory cells in the over-erased state can be significantly reduced. As a result, it is possible to provide a highly reliable rewritable nonvolatile semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a graph showing a rewriting characteristic of a memory cell of a flash memory according to an embodiment of the present invention.

FIG. 2 is a graph showing an impurity concentration profile on a substrate surface of a memory cell of a flash memory according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a circuit configuration of a flash memory according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a structure of a memory cell of a flash memory.

FIG. 5 is an equivalent circuit diagram when four memory cells are connected in a NOR type.

FIG. 6 is a graph showing a rewriting characteristic of a memory cell of a conventional flash memory.

[Explanation of symbols]

 1 P-type silicon substrate 2 Tunnel oxide film 3 Floating gate 4 Insulating film 5 Control gate 6 Source 7 Drain 8 Channel region 31 Memory cell array 32 Row decoder 33 Column decoder 34 Source switch 35 Write voltage generation circuit 36 Erase voltage generation circuit 37 Mode control Circuit 38 Address buffer 39 Sense amplifier 40 Input / output buffer 51, 52, 53, 54 Memory cell 55, 56 Bit line 57, 58 Word line 59 Source line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11C 16/02 16/04 H01L 27/115 H01L 27/10 434

Claims (4)

[Claims] 1. A first insulating film is formed on the channel region of a second conductivity type semiconductor substrate in which a pair of first conductivity type impurity diffusion layers facing each other across a channel region are formed.
In a nonvolatile semiconductor memory device having a floating gate type memory cell in which a floating gate, a second insulating film, and a control gate are sequentially formed, a threshold voltage of the memory cell when the floating gate is in a neutral state is A nonvolatile semiconductor memory device, wherein the memory cell is set to a value between a threshold voltage in an erased state and a threshold voltage in a written state. 2. The threshold voltage of the memory cell when the floating gate is in a neutral state is equal to a second threshold voltage to the channel region.
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is controlled by introducing a conductive impurity. 3. The nonvolatile semiconductor memory device according to claim 1, wherein the threshold voltage of the memory cell in the erased state is smaller than the threshold voltage in the written state. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the threshold voltage of the memory cell in the erased state is higher than the threshold voltage in the written state.