JPH0769400B2 - LSI test method - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention makes it possible to carry out a test for each block by dividing a logic element inside an LSI into a plurality of blocks with a predetermined number of input pins and output pins in common. Regarding the test method of LSI.

[Technical Background of the Invention and Problems Thereof] In recent years, as the integration of LSIs has advanced, the means for testing internal logic elements has become a problem. Conventional LSI in this case
The structure of the internal test circuit is shown in FIG. In the figure, 21 is LS
I and 22 are a plurality of input pins, 23 is the same output pin, 24 is a test dedicated pin, 25 is an input line switching circuit, and 26 is an output line switching circuit. In the test operation in the configuration of FIG. 1, the input line switching circuit 25 and the output line switching circuit 26 are switched and controlled by a signal from the test-dedicated pin 24 to duplicate the input pin 2
2. The output pin 23 is selectively used to input a signal that cannot normally be input or output directly from the outside or directly output to the outside to facilitate the test.

However, in recent years, the scale of LSIs has become larger and the complexity has increased, and along with this, it has become necessary to divide the inside of the LSI into several blocks and perform a test for each block. In order to enable this block-by-block test, it has conventionally been necessary to multiplex (use switching) test pins corresponding to the number of blocks and input pins and output pins. Therefore, conventionally, there has been a problem that the number of test pins is increased and the number of effective signal pins is decreased accordingly, which is a great obstacle to effective utilization of limited pins.

[Object of the Invention] The present invention has been made in view of the above circumstances, and makes it possible to carry out a test for each block by dividing a logic element inside an LSI into a plurality of blocks with a predetermined number of input pins and output pins being common. In an LSI, one test pin is effectively used without increasing the number of test pins, and the limited signal input / output pins are effectively used. Normal mode in /
An object of the present invention is to provide an LSI test method capable of switching test modes and selecting / switching a block under test by selectively connecting a circuit to be tested to the input / output pins.

[Summary of the Invention] The present invention is an LSI in which logical elements inside an LSI are divided into a plurality of blocks with a predetermined number of input pins and output pins in common, and a test can be performed for each block. Test pins, an internal block designation counter, a normal mode / test mode switching gate for selectively enabling the output of this counter, and any one block selectively between the I / O pins And a selection circuit connected to the circuit. The counter is controlled by one test pin to select and switch the block to be tested, and the gate is controlled to selectively output the counter. With this configuration, the test operation is performed in block units inside the LSI by effectively using only one test pin without increasing the number of test pins. Can be implemented efficiently.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the present invention. Here, the internal logic element of the LSI is divided into four blocks into four blocks, and the configuration is shown as an example in which the input pins and the output pins are quadrupled to facilitate the test. 1 in the figure
Is an LSI, 2 is a plurality of input pins, 3 is also a plurality of output pins, 4 is a clear pin for initializing a predetermined circuit in the LSI, and 5 is only one test pin. Reference numeral 6 is a counter for designating a clock which is initialized by the clear signal of the clear pin 4 and counts up at the falling edge (“true” → “false”) of the test signal of the test pin 5, and here is a block to be selected. Since there are four, there are 2 bits. A decoder 7 decodes the output of the counter 6. Reference numeral 8 is a gate which controls the output of the decoder 7, and makes the output signal of the decoder 7 valid while the test signal of the test pin 5 is "true". Reference numeral 9 is a block selection line that supplies an output signal of the decoder 7 via the gate 8 as a block designation signal to an input line selection circuit 10 and an output line selection circuit 11 which will be described later. Reference numeral 10 indicates that the signal between the input pin 2 and the corresponding block is received in response to the selection signal “true” of the corresponding block selection line 9 in the test mode (when the signal on the test pin 5 is “true”). Selectively connect the circuit,
During other normal operation (the signal on test pin 5 is "false")
Is the input line selection circuit which receives the selection signal "true" common to all blocks on the input / output signal selection line 12 and circuit-connects between the input pin 2 and all blocks. . The reference numeral 11 receives the selection signal “true” from the corresponding block selection line 9 in the test mode to selectively connect the circuit between the corresponding block and the output pin 3; The output line selection circuit receives the selection signal “true” common to all the blocks on the output signal selection line 12 and circuit-connects all the blocks and the output pin 3. An input / output signal selection line 12 inverts the signal on the test pin 5 and supplies it as an input / output selection signal common to all blocks in the normal operation mode to the input line selection circuit 10 and the output line selection circuit 11. Is. Reference numeral 13 is a block obtained by dividing logical elements inside the LSI, and is divided into four blocks here.

Here, the test operation in one embodiment will be described. First, the counter 6 is initialized by supplying a clear signal to the clear pin 4. Next, when a clock signal for block selection is supplied to the test pin 5, the counter 6 is updated and controlled according to the fall of the signal (“true” → “false”). In this way, by supplying the test signal to the test pin 5 as the counter clock, the counter 6
Can be set to any value. The output of the counter 6 is decoded by the decoder 7. That is, if the output of the counter 6 is “false” for both 2 bits of MSB and LSB, block 0, if MSB is “false” and LSB is “true”, block 1, MS
If B is "true" and LSB is "false", block 2, MSB, LSB
If both of the 2 bits are true, the selection signal of block 3 is output.

Next, by supplying a signal of "true" value indicating the test mode to the test pin 5, the gate 8 is opened for the period of the test signal of "true" value, and the signal output from the decoder 7 is output. Input line selection circuit 1 via block selection line 9
0, and is supplied to the output line selection circuit 11, of which
Only the selection circuit receiving the "true" value signal is selectively brought into the circuit connection state, and the corresponding block is connected as a test target between the input pin 2 and the output pin 3. That is, the output of the counter 6 is “false” for both 2 bits of MSB and LSB.
, The output of the decoder 7 causes block 0
Is selectively connected between the input pin 2 and the output pin 3 as a test target, and when the MSB is "false" and the LSB is "true", the block 1 is selectively input in the same manner as above. Circuit is connected between pin 2 and output pin 3, MSB is "true", LSB
Is "false", the block 2 is selectively connected between the input pin 2 and the output pin 3 in the same manner as above, and the MS
When both 2 bits of B and LSB are "true", the block 3 is selectively connected between the input pin 2 and the output pin 3 in the same manner as above. In this way, after the block to be tested is connected between the input pin 2 and the output pin 3,
An input signal for testing the block is applied to the input pin 2, and the result is output from the output pin 3. When the test of one block is completed, first, the test signal on the test pin 5 is set to "false" and the clear pin 4
A clear signal is supplied to the counter 6 to initialize the counter 6. Then, by supplying the "true" test signal again, the next block can be continuously tested. That is, by setting the test signal on the test pin 5 to "false" at the end of the test, the counter 6 is counted up at the falling timing of this signal and becomes the "true" value again. A block is opened and a block according to the count value of the counter 6 is selected, and the block can be tested. By repeating this, the blocks to be tested can be sequentially and continuously switched only by interrupting the signal supplied to the test pin 5.

On the other hand, when the signal on the test pin 5 remains in the "false" state, the gate 8 is closed and instead the input output signal select line
The signal on 12 has a "true" value, and all blocks are commonly connected to the input pin 2 and the output pin 3 and the normal operation mode (normal mode) is set.

In this way, with only one test pin, the input pin and the output pin can be multiplexed to test each divided block in the LSI, without reducing the number of effective signal pins for normal operation. The block unit test can be performed efficiently and quickly.

As described above in detail, according to the LSI test method of the present invention, L
In an LSI that allows logical elements inside the SI to be divided into multiple blocks with a predetermined number of input pins and output pins in common, and test can be performed for each block, one test pin and an internal block designation counter A normal mode / test mode switching gate for selectively enabling the output of the counter, and a selection circuit for selectively circuit-connecting any one block between the input / output pins. , A test pin is controlled by a single test pin to select and switch a block to be tested, and a gate is controlled to selectively enable the output of the counter. The test operation of each block inside the LSI can be efficiently performed by effectively using only one test pin without causing an increase in the number of pins.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional LSI internal test mechanism. 1 ... LSI, 2 ... input pin, 3 ... output pin, 4 ...
Clear pin, 5 ... Test pin, 6 ... Counter, 7 ...
Decoder, 8 ... Gate, 9 ... Block selection line, 10
...... Input line selection circuit, 11 …… Output line selection circuit, 12 …… Input output signal selection line, 13 …… Block.

Claims (1)

[Claims] 1. An LSI in which a logic element inside an LSI is divided into a plurality of blocks with a predetermined number of input pins and output pins in common, and a test can be performed for each block.
The test pin provided on SI, the block designating counter that is controlled by receiving the logic signal input from the above test pin, and the output of this counter are valid only when the signal on the above test pin is in a specific state. Selection circuit that selects one of the plurality of blocks according to the gate to be activated and the output value of the counter validated by the gate, and enables input / output of a signal via the input pin and the output pin of the block. An LSI characterized by comprising:
Test method.