JPH0767072A - Digital video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To decrease circuit scale while maintaining the high picture quality of a reproduction picture, and to data-compress and record/reproduce a video signal. CONSTITUTION:An odd-numbered frame is written in a frame memory 12, and an even-numbered frame is written in a frame memory 13, and the odd-numbered frame and the even-numbered frame are alternately read from those memories. The even-numbered frame read from the frame memory 13 is supplied to a subtracting circuit 16, and converted into inter-motion compensated frame predictive error data by movement compensation predictive data generated by a movement compensating circuit 15 by using the frame stored in the frame memory 12. The picture data of the odd-numbered frame from the frame memory 12 and the inter-motion compensated frame predictive data of the even-numbered frame from the subtracting circuit 16 are data-compressed and converted into compressed data by a DCT circuit 18, feedforward type quantizing circuit 21 under information amount control, and variable length encoding circuit 22, and recorded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal recording / reproducing apparatus for compressing a video signal and recording it on a data recording medium, and more particularly to recording / reproducing a video signal having a small circuit scale and high image quality. The present invention relates to a realized digital video signal recording / reproducing device.

[0002]

2. Description of the Related Art As a digital video signal recording / reproducing apparatus for compressing a video signal and recording it on a magnetic tape, for example, "Signal Processing: Image Communication" Vo
A digital VTR described in L. 4, Nos. 4-5 (August 1992), pp. 401-420 is known. This digital VTR
Is a method for compressing a European HDTV signal (high-definition television signal), recording it on a magnetic tape, reproducing the compressed data recorded, and expanding the data to obtain a reproduced video signal.

That is, first, when recording a video signal,
The analog input video signal is A / D converted, and the obtained digital image data is data-compressed in units of two frames. In the odd frame of the two frames, the discrete cosine transform (D
CT), quantization, and variable-length coding to perform image coding processing to generate compressed data. This method is called intra-coding, and redundancy can be reduced in the two-dimensional space, so that data compression is realized. For odd-numbered frames, in addition to such image coding processing, local decoding processing including inverse quantization and inverse DCT is performed to decode compressed data, and reproduced image data obtained when the compressed data is reproduced. Is generated and stored in the local frame memory.

In the even-numbered frame of the two frames, the motion-compensated inter-frame prediction error data generated from the image data of the even-numbered frame to be encoded and the reproduced image data of the odd-numbered frame held in the local frame memory , 8 × 8 pixels are used as a block unit to perform coding processing including DCT, quantization, and variable length coding to generate compressed data. Here, the motion-compensated inter-frame prediction detects a motion vector representing a motion between the previous frame and the current frame in block units, and predicts the predicted value of the image data of the current frame in the previous frame in block units. It is a process of generating image data by shifting the image data according to the detected motion vector. This method is called inter-encoding and can reduce the redundancy in the time direction, so that the data compression rate can be improved.

The image data generated as described above is added with an error correction code, modulated and recorded on a magnetic tape. When the rotary head scans the magnetic tape helically, a video signal of image data is recorded on a track obliquely formed on the magnetic tape.

Upon reproduction, the video signal reproduced from the magnetic tape is demodulated and then subjected to error detection and error correction processing when an error occurs using an error correction code to reproduce compressed data. In the odd-numbered frame of the above-mentioned two frames, the compressed data is subjected to data decompression by an image decoding process including variable length decoding, inverse quantization and inverse DCT, thereby generating reproduced image data. It is temporarily stored in the frame memory. In the even frames of the above-mentioned two frames, the same image decoding process is performed on the compressed data to reproduce the motion compensation inter-frame prediction error data. Then, the reproduced image data of the odd-numbered frames stored in the frame memory is motion-compensated and added to this motion-compensated inter-frame prediction error data,
As a result, reproduced image data of even frames is generated. The digital reproduction image data thus generated is converted into an analog video signal by D / A conversion and output.

The information amount originally possessed by the image data changes according to the variation of the picture pattern for each frame and each partial area in the frame. Therefore, in order to record compressed data on a magnetic tape in which the amount of recorded data per unit time is constant,
The fineness of the quantization in the quantization processing is controlled, and the information amount control is performed to make the compressed data amount constant in a predetermined unit.

It should be noted that, as described above, the quantization in the even frame which compresses the motion compensation inter-frame prediction error data can be generally coarser than that in the odd frame which compresses the image data itself. it can. As a result, the compressed data amount of the inter-coded even-numbered frame is usually 1/3 or less of the compressed data amount of the intra-coded odd-numbered frame.

The above-mentioned prior art is a motion-compensated frame prediction D used for communication of videophones and videoconferences.
The CT coding system (called MC-DCT coding system) is applied to a digital video signal recording / reproducing apparatus. For communication, the first frame is intra-coded, and the subsequent frames are basically inter-coded.However, in the above-mentioned conventional technique, an odd-numbered frame is intra-coded and an even-numbered frame is inter-coded. The feature is that MC-DCT encoding is completed in units of two frames. This allows the digital VT
Functions such as editing and special playback required by R are realized.

[0010]

However, in the above-mentioned conventional digital video recording / reproducing apparatus, both the image coding processing circuit for performing DCT and quantization and the image decoding processing circuit for performing inverse quantization and inverse DCT are used. Therefore, there is a problem that it is difficult to reduce the cost because the circuit scale becomes large because it must be provided. This is because it is necessary to simultaneously operate not only the image coding processing circuit that performs the image coding processing but also the image decoding processing circuit that performs the local decoding processing when recording the video signal.

An object of the present invention is to solve the above problems and to provide a digital video signal recording / reproducing apparatus having a relatively small circuit scale and capable of recording / reproducing a high quality video signal. is there.

[0012]

In order to achieve the above object, in the present invention, an image data storage means having a capacity of one screen or more for storing input image data, is provided as a video signal recording system circuit, and Prediction error data generation means for generating inter-screen prediction error data from image data and the image data held in the image data storage means, output image data of the image data storage means, and output from the prediction error data generation means And an image coding means for compressing the inter-frame prediction error data.

[0013]

The input image data of the selected specific screen is stored in the image data storage means and is intra-coded by the image coding means. For the input image data of the other screens, the prediction error data generation unit generates inter-screen prediction error data from the input image data of the specific screen held in the image data storage unit, and the inter-screen prediction error data is generated. The prediction error data is inter-coded by the image coding means.

Therefore, since the local decoding means required in the past is unnecessary, the circuit scale can be reduced as compared with the prior art. Further, since the image encoding means in the recording system circuit and the image decoding means in the reproduction system circuit have high symmetry, it is easy to realize the commonality of the circuits in both circuits.

The selected specific screen is data-compressed while maintaining high image quality by intra-coding, and the other screens are data-compressed by inter-coding having a high data compression rate, so that the average data compression rate becomes high and Therefore, it is possible to realize recording and reproduction of high-quality video signals.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a recording system circuit in a first embodiment of a digital video signal recording / reproducing apparatus according to the present invention, in which 1 is a video signal input terminal, 2 is an A / D conversion circuit,
3 is an image encoding circuit, 4 is a correction encoding circuit, 5 is a modulation recording circuit, 6 is a recording magnetic head, 7 is a magnetic tape, 11 is a selection circuit, 12 and 13 are frame memories, 14 is a motion vector detection circuit, Reference numeral 15 is a motion compensation circuit, 16 is a subtraction circuit, 17 is a selection circuit, 18 is a DCT circuit, 19 is a delay circuit, 20 is an information amount control circuit, 21 is a quantization circuit, 22 is a variable length coding circuit, and 23 is a buffer. The memory 24 is a vector memory.

First, the recording system circuit of the first embodiment will be described with reference to FIG.

From the input terminal 1, a three-component analog video signal composed of a luminance signal and two types of color difference signals is input. Here, this video signal is a Japanese type HDTV signal, and the number of lines per screen (frame) is 1125 and the number of frames per second is 30. The number of valid display lines is 1035. In display scanning, the scanning position is sequentially changed from top to bottom while horizontally scanning from left to right toward the screen. However, in the case of interlaced scanning, one frame consists of an odd field and an even field transmitted subsequently to this. The odd field is composed of the odd-numbered 562.5 lines of the 1125 lines constituting the screen, and the even field is composed of the even-numbered 562.5 lines.

The input analog video signal is A /
The D signal is supplied to the D conversion circuit 2, and the luminance signal and the two types of color difference signals are converted into digital image data. Here, the sampling frequency of the luminance signal is 44.55 MHz, and the sampling frequency of each of the two types of color difference signals is 1/2 of that.
22.275 MHz, which is double. As a result, the number of effective display horizontal pixels in the luminance signal is 1152, and the number of effective display horizontal pixels in the two types of color difference signals is 1 /
It doubles to 576.

The image data generated by the A / D conversion circuit 2 is compressed by the image coding circuit 3 by the MC-DCT coding method of two-frame completion, which will be described in detail later, to generate compressed data. It The compressed data output from the image encoding circuit 3 is output by the correction encoding circuit 4 to
An error correction code based on the Reed-Solomon product code is added to generate data to be recorded on the magnetic tape 7. Here, the addition of the error correction code will be described.

First, a data string of compressed data divided into predetermined sizes is vertically stacked to generate a two-dimensional array structure, and outer code parity is added in the vertical direction by Reed-Solomon coding, and the horizontal direction is also added. As for, the inner code parity is added by Reed-Solomon coding. Synchronous data and ID data are added to the head of the compressed data (or the outer code parity) and the inner code parity added to the compressed data to form a synchronous block. This synchronization block serves as a basic unit of data recorded / reproduced on / from the magnetic tape 7. The synchronization data is a special bit pattern used to synchronize reproduction when reading data from the magnetic tape 7 in synchronization block units. The ID data is attribute data indicating the number of the sync block and the like.

The compressed data to which the error correction code has been added by the correction coding circuit 4 is converted into a signal format suitable for recording / reproduction on the magnetic tape 7 by the modulation recording circuit 5 and is amplified.
It is supplied to the recording magnetic head 6 and recorded on the magnetic tape 7.

Similar to the current analog VTR, the recording magnetic head 6 is mounted on a rotating cylinder (not shown), and the magnetic tape 7 running obliquely wound around the rotating cylinder is helically scanned to record data. Therefore, data is recorded on the magnetic tape 7 in track units having a predetermined inclination. Incidentally, on each track, an integer number of synchronization blocks generated by the correction encoding circuit 4 are recorded.

Next, the image coding circuit 3 will be described.

The image data supplied from the A / D conversion circuit 2 is distributed by the selection circuit 11 in units of one frame, and the frame memory 12 stores the image data of the odd frames and the frame memory 13 stores the image data of the even frames. Retained. Since the image data is supplied in the order of lines displayed by interlaced scanning, the image data of the first field forming one frame is written in the odd lines in these frame memories, and the image data of the second field forming one frame is written. The image data is written to even lines in these frame memories. This translates the data order from field to frame.

However, the number of lines per frame stored in these frame memories is 1 for the luminance signal.
040 lines, and 1 for two types of color difference signals
Since the data is thinned out every line and stored, it is 520 lines which is 1/2 times as large as that in the case of the luminance signal. The image data stored and held in the frame memories 12 and 13 is necessary for subsequent image coding processing, and the image data written in each of them is held for at least two frame periods after the writing is completed. Therefore, each of the frame memories 12 and 13 has a two-sided structure, and the side to be used is switched every two frames.

In the frame period in which the image data of the odd-numbered frame is supplied, the selection circuit 11 selects the frame memory 12 and writes the odd-numbered frame on one surface of the frame memory 12. The written odd-numbered frame image data is held for the next three frame periods. While this writing is being performed, at the same time, the image data of the frame two frames before, which was stored and held in another surface of the frame memory 12, is read out, and the selection circuit 17 outputs this image data to the intra. The signal is supplied to the DCT circuit 18 for encoding processing. Here, the reading of the image data from the frame memory 12 is performed based on a predetermined pattern.
This is performed by sequentially selecting blocks of 8 × 8 pixels located at distant positions in the frame and sequentially scanning the image data of each pixel in the block in a predetermined order. As a result, the shuffling process is performed in block units based on the predetermined shuffling pattern.

In the frame period in which the image data of the even frame is supplied, the selection circuit 11 selects the frame memory 13 and writes the even frame on one surface of the frame memory 13. The written even-numbered frame image data is continuously held for three frame periods. While this writing is being performed, at the same time, the image data of the frame two frames before the period stored and held in another surface of the frame memory 13 is read out, and the subtraction circuit 16
Is supplied to. Further, the same odd-numbered frame image data as described above is read again from the frame memory 12, supplied to the motion compensation circuit 15 to generate motion compensation prediction data, and supplied to the subtraction circuit 16. In the subtraction circuit 16, the difference between the even-numbered frame image data read from the frame memory 13 and this motion compensation prediction data is calculated to generate motion compensation inter-frame prediction error data.
The selection circuit 17 supplies the motion compensation inter-frame prediction error data from the subtraction circuit 16 to the DCT circuit 18 in order to perform the inter coding process. When reading the image data from the frame memory 13, the shuffling process is performed in block units based on the shuffling pattern, as in the case of reading the image data from the frame memory 12 described above.

When the even-numbered frame image data is written in the frame memory 13, the even-numbered frame image data is written in the frame memory 1 in the next frame period.
3 and is supplied to the motion vector detection circuit 14. At the same time, the image data of the odd-numbered frame, which is the immediately preceding frame, is read from the frame memory 12 and is also supplied to the motion vector detection circuit 14. In the motion vector detection circuit 14, the frame memory 1
The even-numbered frame supplied from No. 3 is divided as a current frame into block units of 8 × 8 pixels, and the frame memory 12 that becomes the previous frame with respect to this even-numbered frame
A block matching process is performed with the image data of the odd-numbered frames from (3) to detect a motion vector. That is, the shift amount of the block position required to extract the block having the highest degree of approximation with respect to each block of the even frame from the odd frame is set as the motion vector of each block. The detected motion vector of each block of the even frame is written in the vector memory 24.

Then, in the next frame period, the image data of the even frame is read out from the frame memory 13 again and supplied to the subtraction circuit 16. Further, in this frame period, the motion vectors of the respective blocks of the even frame written in the vector memory 24 are sequentially based on the same shuffling pattern as in the case of reading the image data from the frame memories 12 and 13 described above. It is read out and supplied to the motion compensation circuit 15. Motion compensation circuit 1
5, the image data of the above-mentioned odd frame which is the previous frame read out again from the frame memory 12 is supplied, and the position of each block of the even frame and the motion vector corresponding thereto are supplied to determine the predetermined number of the odd frame in block units. The image data at the position is read out and used as motion compensation prediction data. This motion-compensated prediction data is supplied to the subtraction circuit 16 to generate motion-compensated inter-frame prediction error data for each block of even frames.

Select circuit 1 in the frame period of an odd frame
The image data output from the frame memory 12 and the motion compensation inter-frame prediction error data output from the subtraction circuit 16 from the selection circuit 17 during the frame period of the even frame are subjected to data compression processing in block units. Although this data compression processing will be described below, since the same processing is performed for image data and motion compensation inter-frame prediction error data, they will be generically referred to as image data in the following description.

The image data from the selection circuit 17 is DC
The signal is supplied to the T circuit 18 and a two-dimensional discrete cosine transform (DCT) is performed in a block unit of 8 × 8 pixels. The DCT performs frequency analysis similarly to the Fourier transform, and the 64 transform coefficients after the DCT correspond to the average value of the image data in the block D.
AC (alternating current) showing various frequency components with C (direct current) coefficient
It consists of a coefficient and.

2 × 2 of the image data of the luminance signal
A total of 6 blocks consisting of 4 blocks and 1 block of image data of two kinds of color difference signals that occupy the same screen position as those are treated as one group, which is called a macro block. The number of pixels of one frame to be coded is 1152 horizontal with respect to the luminance signal.
Since there are pixels × vertical 1040 pixels, the number of macroblocks forming one frame is 72 horizontal × 65 vertical macroblocks, that is, 4680 macroblocks.

The transform coefficient output from the DCT circuit 18 is supplied to the information amount control circuit 20, and 4680 macroblocks forming one frame are divided into 390 compressed blocks each including 12 macroblocks in an odd frame, and even frames are added. Then, each is divided into 130 compressed blocks consisting of 36 macroblocks, and the quantization parameter is generated in such a compressed block unit so that the data amount of the compressed data becomes constant. Here, the quantization parameter is a parameter that specifies the fineness of quantization when the transform circuit that is the output of the DCT circuit 18 is quantized by the quantization circuit 21. The information amount control circuit 20 performs feed-forward type information amount control, and determines how much information amount is generated when transform coefficient quantization and variable length coding are performed by a predetermined quantization parameter. A plurality of counting circuits for counting are provided, and a value of a quantization parameter that is closest to or less than a predetermined target data amount is selected for each compression block.

It should be noted that the activity of the conversion coefficient is detected in block units, and classification into four classes is performed according to the value of the activity. The same quantization parameter is generated for all blocks that make up a compressed block, but the degree of detail for quantizing the transform coefficient of a block in accordance with the class information determined from the value of the activity of the block is somewhat small. It is variable. Here, the activity of the block is an index indicating whether the amount of information originally possessed by the image data is large or small due to a thin pattern, a large movement, or a deformed object. In the embodiment, the maximum absolute value of the AC coefficient in the block is used.

The transform coefficient output from the DCT circuit 18 is delay-compensated by the delay circuit 19 at the time when the quantization parameter of the compressed block is generated by the information amount control circuit 20, and then the quantization circuit. 21.

In the quantizing circuit 21, the delay circuit 19 is responsive to the quantization parameter for each compressed block and the class information for each block supplied from the information amount control circuit 20.
The transform coefficients of each block supplied via the are quantized. When quantizing the transform coefficient of the odd-numbered frame image data, the low-frequency AC is considered in consideration of human visual characteristics that the detection sensitivity is lower for high-frequency information than for low-frequency information. Weighted quantization is performed so that the coefficient is quantized relatively finer than the high frequency AC coefficient. However, the fineness of the quantization of the DC coefficient is always constant. On the other hand, when quantizing the transform coefficients of the motion-compensated inter-frame prediction error data of even frames, uniform quantization is performed so that all transform coefficients are quantized with the same fineness. Also, the transform coefficients of blocks belonging to a class with small activity are finely quantized, and the transform coefficients of blocks belonging to a class with large activity are roughly quantized.

The quantized transform coefficient output from the quantization circuit 21 is supplied to the variable length coding circuit 22. In the variable length coding circuit 22, such transform coefficients are scanned from a low frequency to a high frequency in a predetermined order, and the number of consecutive conversion coefficients having a value of 0 (run length) and a conversion coefficient having a value other than 0 are obtained. A pair of values (levels) is generated, and the pair is Huffman-encoded into a variable length code according to a predetermined encoding table. A code with a short code length is assigned to a pair with a high probability of occurrence, a short run length, and a low level,
Conversely, a code having a long code length is assigned to a pair having a long run length or a high level. However, only the DC coefficient of the image data of the odd-numbered frame is special and fixed-length coded with a predetermined code length.

The compressed data which is compressed by the variable length coding circuit 22 and output as described above is supplied to the buffer memory 23. Further, as additional information of this, a quantization parameter for each compressed block, class information of each block, and in the case of an even frame, a motion vector of each block is supplied to the buffer memory 23, respectively.

The buffer memory 23 has a predetermined size so that the compressed data output from the variable length coding circuit 22 is stored in a predetermined number of sync blocks recorded on the tracks of the magnetic tape 7 in units of compressed blocks. The data is rearranged according to the rules and supplied to the correction coding circuit 4.

FIG. 2 is an explanatory view showing the recording format of the compressed data in the first embodiment.

As shown in FIG. 2A, compressed data for odd-numbered frame image data, that is, intra-coded data is recorded in 30 tracks, and compressed data for motion-compensated inter-frame prediction error data for the next even-numbered frame. That is, the inter-coded data is recorded in the 10 tracks following this. That is, two frames of compressed data are recorded on 40 tracks. In addition, 13 blocks of compressed data are recorded per track.

The manner in which the compressed data of each compressed block controlled to have a constant data amount is stored in a predetermined number of synchronous blocks is shown in FIGS. 2B and 2C, which is called packing processing. FIG. 2B shows compressed data of odd frames,
That is, FIG. 2C shows the packing process of intra-coded data, and FIG. 2C shows the packing process of even-frame compressed data, that is, inter-coded data.

To each sync block, sync data SYNC and ID data are added before the compressed data, and inner code parity ECC is added after the sync data. At the time of reproduction from the magnetic tape 7, the data is read out and demodulated in synchronization block units, and thereafter, error correction is performed. If the tape reproduction condition is not good during normal reproduction, an error may remain in the compressed data. Also, during high-speed search reproduction in which the magnetic tape 7 is run at a higher speed than in normal reproduction to reproduce an image, the reproducing magnetic head does not trace the track accurately, but crosses the track diagonally. Only part of the recorded sync block can be played back. In general, if one part of the variable-length coded data is erroneous or missing due to the above reasons, it becomes impossible to decode the variable-length coded data after that. Will continue to propagate after that.

Therefore, in order to suppress such error propagation to be short, in the buffer memory 23, as shown in FIG. 2B, one intra-coded data of one compressed block consisting of 12 macroblocks has 12 sync blocks. Packed in. Each sync block corresponds to one macro block. That is, the compressed data in the sync block formed by the correction coding circuit 4 is set to one macro block.

In FIG. 2 (b), each area delimited by a horizontal line is a sync block, and sync data SYNC and ID data are added to the head of each sync block.
An inner code parity ECC is added to the terminal part. An area between the ID data and the inner code parity ECC is a macroblock storage area in which the compressed data MB1, MB2, ... Of the macroblock are stored.

In the macroblock storage area of each synchronization block, quantization parameters for the entire compressed block,
The class information of each of the six blocks forming the macroblock stored therein and the DC coefficient of each block are stored, and following these fixed-length encoded data, the macroblock in this macroblock is stored. The AC coefficients of each variable-length coded block are stored in order from the lowest frequency to the highest frequency. This means that the compressed data is rearranged in the order of importance from the most important data to the least important data.

By the way, although the amount of compressed data for each compressed block is controlled to be constant, the amount of compressed data for each macroblock varies. Therefore, of the compressed data MB1, MB2, ... Of each macroblock, for example, the compressed data MB1 of the first macroblock
When is stored in the corresponding macro block storage area of the synchronous block, the amount of data is small, so there is a free area in this macro block storage area.
When the compressed data MB3 of the third macroblock is to be stored in the macroblock storage area of the corresponding sync block, the amount of data is so large that it may not be completely filled.

Therefore, the end portion of the compressed data MB3 thus protruding is stored in the empty area remaining in the other macroblock storage area. In FIG. 2B, an empty area is created in the macroblock storage areas of the macroblock compressed data MB1 and MB2, and the macroblock compressed data MB1.
3 and MB4 indicate the case where the macro block storage area cannot be filled, and as indicated by the arrow, the compressed data MB3
And a part of the end portion of MB4 are stored in the free space of the macroblock storage area of the compressed data MB1 of the macroblock, and the rest of the tail portion of the compressed data MB4 is stored in the macroblock of the compressed data MB2 of the macroblock. It is stored in the free area of the area.

The macroblock MB is a concatenated address that indicates in which macroblock storage area the end portion of the compressed data MB3 and MB4 is stored.
It is stored as additional information in the macroblock storage area corresponding to 3, MB4.

As described above, the inner code parity ECC is added to the end of the packed intra-coded data. As a result, even if an error occurs in the middle of the synchronization block and correction cannot be completed, data with higher importance before the error can be decoded, and error propagation ends within that macroblock. However, it does not propagate to other macroblocks. Further, even when only a part of the sync blocks are read out as in the high speed search reproduction, the macro blocks of the reproduced sync blocks can be decoded, and the image reproduction of a part of the screen can be performed.

In the buffer memory 23, 36
Inter-coded data of a compressed block composed of macroblocks is also packed into 12 sync blocks, as shown in FIG. Therefore, three macroblocks are stored in each synchronization block.

The synchronization data S at the beginning is included in each synchronization block.
After the YNC and ID data, the quantization parameter for the entire compressed block is stored, then there is a storage area for storing the inter-coded data, and the inner code parity ECC is added at the end. The storage area of the inter-coded data of each synchronization block is divided into three macroblock storage areas of equal size, and in each macroblock storage area, class information of each of the six blocks forming the macroblock and The motion vector information of the block is stored, and subsequently, the transform coefficients of each block in the variable-length coded macroblock are stored in the order from the lowest-frequency transform coefficient to the highest-frequency transform coefficient. .
In FIG. 2C, for example, compressed data of three macroblocks stored in the first synchronization block is represented by mb1 and mb.
2 and mb3, it is shown that compressed data of three macro blocks is stored in each synchronous block.

Even in this case, there is a variation in the compressed data amount of the compressed data of each macroblock as shown in FIG. 2 (b).
This is the same as the case of packing the intra-coded data shown in. Therefore, the tail portion of the compressed data of the macro blocks that cannot be stored in each macro block storage area is stored in the free area remaining in the other macro block storage areas. In FIG. 2C, as indicated by the arrow, the end portion of the compressed data mb4 of the macroblock is in the free space of the macroblock of the compressed data mb2 of the macroblock, and the end portion of the compressed data mb3 of the macroblock is the macroblock. The compressed data mb6 are stored in the empty areas of the macro blocks. Even in this case, a concatenated address indicating at which position of which synchronization block the tail portion is stored is recorded as additional information in the macroblock storage area corresponding to the macroblock.

By packing the inter-coded data as described above, even if an error occurs in the middle of the synchronization block and correction cannot be completed, the data of higher importance before the error can be decoded. And the effect of the error does not propagate to other macroblocks.

FIG. 3 is a block diagram showing a reproducing system circuit for the recording system circuit shown in FIG. 1. 25 is a reproducing magnetic head, 26 is a reproducing demodulating circuit, 27 is an error correcting circuit, 28 is an image decoding circuit, 29 is a D / A conversion circuit, 30 is an output terminal for a reproduced video signal, 31 is a buffer memory, 32 is a variable length decoding circuit, 33 is an inverse quantization circuit, 34 is an inverse DCT circuit, 35 is a selection circuit, and 36 is An adder circuit, 37 is a motion compensation circuit, 38 and 39 are frame memories, and 40 is a selection circuit.

In the same figure, the reproducing magnetic head 25 helically scans the magnetic tape 7 recorded as described above in the same manner as the recording magnetic head 6, and data reproduction is performed. The reproduction signal from the magnetic tape 7 is reproduced and demodulated by the reproduction demodulation circuit 2.
6, the waveform is equalized to compensate the recording / reproducing characteristics of the magnetic tape 7, and demodulated into digital signals of "0" and "1".

The demodulated digital signal output from the reproduction demodulation circuit 26 is supplied to the error correction circuit 27, and the sync data of a special bit pattern added to the head of the sync block is detected, whereby the data is converted in sync block units. Reproduced, error detection and random error correction are performed using the inner code parity, and output as error-corrected compressed data. Further, when a burst error or a large number of random errors occur, further, after the data of the synchronization block made up of the outer code parity is reproduced, the outer code parity is used for error correction to obtain compressed data. Is output. If an uncorrectable error still remains, error position data indicating the error position is output at the same time as the compressed data.

The compressed data output from the error correction circuit 27 is processed by the image decoding circuit 28 in the image coding circuit 3 (FIG. 1).
By performing the processing opposite to that, the data is expanded and reproduced as image data. However, if there is an error that cannot be corrected by the error correction circuit 27 as described above,
The compressed data of the portion indicated by the error position data supplied from the error correction circuit 27 is not decoded. Therefore, the image data corresponding to the compressed data of that portion is replaced with the image data of the same screen position before that. Due to such concealment processing, the quality of the reproduced image is not significantly deteriorated.

The digital image data reproduced from the image decoding circuit 28 is converted into three kinds of analog video signals by the D / A conversion circuit 29. Then, the output terminal 30 outputs a three-component video signal including a luminance signal and two types of color difference signals.

Next, the image decoding circuit 28 in FIG. 3 will be described.

The compressed data, which has been error-corrected in synchronization block units, from the error correction circuit 27 is temporarily stored in the buffer memory 3.
Stored in 1. In the buffer memory 31, FIG.
As shown in (b) and (c), the intra-coded data and inter-coded data packed for each macroblock are rearranged in the original order, and the variable-length coded transform coefficients of each block are The variable length decoding circuit 32 is output in block units, and the quantization parameter, class information, and motion vector are also separated and output.

The variable length decoding circuit 32 performs a process reverse to that of the variable length coding circuit 22 in the image coding circuit 3 in FIG. That is, the Huffman-encoded variable length code is decoded according to a predetermined encoding table, a run length and level pair is generated, and the value of the quantized transform coefficient is restored. The combination of the variable length coding process and the variable length decoding process is reversible.

The quantized transform coefficient from the variable length decoding circuit 32 is supplied to the inverse quantization circuit 33, and the buffer memory 31.
In accordance with the quantization parameter and the class information supplied from, the processing opposite to that of the quantization circuit 21 in the image coding circuit 3 in FIG. 1 is performed and the value of the transform coefficient is restored. Since the combination of the quantization process and the inverse quantization process is irreversible, some coding distortion is mixed in the restored transform coefficient.

The transform coefficient output from the inverse quantization circuit 33 is supplied to the inverse DCT circuit 34, and the process is the reverse of that of the DCT circuit 18 in the image coding circuit 3 in FIG. 1, that is, the restored transform coefficient. On the other hand, two-dimensional inverse discrete cosine transform (inverse DCT) processing is performed in block units, and image data is reproduced in the case of odd frames, and motion compensation inter-frame prediction error data is reproduced in the case of even frames.

During the frame period in which the inverse DCT circuit 34 outputs the odd-numbered frame image data, the odd-numbered frame image data is output to the frame memory 3 by the selection circuit 35.
8 and is written. Further, during the frame period in which the inverse DCT circuit 34 outputs the motion compensation inter-frame prediction error data of the even frames, the selection circuit 35 supplies the motion compensation inter-frame prediction error data of the even frames to the adding circuit 36. At the same time, the motion compensation circuit 3
Reference numeral 7 denotes the image data of the odd-numbered frame, which is the previous frame, stored in the frame memory 38.
According to the motion vector supplied from 1, the block-based motion compensation prediction data is read out and supplied to the adding circuit 36. Therefore, in the addition circuit 36, the motion compensation prediction data from the motion compensation circuit 37 is added to the motion compensation inter-frame prediction error data of the even frame to reproduce the image data of the even frame. This image data is written in the frame memory 39.

Since the order of the blocks in which the decoded and image data is reproduced is shuffled according to a predetermined pattern, the image data is sequentially framed at a predetermined screen position determined according to the shuffling pattern. Deshuffling is performed by writing in the memories 38 and 39.

In the frame period in which the image data of the even frame is written in the frame memory 39, the image data of the odd frame which is the previous frame is read from the frame memory 38 in the display line of the interlaced scan in field units. Further, during the frame period in which the image data of the odd-numbered frame is written in the frame memory 38, the image data of the even-numbered frame which is the previous frame is read out from the frame memory 39 in the display line of the interlaced scanning in field units. The selection circuit 40 is switched alternately for each frame, and the odd-numbered frame image data read from the frame memory 38 and the frame memory 39 are read.
Image data of even frames read from D / A
It is supplied to the conversion circuit 29.

Although the first embodiment of the present invention has been described above, in order to clarify the features and effects of this embodiment,
One of the conventional examples will be briefly described with reference to FIG. However, FIG. 4 shows a recording system circuit in the conventional example, and the reproducing system circuit is the same as the reproducing system circuit of the embodiment shown in FIG. In FIG. 4, 8 is an image coding circuit, 41 is a selection circuit, 42 and 43 are frame memories, 44 is a motion vector detection circuit, 45 is a selection circuit, 46 is a subtraction circuit, and 4 is a subtraction circuit.
7 is a DCT circuit, 48 is a quantization circuit, 49 is an information amount control circuit, 50 is a variable length coding circuit, 51 is a buffer memory, 52 is an inverse quantization circuit, 53 is an inverse DCT circuit, 54 is a selection circuit, 55 Is a frame memory, 56 is a motion compensation circuit, and 57 is a selection circuit. The parts corresponding to those in FIG.

In FIG. 4, the image data from the A / D conversion circuit 2 is alternately supplied to the frame memories 42 and 43 for each frame by the selection circuit 41 and stored therein.
Here, the frame memory 42 stores and holds image data of odd frames, and the frame memory 43 stores and holds image data of even frames. In the frame period in which the image data of the even frame is written in the frame memory 43, the image data of the odd frame which is the previous frame stored and held in the frame memory 42 is read, and the image data of the odd frame is changed to the frame memory 42. In the frame period written in, the image data of the even frame which is the previous frame stored and held in the frame memory 43 is read out and supplied to the subtraction circuit 46 by the selection circuit 45, respectively. However, in this case, the shuffling processing in block units is not performed, and the image data of the blocks is output from the upper left to the lower right in the same order as the display scanning.

The image data of the odd frame is subtracted by the subtraction circuit 46.
In the frame period supplied to
Is supplied to the subtraction circuit 46, whereby the subtraction circuit 46 outputs the image data of the odd-numbered frame as it is. The image data of this odd frame is DC
The T circuit 47, the quantizing circuit 48, the information amount control circuit 49, and the variable length coding circuit 50 perform intra coding processing, and the buffer memory 51 temporarily stores and performs packing processing, and then the image coding circuit as compressed data. It is output from 8.

Here, the difference from the image coding circuit 3 in the above embodiment in FIG. 1 is that the information amount control circuit 49 performs feedback type information amount control. Depending on the integrated value of the difference between the amount of compressed data supplied to the buffer memory 51 and the amount of compressed data output from the buffer memory 51 at a fixed rate, the amount of compressed data is almost constant when viewed over a frame period or longer period. Thus, the information amount control circuit 49 sequentially changes the quantization parameter.
It should be noted that activity is detected in units of blocks and classification is performed, and the fineness of quantization is controlled according to the class information.

The inverse quantization circuit 52 and the inverse DCT circuit 5
3 is for reproducing the image data reproduced by the image decoding circuit corresponding to the image encoding circuit 8 by local decoding, and the locally decoded reproduced image data of odd-numbered frames is It is written in the frame memory 55 through the selection circuit 54 which is turned on.

On the other hand, in the frame period in which the image data of the even frame is supplied to the subtraction circuit 46, the motion compensation circuit 5
The motion-compensated prediction data output from No. 6 is supplied to the subtraction circuit 46 via the selection circuit 57, and the subtraction circuit 46 outputs motion-compensated inter-frame prediction error data. The motion compensation inter-frame prediction error data of this even frame is DC
The T circuit 47, the quantization circuit 48, the information amount control circuit 49, and the variable-length coding circuit 50 perform inter-coding processing, which is once stored in the buffer memory 51 and subjected to packing processing, and then compressed as image data as an image coding circuit. It is output from 8.

Also in this case, unlike the image coding circuit 3 in the above-mentioned embodiment in FIG. 1, the information amount control circuit 49 performs the feedback type information amount control.

The inverse quantization circuit 52 and the inverse DCT circuit 5
The motion-compensated inter-frame prediction error data locally decoded in 3 is not written in the frame memory 55 because the selection circuit 54 is turned off. In the frame memory 55,
The locally decoded reproduced image data of the odd frame which is the previous frame is stored and held as it is. Therefore, the motion vector detection circuit 44 uses the image data of even frames held in the frame memory 43 and the frame memory 55.
The motion vector is detected block by block from the reproduced image data of the odd-numbered frames held in the memory and sequentially supplied to the motion compensation circuit 56. The motion compensation circuit 56 reproduces the reproduced image data from the frame memory 55 according to the motion vector. Is read out to generate motion compensation prediction data for each block.

The image decoding circuit of the reproducing system circuit corresponding to the recording system circuit of the conventional digital video signal recording / reproducing apparatus shown in FIG. 4 is the same as that of the first embodiment of the present invention shown in FIG. It has the same configuration as the image decoding circuit 28 of the reproduction system circuit, but is different in that the reproduced image data of each block in the frame is decoded in the same order as in the display scanning which is not shuffled.

As is clear from the above description, the first
In this embodiment, the local decoding circuit, that is, the inverse quantization circuit and the inverse DCT circuit, in the image encoding circuit, which is conventionally required, is unnecessary, so that the circuit scale can be reduced as compared with the conventional case. Further, the symmetry of the processing between the image encoding circuit in the recording system circuit and the image decoding circuit in the reproducing system circuit is enhanced, and in the digital video signal recording / reproducing apparatus in which the circuits are shared by both, especially compared with the conventional technique. Can also reduce the circuit scale.

In the first embodiment, in the inter-coded even frame, the motion compensation prediction data generated from the input image data of the odd frame by the image coding circuit 3 and the image decoding circuit 28. It does not completely match the motion-compensated prediction data generated from the reproduced image data of odd-numbered frames. This is because the intra-encoding of odd-numbered frames causes some coding distortion to be mixed in the reproduced image data of odd-numbered frames. However, the deterioration of the image quality of even frames due to this coding distortion is small, and since the next odd frame is intra-coded again, it does not affect the subsequent frames.

Further, in the first embodiment, after shuffling in block units, a plurality of blocks at distant positions in the frame are collected to form a compressed block, and a feedforward type information amount is set in compressed block units. Since the quantization process is performed by the control, even in the odd frames that are intra-coded and in the even frames that are inter-coded, the change in the fineness of the pattern depending on the screen position and the change in the object depending on the screen position It is possible to suppress variations in the image quality of reproduced images due to variations in the degree of movement and deformation.

FIG. 5 is a block diagram showing a recording system circuit of a second embodiment of the digital video signal recording / reproducing apparatus according to the present invention. 58 is a frame delay circuit, 59 is a multiplexing circuit, and 61 is an image coding circuit. Therefore, parts corresponding to those in FIG.

In FIG. 5, the selection circuit 11 causes A /
The odd-numbered frame image data from the D conversion circuit 2 is delayed by one frame period in the frame delay circuit 58 and then supplied to the frame memory 12 for writing, and the even-numbered frame image data is supplied to the frame memory 13. Written. As a result, the image data of the even frame and the image data of the odd frame which is the previous frame are simultaneously written in the frame memories 13 and 12 during the frame period in which the image data of the even frame is input. The frame memories 12 and 13 each have a two-sided structure, and the side to be used is switched every two frames.

During the next frame period in which the odd-numbered frame image data is supplied from the A / D conversion circuit 2, the even-numbered frame image data is output from the frame memory 13 and the odd-numbered frame image data which is the previous frame is output from the frame memory 12. Each of them is read out, and the motion vector detection circuit 14 detects a motion vector in block units from the image data of these frames and stores it in the vector memory 24. Then, over the next two frame periods, the same odd frame image data is read from the frame memory 12 and the same even frame image data is read from the frame memory 13 alternately in macro block units. At this time,
The motion compensation circuit 15 generates motion compensation prediction data for image data of even frames according to the motion vector supplied from the vector memory 24, and the subtraction circuit 16 generates motion compensation interframe prediction error data of even frames. . Therefore, the image data of the odd-numbered frame is supplied to the multiplexing circuit 59 as it is, and the motion-compensated interframe prediction data is supplied to the multiplexing circuit 59 in the even-numbered frame.

In the multiplexing circuit 59, the image data of the odd-numbered frame and the motion compensation inter-frame prediction error data of the even-numbered frame are multiplexed in macroblock units. Then, similarly to the image encoding circuit 3 in FIG. 1, the DCT circuit 18, the delay circuit 19, the information amount control circuit 20, the quantization circuit 21, the variable length encoding circuit 22 and the buffer memory 23 are used to generate an image of an odd frame. The data is intra-coded and
The motion-compensated inter-frame prediction error data of even frames is inter-coded.

FIG. 6 is an explanatory diagram showing the recording format of the compressed data in the second embodiment.

As shown in FIG. 6A, the compressed data (intra-coded data) for the image data of the odd-numbered frame multiplexed in macroblock units and the motion-compensated inter-frame prediction error data for the next even-numbered frame are used. Compressed data (inter-coded data) is recorded on 40 tracks. Compressed data for 13 compressed blocks is recorded per track.

FIG. 6B shows how the compressed data of each compressed block controlled to have a constant data amount is packed into a predetermined number of synchronous blocks. Here, MB1, M
B2 ... Represents intra-coded data of macroblocks, and mb1, mb2, ... Represents inter-coded data of macroblocks.

Also in this case, in order to reduce error propagation when an error or omission occurs in the middle of the variable-length coded data, the intra-coded data of 9 macroblocks each is stored in the buffer memory 23. The compressed data of the compressed block composed of
As shown in (b), it is packed into 12 synchronization blocks. Specifically, one continuous macroblock is packed with one macroblock of intra-coded data, and the next one synchronous block is packed with three macroblocks of inter-coded data. In addition, the multiplexing circuit 59 performs the multiplexing process so as to be like this.

The end portion of the compressed data of the macroblock that could not be stored in the macroblock storage area corresponding to each macroblock is stored in the empty area remaining in the other macroblock storage areas, as in the first embodiment. Store.

By packing the compressed data as described above, even if an error occurs in the middle of the synchronization block and the correction cannot be completed, the data of higher importance before the error can be decoded. Also, the effect of the error does not propagate to other macroblocks.

FIG. 7 is a block diagram showing a reproducing system circuit corresponding to the recording system circuit shown in FIG. 5, in which 60 is a compressed data memory and 62 is an image decoding circuit. Are denoted by the same reference numerals and redundant description will be omitted.

In FIG. 7, the intra-coded data and the inter-coded data packed in the macro block unit shown in FIG. 6B from the error correction circuit 27 are temporarily stored in the buffer memory 31, and the original order is stored. And the quantization parameter, class information, and motion vector are separated. Then, all of these data are supplied to and stored in the compressed data memory 60.

In the compressed data memory 60, the intra-coded data of the odd-numbered frame and the inter-coded data of the even-numbered frame, which are multiplexed in macroblock units, are stored and held for one frame period respectively, and the intra-coded data of the odd-numbered frame is first stored. After the encoded data is output for one frame in block units, the inter-coded data for the even frames is then output for one frame in block units.

The odd-coded intra-coded data and the even-framed inter-coded data output from the compressed data memory 60 are processed in the same manner as in the first embodiment shown in FIG. , The inverse quantization circuit 33,
Inverse DCT circuit 34, addition circuit 36 and motion compensation circuit 37
The reproduced image data of the odd frames is written in the frame memory 38 and the reproduced image data of the even frames is written in the frame memory 39 by the selection circuit 35. The reproduced image data of the odd-numbered frame held in the frame memory 38 and the reproduced image data of the even-numbered frame held in the frame memory 39 are supplied to the D / A conversion circuit 29 through the selection circuit 40 that switches alternately. .

In the second embodiment described above, after the shuffling in block units, the intra-coded odd frame and the inter-coded even frame are
Compressed blocks are constructed by collecting multiple blocks at distant positions in the frame, and quantization is performed by the feedforward type information amount control in units of compressed blocks. Therefore, changes in the fineness of the picture depending on the screen position, and It is possible to suppress the fluctuation of the image quality of the reproduced image due to the variation in the degree of movement or deformation of the object depending on the screen position.

The two embodiments have been described above. The invention is not limited to only such examples.

That is, the conditions such as the number of coded pixels, the block structure, the macro block structure, the compressed block structure, the synchronous block structure, and the recording format are not limited to those in the above-described embodiment, and various cases are conceivable. In any case, the present invention is similarly applicable. Further, the image coding method for compressing the image data and the motion compensation inter-frame prediction error data may be other than the DCT coding method described in the above embodiments. For example,
A DPCM coding method, a vector quantization method, etc. are conceivable.

In the present invention, as a motion compensation method,
The present invention is not limited to the embodiment described above, and may be, for example, a method of performing the filtering process on the image data of the previous frame and then shifting the image data by the motion vector to generate the motion compensation prediction data. In the case of the present invention, the motion-compensated prediction data at the time of encoding and the motion-compensated predictive data at the time of decoding do not completely match, but a motion compensation method including a filtering process for reducing noise and coding distortion in this way is used. When used, the difference between the motion-compensated prediction data at the time of encoding and the motion-compensated prediction data at the time of decoding becomes small, so that the coding distortion included in the reproduced image data is reduced and the image quality is improved.

Further, it is clear that the present invention is effective even when the inter-frame prediction error data is generated by a simple inter-frame difference without using motion compensation.

Further, although the magnetic tape is used as the data recording medium in the embodiments described above, the present invention is not limited to this, and the same can be applied to the case of using another data recording medium such as an optical disk or a magnetic disk.

[0101]

As described above, according to the present invention,
In the recording system circuit, the input image data of the selected specific screen is stored in the image data storage means and is intra-coded by the image coding means, and the input image data of other screens is held in the image data storage means. Since the inter-picture prediction error data is generated by the prediction error data generating means from the input image data of the specified screen, which is inter-encoded by the image encoding means, the conventionally required local decoding means is unnecessary. Therefore, the circuit scale can be reduced more than ever before.

Further, according to the present invention, since the processing of the image coding means in the recording system circuit and the processing of the image decoding means in the reproduction system circuit are highly symmetrical, it is easy to realize the commonality of the circuits in both. .

Further, according to the present invention, the selected specific screen is data-compressed while maintaining high image quality by intra-coding, and the other screens are data-compressed by inter-coding having a high data compression rate. It is possible to realize recording and reproduction of a video signal having a high data compression rate and high image quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a recording system circuit of a first embodiment of a digital video signal recording / reproducing apparatus according to the present invention.

FIG. 2 is an explanatory diagram showing a recording format of compressed data in the first embodiment of the digital video signal recording / reproducing apparatus according to the present invention.

3 is a block diagram showing a reproducing system circuit for the recording system circuit shown in FIG. 1. FIG.

FIG. 4 is a block diagram showing a recording system circuit of an example of a conventional digital video signal recording / reproducing apparatus.

FIG. 5 is a block diagram showing a recording system circuit of a second embodiment of the digital video signal recording / reproducing apparatus according to the present invention.

FIG. 6 is an explanatory diagram showing a recording format of compressed data in a second embodiment of the digital video signal recording / reproducing apparatus according to the present invention.

7 is a block diagram showing a reproduction system circuit for the recording system circuit shown in FIG.

[Explanation of symbols]

 3 image coding circuit 4 correction coding circuit 5 modulation recording circuit 12, 13 frame memory 14 motion vector detection circuit 15 motion compensation circuit 16 subtraction circuit 18 DCT circuit 20 information amount control circuit 21 quantization circuit 22 variable length coding circuit 23 Buffer memory 24 Vector memory 26 Playback demodulation circuit 27 Error correction circuit 28 Image decoding circuit 31 Buffer memory 32 Variable length decoding circuit 33 Inverse quantization circuit 34 Inverse DCT circuit 36 Adder circuit 37 Motion compensation circuit 38, 39 Frame memory 59 Multiplexing Circuit 60 Compressed data memory 61 Image encoding circuit 62 Image decoding circuit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Nobuyoshi Tsukiji 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture

Claims (10)

[Claims] 1. A digital video signal recording / reproducing apparatus for compressing an input video signal and recording it on a data recording medium, comprising: image data storage means for storing image data of the input video signal for one screen or more; Prediction error data generation means for generating inter-screen prediction error data from image data of signals and image data held in the image data storage means, image data output from the image data storage means, and the prediction error data A digital video signal recording / reproducing apparatus comprising: an image encoding unit for compressing inter-picture prediction error data output from the generating unit. 2. The image coding means according to claim 1, wherein the image coding means includes at least an orthogonal transforming means and a quantizing means, and outputs image data output from the image data storage means and output from the prediction error data output means. A digital video signal recording / reproducing device characterized by orthogonally transform-encoding certain inter-picture prediction error data and compressing the data. 3. The prediction error data generation means according to claim 1, wherein the prediction error data generation means reads out image data approximate to the image data of the input video signal from the image data storage means, and the motion compensation means. A digital video signal recording / reproducing apparatus comprising: subtraction means for subtracting output image data from image data of the input video signal to generate inter-screen prediction error data. 4. The image coding means according to claim 1, wherein the image coding means outputs the image data output from the image data storage means and the inter-screen prediction error data output from the prediction error data output means. , A digital video signal recording / reproducing apparatus characterized in that encoding is performed while alternately switching in screen units. 5. The image coding means according to claim 1, wherein the image coding means outputs the image data output from the image data storage means and the inter-screen prediction error data output from the prediction error data output means. , A digital video signal recording / reproducing apparatus characterized in that encoding is performed while alternately switching in units of partial areas consisting of a plurality of pixels in a screen. 6. A digital video signal recording / reproducing apparatus for compressing an input video signal and recording it on a data recording medium, comprising: image data storage means for storing image data of the input video signal for one screen or more; A prediction error data generating unit that generates inter-screen prediction error data from image data of a signal and image data stored in the image data storage unit; and image data of the input video signal and an output of the prediction error data generating unit. A digital video signal recording / reproducing apparatus comprising: an image encoding means for compressing a certain inter-picture prediction error data. 7. The image coding means according to claim 6, wherein the image coding means includes at least an orthogonal transforming means and a quantizing means, and image data of the input video signal and inter-picture prediction output from the prediction error data output means. A digital video signal recording / reproducing apparatus characterized by orthogonally transform-encoding error data and compressing the data. 8. The prediction error data generation means according to claim 6 or 7, wherein the prediction error data generation means reads out image data approximate to the image data of the input video signal from the image data storage means, and the motion compensation means. A digital video signal recording / reproducing apparatus comprising: subtraction means for subtracting output image data from image data of the input video signal to generate inter-screen prediction error data. 9. The image coding means according to claim 6, 7 or 8, wherein the image data of the input video signal and the inter-screen prediction error data output from the prediction error data output means are alternated on a screen-by-screen basis. A digital video signal recording / reproducing apparatus characterized in that encoding is performed while switching to. 10. The image coding means according to claim 6, 7 or 8, wherein the image data of the input video signal and the inter-screen prediction error data output from the prediction error data output means are stored in a plurality of frames within the screen. A digital video signal recording / reproducing apparatus characterized in that encoding is performed while being switched alternately in units of partial areas each consisting of the pixels.