JPH0767068B2 - Level shifter circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit, and more particularly to a level shifter circuit between a shift register in a scanning circuit for supplying a scanning signal to a liquid crystal display panel and an output buffer circuit.

[0002]

2. Description of the Related Art A liquid crystal display, a contact image sensor, a liquid crystal shutter, a fluorescent display tube, and the like are manufactured integrally with a display circuit for the purpose of downsizing, cost reduction, and high reliability. There is technology. This is because the number of connection terminals and the number of external drive ICs can be significantly reduced by installing the peripheral drive circuit on the same substrate as the pixel electrodes, and the limitation of the bonding process of large area and high density. It is based on the concept of being able to solve reliability problems.

A scanning circuit is one of the most basic circuits among the peripheral driving circuits such as a liquid crystal display and a contact image sensor. This scanning circuit has usually been composed of a shift register and an output buffer circuit, but recently,
Level shifter circuits for converting the levels of power supply voltages of shift registers and output buffer circuits have come to be used as interface circuits between shifter registers and output buffer circuits. This corresponds to the increase in the number of pixels of liquid crystal displays, contact image sensors, etc.
By operating the shift register at a speed lower than the drive voltage of the output buffer circuit, low power consumption is achieved.
This level shifter circuit plays an increasingly important role in the future, in order to achieve high reliability.

FIG. 4 shows a circuit diagram including a conventional level shifter circuit and its peripheral circuits.

The level shifter circuit 10 receives an input signal Vin from the shift register 20 having a power supply potential Vdd1 at its gate electrode and an N-channel type MOS transistor Q11 having its source electrode connected to a ground potential point, and an input signal Vin at its gate electrode. N-channel type MOS transistor Q which receives the level inversion signal and connects the source electrode to the ground potential point
12, the gate electrode is connected to the drain electrode of the MOS transistor Q12, the source electrode is connected to the power supply terminal of the power supply potential Vdd2 (hereinafter referred to as the power supply terminal (Vdd2)), and the drain electrode is connected to the drain electrode of the MOS transistor Q11. P-channel type MOS transistor Q
7, and the gate electrode is connected to the drain electrode of the MOS transistor Q11, and the source electrode is the power supply terminal (Vdd
2) Connect the drain electrode to the MOS transistor
A level shift portion 11b having a P-channel type MOS transistor Q8 connected to the drain electrode of the above and having this connection point as a signal output terminal, and an N channel type for connecting the source electrode to the ground potential point by receiving the input signal Vin at the gate electrode. MO
Input signal Vin to the S transistor Q9 and the gate electrode
The source electrode is connected to the power supply terminal of the power supply potential Vdd1 (hereinafter referred to as power supply terminal (Vdd1)), the drain electrode is connected to the drain electrode of the MOS transistor Q9, and the level inversion signal of the input signal Vin is supplied from this connection point. And a level inversion unit 12 of a CMOS type inverter having a P-channel type MOS transistor Q10 for output, and an output signal Vou from the output of the level shift unit 11b.
t is supplied to the output buffer circuit 30. The level shifter circuit having such a structure is disclosed in, for example, Japanese Patent Laid-Open Nos. 62-269419 and 63-1055.
No. 22 publication.

In this example, the power supply potential Vdd1 of the shift register 20 and the level inverting section 12 is set to the level shift section 1
It is set to 1/2 of the power supply potential Vdd2 of 1b, so that the maximum voltage level of the input signal Vin and its level inversion signal is also 1/2 of Vdd2.

FIG. 5 is a voltage waveform diagram of each part of the level shifter circuit 10.

When the input signal Vin is at a low level (0V), the MOS transistor Q11 is turned off and the transistor Q12 is turned on. Therefore, the gate electrode potential of the MOS transistor Q7 shifts to the ground potential side and the MOS transistor Q7 turns on. . This MOS transistor Q7 supplies the power supply potential Vdd2 to the gate electrode of the MOS transistor Q8.
The OS transistor Q8 is turned off. As a result, the output signal Vout becomes a low level of 0V. When the input signal Vin becomes high level, the MOS transistors Q11 and Q8 are turned on and the MOS transistors Q12 and Q7 are turned off,
The output signal Vout becomes the high level Vdd2. Thus, the input signal Vin of the maximum voltage Vdd1 is
The level is converted into the output signal Vout of dd2.

For example, in a liquid crystal display, an image signal Vv having an amplitude of about 12V is supplied to the liquid crystal cells LC41 and N.
The signal is transmitted to the source electrode of the MOS transistor Q41 of each pixel of the liquid crystal display section 40 including the channel type MOS transistor Q41. In order to efficiently transmit this image signal Vv to the liquid crystal cell LC41, the MOS transistor Q41
The voltage of the gate electrode is set to about 20 V, which is higher than the image signal Vv by the threshold voltage of the MOS transistor Q41. That is, the output signal Vou of the level shifter circuit 10
In response to t, the MOS transistor Q41 of the liquid crystal display unit 40
Of the output signal Vout of the level shifter circuit 10 is set to about 20V, and the power supply voltage Vdd2 needs to be set to about 20V.

Here, when the input signal Vin is at a low level, the source-drain voltage Vds (Q11) of the MOS transistor Q11 is high, and when it is at a high level, the source-drain voltage Vds (Q1) of the MOS transistor Q12.
2) becomes substantially equal to the power supply potential Vdd2 (20V), the source-drain breakdown voltage of the MOS transistors Q11 and Q12 must be higher than the power supply potential Vdd2 (20V).

On the other hand, with the shortening of the channel of the transistor, particularly in the N-channel type MOS transistor,
Characteristic deterioration due to the generation of hot carriers is becoming a problem. Hot carriers are generated because electrons flowing from the source region to the drain region are accelerated by a strong electric field in the vicinity of the drain region to obtain large energy. The electrons injected into the strong electric field region near the drain region generate many electron-hole pairs by impact ionization. These hot carriers cause an excessive drain current or are injected into the oxide film, which causes an increase in drain withstand voltage threshold voltage and a decrease in mutual conductance.

Generally, in a single crystal silicon LSI driven at 5V, the hot carrier becomes a problem when the channel length is 2 μm or less. However, as described above, the peripheral driving circuit of the liquid crystal display requires 20V driving, and therefore, the problem of hot carrier generation occurs even in a channel length region (for example, 4 μm) which does not cause any problem in 5V driving. In order to solve this problem, it is most effective to adopt a structure for relaxing the electric field strength at the edge of the drain region, that is, an offset gate structure or an LDD (Lightly Doped Dain) structure.

[0013]

The conventional level shifter circuit described above has the MOS transistor (Q41) of each pixel.
Since it is necessary to drive the gate electrode of the above with a high voltage of, for example, about 20 V, the MOS forming the level shift unit 11b
Transistors, especially N-channel type MOS transistors Q11 and Q12 that are greatly affected by hot carriers
Is of a high breakdown voltage type having an offset gate structure and an LDD structure. However, in the case of the offset gate structure, since the on-current is small, it cannot be said to be ideal in terms of operation speed. Further, in the case of the LDD structure, the number of process steps is increased, so that there is a problem that the yield is reduced and the cost is increased.

An object of the present invention is to provide a level shifter circuit which can obtain a high voltage output and a high reliability without reducing the operation speed and increasing the number of process steps.

[0015]

A level shifter circuit of the present invention comprises a first conductivity type MOS transistor for connecting an input signal to a gate electrode and a source electrode to a reference potential point, and a gate electrode for receiving the input signal. A second one-conductivity type which receives the level inversion signal and connects the source electrode to the reference potential point
And a third MOS transistor of one conductivity type that connects the source electrode to the drain electrode of the first MOS transistor by receiving the input signal at its gate electrode, and a level inversion signal of the input signal at its gate electrode. A fourth MOS transistor of one conductivity type that connects the receiving source electrode to the drain electrode of the second MOS transistor, and the gate electrode receives the input signal to form the first source electrode.
A fifth MOS transistor of reverse conductivity type connected to the first power supply terminal of the power supply potential and having a drain electrode connected to the drain electrode of the first MOS transistor, and a level-inverted signal of the input signal to the gate electrode. A sixth MOS transistor of the reverse conductivity type having a receiving source electrode connected to the first power supply terminal and a drain electrode connected to the drain electrode of the second MOS transistor, and a gate electrode of the fourth MOS transistor.
Reverse-conduction-type seventh MOS connected to the drain electrode of the MOS transistor, the source electrode connected to the second power supply terminal of the second power supply potential, and the drain electrode connected to the drain electrode of the third MOS transistor A transistor and a gate electrode connected to the drain electrode of the third MOS transistor, a source electrode connected to the second power supply terminal, a drain electrode connected to the drain electrode of the fourth MOS transistor, and a drain electrode connected to the drain electrode of the fourth MOS transistor. It has a level shift section including an eighth MOS transistor of the reverse conductivity type which serves as a signal output terminal.

Further, a ninth MOS transistor of one conductivity type, in which the gate electrode receives the input signal and the source electrode is connected to the reference potential point, and the gate electrode receives the input signal and the source electrode is the first power supply terminal. A reversely conductive type tenth MOS transistor connecting the drain electrode to the drain electrode of the ninth MOS transistor;
And a level inversion unit that outputs a level inversion signal of the input signal from the drain electrode connection point of the tenth MOS transistor. Alternatively, it has a configuration in which the level inversion signal of the input signal is obtained from the drain electrode connection points of the first and fifth MOS transistors.

In addition, the first power supply potential is set to be approximately half of the second power supply potential, one conductivity type is an N channel type, and the opposite conductivity type is a P channel type.

[0018]

According to the structure of the present invention, when the input signal is at a low level, the N-channel type first and third MOS transistors and the P-channel type sixth and eighth MOS transistors are off, and the N-channel type Since the second and fourth MOS transistors and the P-channel type fifth and seventh MOS transistors are turned on, the drain electrode of the first MOS transistor and the source electrode of the third MOS transistor are
1 / second of the second power supply potential by the fifth MOS transistor
The second power supply potential is supplied to the drain electrode of the third MOS transistor, and the second power supply potential is supplied to the drain electrode of the third MOS transistor by the seventh MOS transistor. Therefore, the third M
The source-drain voltage of the OS transistor and the first MOS transistor that connects the source electrode to the reference potential point (usually the ground potential point) is ½ of the second power source potential (first
Equal to the power supply potential of). In addition, the drain electrodes of the second and fourth MOS transistors in the ON state are
Since the sixth and eighth MOS transistors are off, the first and second power supply potentials are no longer supplied and the potentials drop to near ground. That is, the source-drain voltage of the second and fourth MOS transistors is almost 0V. When the input signal is at a high level, the on / off state of each MOS transistor is opposite to the above case, and the second, fourth
The source-drain voltage of the second MOS transistor is the second
To 1/2 (first power supply potential) of the power supply potential of
The source-drain voltage of the MOS transistor is about 0V.

Therefore, the N-channel type first to fourth MOs
The source-drain voltage of the S transistor does not exceed 1/2 of the second power supply potential (first power supply potential) in any case, and the high withstand voltage of the offset gate structure or LDD structure of these MOS transistors is obtained. It doesn't have to be a mold.

As a result, the generation of hot carriers can be prevented without increasing the number of process steps and without lowering the operation speed, so that the characteristics are not deteriorated and high reliability is obtained, and a desired high voltage output is obtained. To be

[0021]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, the input signal Vi is applied to the gate electrode.
n-type first MOS transistor Q1 that receives n and connects the source electrode to the ground potential point, and second N-channel type transistor that receives the level inversion signal of the input signal Vin on the gate electrode and connects the source electrode to the ground potential point Of the MOS transistor Q2, whose gate electrode receives the input signal Vin, and whose source electrode is connected to the drain electrode of the MOS transistor Q1.
A channel type third MOS transistor Q3, N having its gate electrode receiving a level inversion signal of the input signal Vin and having its source electrode connected to the drain electrode of the MOS transistor Q2
A channel-type fourth MOS transistor Q4, a gate electrode of which receives an input signal Vin and a source electrode of which is connected to a first power supply terminal of a first power supply potential Vdd1 (hereinafter referred to as a power supply terminal (Vdd1)) and a drain electrode Is connected to the drain electrode of the MOS transistor Q1, a gate electrode receives the level inversion signal of the input signal Vin at the gate electrode, the source electrode is connected to the power supply terminal (Vdd1), and the drain electrode is the MOS transistor. A sixth P-channel type MOS transistor Q6 connected to the drain electrode of Q2, a gate electrode connected to the drain electrode of the MOS transistor Q4 and a source electrode connected to the second
A P-channel type seventh MOS transistor Q7 having a drain electrode connected to the second power supply terminal (hereinafter, referred to as a power supply terminal (Vdd2)) of the power supply potential Vdd2 of FIG. An eighth P-channel type in which the electrode is connected to the drain electrode of the MOS transistor Q3, the source electrode is connected to the power supply terminal (Vdd2), the drain electrode is connected to the drain electrode of the MOS transistor Q4, and this drain electrode serves as a signal output terminal. Level MOS transistor Q8, an N-channel type ninth MOS transistor Q9 having a gate electrode receiving the input signal Vin and a source electrode connected to the ground potential point, and a gate electrode receiving the input signal Vin. The source electrode is connected to the power supply terminal (Vdd1) and the drain electrode is MOS Tenth MOS transistor Q1 of the P-channel type to be connected to the drain electrode of transistor Q9
0 and a level inversion unit 12 that outputs a level inversion signal of the input signal Vin from the drain electrode connection point of the MOS transistors Q9 and Q10. Note that the first power supply potential Vdd1 is equal to the second power supply potential Vdd2.
It is set to 1/2 of (for example, 20V).

Next, the operation of this embodiment will be described.
FIG. 2 is a voltage waveform diagram of each part for explaining the operation of this embodiment.

First, when the input signal Vin is low level,
The MOS transistors Q1 and Q3 that directly receive the input signal Vin at their gate electrodes are off, Q5 is on, and the MOS transistors Q2 and Q4 that receive the level inversion signal of the input signal Vin at their gate electrodes through the level inversion unit 12 are on.
Q6 is turned off, the MOS transistor Q7 is turned on, and Q8 is turned off with the turning on of the MOS transistors Q2 and Q4. Therefore, the output signal Vout becomes the ground potential level of 0 V, and at this time, the source-drain voltage Vds (Q of the N-channel type MOS transistors Q2, Q4 is obtained.
2), Vds (Q4) becomes 0V. Further, the drain electrode and the MOS of the N-channel type MOS transistor Q1
The potential Vb of the source electrode of the transistor Q3 is the power source potential V
Since the potential Va of the drain electrode of the dd1 and the MOS transistor Q3 becomes the power source potential Vdd2, the source-drain voltage Vds of these MOS transistors Q1 and Q3.
(Q1) and Vds (Q3) are both 1 of the power supply potential Vdd2.
The voltage becomes / 2 (equal to the power supply potential Vdd1).

Further, when the input signal Vin is at the high level, the on / off states of the MOS transistors Q1 to Q8 are opposite to those at the low level, and the output signal Vout.
Is the power supply potential Vdd2 and the MOS transistors Q1 and Q3
Source-drain voltage Vds (Q1), Vds (Q
3) is set to 0V, and the source-drain voltages Vds (Q2) and Vds (Q4) of the MOS transistors Q2 and Q4 are ½ of the power supply potential Vdd2 (equal to the power supply potential Vdd1).

That is, the maximum voltage of the output signal Vout reaches the desired power supply potential Vdd2, but the source-drain voltage of the N-channel MOS transistors Q1 to Q4 is 1/2 of the power supply potential Vdd2 in any case. The voltage (equal to the power supply potential Vdd1) is not exceeded, and these MOS transistors need not be of high withstand voltage type.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In the first embodiment, the input signal Vin
In order to obtain the level inversion signal of, the level inversion unit 12 is provided separately from the level shift unit 11, and the level inversion unit 11 has the same function as this level inversion unit 12.
A circuit composed of MOS transistors Q1 and Q5 (1 in FIG. 3)
1a), there is a broken line portion 1a). Therefore, in the second embodiment,
The level inversion signal of the input signal Vin is obtained from the connection point of the drain electrodes of the MOS transistors Q1 and Q5 of this circuit and supplied to the gate electrodes of the MOS transistors Q2, Q4 and Q6, and the level inversion unit 12 in the first embodiment is supplied. It is unnecessary. The operation and effect are basically the same as those of the first embodiment, and the description thereof will be omitted.

The above-described level shifter circuit according to the present invention was manufactured by integrating thin film transistors of polycrystalline silicon on a glass substrate, and was adopted in a vertical scanning circuit for a liquid crystal display for testing. The channel length of the thin film transistor forming the level shifter circuit was designed such that the withstand voltage between the source and drain was 10 V, which is half the power supply potential Vdd2 = 20 V. That is, the N-channel type thin film transistor was designed with a channel length of 3 μm and the P-channel type thin film transistor with a channel length of 2 μm. This is set to be equal to the channel length of the thin film transistor which constitutes the shift register circuit driven by 10V. This circuit was continuously operated for 1500 minutes under the conditions of the power supply potential Vdd2 = 20 V and the clock frequency f = 1 MHz, but even after that, the deterioration of the characteristics including the reduction of the breakdown voltage was not recognized.

[0031]

As described above, according to the present invention, the drain electrode and the source electrode of the first conductivity type (N-channel type) first and second MOS transistors are of opposite conductivity type (P-channel type) which receives a predetermined power supply potential. Type MOS transistors of the same conductivity type, and third and fourth MOS transistors of one conductivity type for connecting the gate electrodes to the gate electrodes of the first and second MOS transistors correspondingly, respectively, and the source electrodes. And a reverse conductivity type fifth and sixth MOS transistors for respectively connecting the gate electrode and the drain electrode which receive the potential of 1/2 of the power source potential to the gate electrode and the drain electrode of the first and second MOS transistors, respectively. By providing the configuration, the source-drain voltage of the one conductivity type (N-channel type) first to fourth MOS transistors is set to the power supply potential. Can be suppressed to 1/2,
Since these MOS transistors do not have to have a high withstand voltage structure, the number of process steps does not increase, the operation speed does not decrease, the generation of hot carriers can be prevented, the characteristics are not deteriorated, and high voltage output and high reliability are obtained. There is an effect that is.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a voltage waveform diagram of each portion for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional level shifter circuit and its peripherals.

5 is a voltage waveform diagram of each portion for explaining the operation of the level shifter circuit shown in FIG.

[Explanation of symbols]

 10 level shifter circuit 11, 11a level shift unit 12 level inversion unit 20 shift register 30 output buffer circuit 40 liquid crystal display unit LC41 liquid crystal cell Q1 to Q12, Q41 MOS transistor

Claims (5)

[Claims] 1. A first-conductivity-type first MOS transistor connecting a gate electrode with an input signal to connect a source electrode to a reference potential point, and a gate electrode receiving a level inversion signal of the input signal with a source electrode having the reference potential. A second MOS transistor of one conductivity type connected to the point, a third MOS transistor of one conductivity type connected to the gate electrode of the input signal with the source electrode connected to the drain electrode of the first MOS transistor, and a gate A fourth MOS transistor of one conductivity type, the source of which receives the level inversion signal of the input signal and the source electrode of which is connected to the drain electrode of the second MOS transistor, and the gate electrode of which is the first source electrode which receives the input signal. Of the opposite conductivity type, the drain electrode of which is connected to the first power supply terminal of the power source potential and the drain electrode of which is connected to the drain electrode of the first MOS transistor. A fifth MOS transistor and a reverse conductivity type in which a gate electrode receives a level inversion signal of the input signal and a source electrode is connected to the first power supply terminal and a drain electrode is connected to a drain electrode of the second MOS transistor. And a gate electrode connected to the drain electrode of the fourth MOS transistor, a source electrode connected to a second power supply terminal of a second power supply potential, and a drain electrode connected to the third MOS transistor. A reverse conductivity type seventh MOS transistor connected to the drain electrode of the third MOS transistor, a gate electrode connected to the drain electrode of the third MOS transistor, a source electrode connected to the second power supply terminal, and a drain electrode connected to the second power supply terminal. An eighth MOS transistor of the reverse conductivity type, which is connected to the drain electrode of the MOS transistor of No. 4 and uses this drain electrode as a signal output terminal. A level shifter circuit, characterized in that it has a level shift unit and a motor. 2. A ninth MOS transistor of one conductivity type, wherein the gate electrode receives an input signal and connects the source electrode to a reference potential point; and the gate electrode receives the input signal and the source electrode is a first power supply terminal. A reverse conductive type tenth MOS transistor connecting the drain electrode of the ninth MOS transistor and the drain electrode of the ninth MOS transistor, and the level of the input signal from the drain electrode connection point of the ninth and tenth MOS transistors. The level shifter circuit according to claim 1, further comprising a level inversion unit that outputs an inversion signal. 3. The level shifter circuit according to claim 1, wherein the level inversion signal of the input signal is obtained from the drain electrode connection points of the first and fifth MOS transistors. 4. The level shifter circuit according to claim 1, wherein the first power supply potential is approximately ½ of the second power supply potential. 5. One conductivity type is N-channel type, and opposite conductivity type is P-type.
The level shifter circuit according to claim 1, which is a channel type.