JPH0767003B2 - Copper / organic insulation film wiring board manufacturing method - Google Patents

Copper / organic insulation film wiring board manufacturing method

Info

Publication number
JPH0767003B2
JPH0767003B2 JP18305288A JP18305288A JPH0767003B2 JP H0767003 B2 JPH0767003 B2 JP H0767003B2 JP 18305288 A JP18305288 A JP 18305288A JP 18305288 A JP18305288 A JP 18305288A JP H0767003 B2 JPH0767003 B2 JP H0767003B2
Authority
JP
Japan
Prior art keywords
copper
organic insulating
insulating film
film
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18305288A
Other languages
Japanese (ja)
Other versions
JPH0232590A (en
Inventor
貞彦 参木
保彦 三宅
富雄 飯▲塚▼
護 御田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP18305288A priority Critical patent/JPH0767003B2/en
Publication of JPH0232590A publication Critical patent/JPH0232590A/en
Publication of JPH0767003B2 publication Critical patent/JPH0767003B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/38Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/381Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate

Description

【発明の詳細な説明】 <産業上の利用分野> 本発明は、銅・有機絶縁膜配線板の製造方法に関する。The present invention relates to a method for manufacturing a copper / organic insulating film wiring board.

<従来の技術> LSIの高速化、高集積化に伴い、これを搭載する配線板
もそれへの対応が要求されており、LSIの高密度実装基
板として電気抵抗の小さい銅と誘電率が低く、かつ厚い
膜の形成が可能なポリイミドを用いた配線板が高速信号
処理が可能なことから注目されている。
<Prior Art> With the increase in the speed and integration of LSIs, the wiring boards on which they are mounted are also required to support it. As a high-density mounting board for LSIs, copper with low electrical resistance and low dielectric constant are used. In addition, a wiring board using polyimide capable of forming a thick film is attracting attention because it can perform high-speed signal processing.

ところで、この種の配線板の製造法としてはアルミナ、
ムライト、AlNなどのセラミック基板上にスピンコート
法などによりポリイミドワニスを所望の厚さに塗布し、
これをベーシング処理し、固化させた後、真空蒸着法に
より、銅膜を所望の厚さに形成し、これをフォトエッチ
ング法により回路を形成するのが一般的である。また、
必要に応じて、このような方法によりポリイミド膜と銅
膜の形成を交互に繰返し、多層の配線板を製造すること
ができる。
By the way, as a manufacturing method of this kind of wiring board, alumina,
Applying polyimide varnish to a desired thickness by spin coating etc. on a ceramic substrate such as mullite or AlN,
It is general that the copper film is formed into a desired thickness by a vacuum evaporation method after being subjected to a basing treatment to be solidified, and a circuit is formed by using the copper film. Also,
If necessary, the formation of the polyimide film and the copper film can be alternately repeated by such a method to manufacture a multilayer wiring board.

<発明が解決しようとする課題> 上記銅ポリイミド配線板の製造において、フォトエッチ
ング法により配線回路を形成する場合、銅膜とポリイミ
ド膜との密着性が悪く、時として銅膜が剥離する場合が
ある。また、剥離しないまでも形成する配線回路幅が微
細な場合には、接着強度の局部的なバラツキによりリー
ド幅が局部的に変化したり、欠けたりすることがある。
<Problems to be Solved by the Invention> In the production of the copper-polyimide wiring board, when a wiring circuit is formed by a photoetching method, the adhesion between the copper film and the polyimide film is poor, and the copper film sometimes peels off. is there. Further, if the wiring circuit width to be formed is small even before peeling, the lead width may be locally changed or chipped due to local variation in adhesive strength.

なお、リード幅の局部的変化、欠けの発生は、詳細な材
料調査の結果、単に接着強度のバラツキのみならず、蒸
着した銅膜の耐食性と深い関係があることがわかった。
すなわち、銅膜の耐食性が悪い場合には、エッチングの
際に銅膜の一部の結晶粒が欠落しやすい。このため、リ
ード幅が極度に微細になった場合には、結晶粒の欠落が
リードの断線にもつながりかねない危険がある。
As a result of a detailed material investigation, it was found that the local change in the lead width and the occurrence of chipping are deeply related to not only the variation in the adhesive strength but also the corrosion resistance of the deposited copper film.
That is, when the corrosion resistance of the copper film is poor, some crystal grains of the copper film are likely to be lost during etching. For this reason, when the lead width becomes extremely fine, there is a risk that the loss of crystal grains may lead to disconnection of the lead.

本発明は、前記従来技術の欠点を解消し、有機絶縁膜、
例えばポリイミド膜への接着強度が高く耐食性が良好で
パターニング性(配線回路形成性)が優れた銅膜を有す
る銅・有機絶縁膜配線板を提供することを目的としてい
る。
The present invention eliminates the above-mentioned drawbacks of the prior art, an organic insulating film,
For example, it is an object of the present invention to provide a copper / organic insulating film wiring board having a copper film having high adhesion strength to a polyimide film, good corrosion resistance, and excellent patterning property (wiring circuit formability).

<課題を解決するための手段> 上記目的を達成するために、本発明によれば、セラミッ
ク基板上に有機絶縁膜を形成し、次に該有機絶縁膜上に
真空蒸着法により純度99.999%以上の銅膜を形成したの
ち、フォトエッチング法によりパターニングを行うこと
を特徴とする銅・有機絶縁膜配線板の製造方法が提供さ
れる。
<Means for Solving the Problems> In order to achieve the above object, according to the present invention, an organic insulating film is formed on a ceramic substrate, and a purity of 99.999% or more is then formed on the organic insulating film by a vacuum deposition method. The method for producing a copper / organic insulating film wiring board is characterized in that the copper film is formed and then patterned by a photoetching method.

また、本発明によれば、セラミック基板上に有機絶縁膜
を形成し、次に該有機絶縁膜の表面を不活性ガスまたは
弱酸化性ガス雰囲気下でイオンボンバード処理したの
ち、この有機絶縁膜上に真空蒸着法により純度99.999%
以上の銅膜を形成し、続いてフォトエッチング法により
パターニングを行うことを特徴とする銅・有機絶縁膜配
線板の製造方法が提供される。
According to the present invention, an organic insulating film is formed on a ceramic substrate, and then the surface of the organic insulating film is subjected to ion bombardment treatment in an atmosphere of an inert gas or a weak oxidizing gas. 99.999% purity by vacuum deposition method
There is provided a method for manufacturing a copper / organic insulating film wiring board, which comprises forming the above copper film and then performing patterning by a photoetching method.

前記有機絶縁膜はポリイミド膜が好ましい。The organic insulating film is preferably a polyimide film.

以下に本発明を、さらに詳細に説明する。The present invention will be described in more detail below.

本発明に用いられるセラミック基板としては、アルミナ
板、ムライト板、AlN板、SiC板などを挙げることができ
る。
Examples of the ceramic substrate used in the present invention include an alumina plate, a mullite plate, an AlN plate, and a SiC plate.

本発明に用いられる有機絶縁膜としては、ポリイミド膜
のほか、誘電率が小さく耐熱性に優れたマレイミド、テ
フロンなど各種高分子膜が挙げられるが、特にポリイミ
ド膜は、他の有機絶縁膜に比較して金属との密着性が良
好で、かつ経済的に安価であるため好ましい。
As the organic insulating film used in the present invention, in addition to the polyimide film, various polymer films such as maleimide and Teflon, which have a small dielectric constant and excellent heat resistance, can be mentioned.In particular, the polyimide film is compared with other organic insulating films. It is preferable because it has good adhesion to metal and is economically inexpensive.

また、本発明で形成される銅膜の純度は、99.999%以上
が好ましい。この純度が99.999%未満では、含有してい
る微量不純物の偏析、あるいはそれに起因する結晶粒度
のバラツキにより、後工程であるエッチング時に結晶の
一部が欠落しやすくなる。特に、純度が99.9996%以上
では、結晶の欠落が著しく減少するので望ましい。
Further, the purity of the copper film formed in the present invention is preferably 99.999% or more. If the purity is less than 99.999%, a part of the crystal is likely to be lost during the etching in the subsequent step due to segregation of contained trace impurities or variation in crystal grain size due to the segregation. In particular, when the purity is 99.9996% or more, crystal loss is remarkably reduced, which is desirable.

まず、前記セラミック基板上に、常法によって前記有機
絶縁膜の原料の例えばワニスを塗布し、ベーキングして
固化、成膜させる。
First, a raw material for the organic insulating film, such as varnish, is applied on the ceramic substrate by a conventional method, and baked to solidify and form a film.

次に、前記有機絶縁膜の表面に真空蒸着法により前記銅
膜を形成させる。この銅膜を形成する前に、予め前記有
機絶縁膜の表面を不活性ガスまたは弱酸性化ガス、例え
ばAr、N2、(Ar+N2)、O2、(N2+O2)、(Ar+O2)な
どの雰囲気下でイオンボンバード処理しておくと、有機
絶縁膜と銅膜との密着性が向上するので好ましい。イオ
ンボンバード処理としては、高周波励起形、直流電界形
などを用いることができる。
Next, the copper film is formed on the surface of the organic insulating film by a vacuum deposition method. Prior to forming this copper film, the surface of the organic insulating film is preliminarily subjected to an inert gas or a weak acidifying gas such as Ar, N 2 , (Ar + N 2 ), O 2 , (N 2 + O 2 ), (Ar + O 2 ). It is preferable to perform the ion bombardment treatment in an atmosphere such as (4) because the adhesion between the organic insulating film and the copper film is improved. As the ion bombardment treatment, a high frequency excitation type, a DC electric field type or the like can be used.

前記銅膜の厚さは、必要に応じて適宜選択できるが、一
般的には0.3〜10μm程度である。0.3μm未満では、電
気抵抗が大きすぎ、また、10μmを超えると成膜に時間
がかかり高コストとなる。
The thickness of the copper film can be appropriately selected according to need, but is generally about 0.3 to 10 μm. If it is less than 0.3 μm, the electric resistance is too large, and if it exceeds 10 μm, it takes a long time to form a film, resulting in high cost.

前記銅膜形成に続いて、常法によりフォトエッチング法
によりパターニングを行い、銅ポリアミド系配線板が得
られる。
Subsequent to the formation of the copper film, patterning is carried out by a photoetching method in a usual manner to obtain a copper polyamide wiring board.

なお、上記有機絶縁膜と銅膜の形成は必要に応じて適宜
繰返えすことにより、多層の配線板を製造することがで
きる。
The formation of the organic insulating film and the copper film can be repeated as necessary to manufacture a multilayer wiring board.

また、有機絶縁膜に銅を直接蒸着する場合について、説
明したが、予め有機絶縁膜に異種金層、例えば、Ti、C
r、Ni、Znなどの薄層を蒸着し、その上に銅を蒸着して
もよい。
Further, the case where copper is directly vapor-deposited on the organic insulating film has been described, but different kinds of gold layers such as Ti and C are previously formed on the organic insulating film.
It is also possible to deposit a thin layer of r, Ni, Zn, etc., and then deposit copper on it.

<実施例> 以下に本発明を実施例に基づき具体的に説明する。<Examples> The present invention will be specifically described below based on Examples.

(実施例1) 厚さ1mmのアルミナ板上にポリイミドワニスを5μm厚
さ塗布し、これを350℃でベーキングし、固化させる操
作を4回繰返すことにより約20μm厚さのポリイミド膜
を得たのち、その表面に特別に何らの処理をすることな
しに純度99.997%の銅を電子ビーム加熱式で真空度4×
10-5torr、基板温度200℃、成膜速度30Å/sceの条件で
5μm厚さ真空蒸着した試料と、蒸着前に予め後述の条
件でポリイミド膜表面をイオンボンバード処理し、しか
るのち、銅を真空蒸着した試料を作成した。
(Example 1) A polyimide varnish having a thickness of 5 μm was applied on an alumina plate having a thickness of 1 mm, baking was performed at 350 ° C., and solidification was repeated 4 times to obtain a polyimide film having a thickness of about 20 μm. , 99.997% pure copper with electron beam heating and vacuum degree of 4 × without any special treatment on its surface
Samples vacuum-deposited with a thickness of 5 μm under the conditions of 10 −5 torr, substrate temperature of 200 ° C., and film formation rate of 30 Å / sce, and the polyimide film surface was subjected to ion bombardment treatment in advance under the conditions described below before vapor deposition. A vacuum evaporated sample was prepared.

このようにして作成した試料の蒸着膜の密着力を測定し
たところ、蒸着前にポリイミド表面をイオンボンバード
処理した試料の密度強度は、引剥し強さで1.31gf/cmで
あり、無処理のそれ(1.11gf/cm)の約1.2倍であった。
When the adhesion of the deposited film of the sample thus prepared was measured, the density strength of the sample subjected to ion bombardment of the polyimide surface before deposition was 1.31 gf / cm in peeling strength, It was about 1.2 times of (1.11 gf / cm).

なお、イオンボンバード処理は、高周波励起法により1.
4×10-4torrのArガス圧力下で高周波電力を200Wとして
約5分間行った。
The ion bombardment process is 1.
High-frequency power was set to 200 W under Ar gas pressure of 4 × 10 −4 torr for about 5 minutes.

(実施例2) 厚さ1mmのムライト板にポリイミドワニスを5μm厚さ
塗布し、これを350℃でベーキングし、固化させる操作
を4回繰返すことにより約20μm厚さのポリイミド膜を
得たのち、実施例1と同様の条件でイオンボンバード処
理し、その表面に純度99.997%の銅および99.997%の銅
を実施例1と同様の条件で約5μm厚さ真空蒸着した。
Example 2 A polyimide varnish having a thickness of 5 μm was applied to a mullite plate having a thickness of 1 mm, baking was performed at 350 ° C., and solidification was repeated 4 times to obtain a polyimide film having a thickness of about 20 μm. Ion bombardment treatment was performed under the same conditions as in Example 1, and 99.997% pure copper and 99.997% copper were vacuum-deposited on the surface thereof under the same conditions as in Example 1 to a thickness of about 5 μm.

得られた蒸着膜をフォトエッチング法により塩化銅溶液
を用いて線幅40μm、線間ピッチ40μmのパターンニン
グを行ったところ、99.997%純度の銅膜は、第1図に示
すリード1のサイド面1aでの結晶粒の欠落が第2a図に黒
点で示す如く多いのに対して99.9997%純度のものは第2
b図に示す如く上記結晶粒の欠落はごく僅かであった。
なお、第1図の2は有機絶縁膜(ポリイミド膜)、3は
セラミック基板、第2a図および第3b図の4は結晶粒を示
している。
The deposited film thus obtained was patterned by a photoetching method using a copper chloride solution with a line width of 40 μm and a pitch between lines of 40 μm. As a result, a copper film of 99.997% purity was formed on the side surface of the lead 1 shown in FIG. The loss of crystal grains in 1a is large as shown by the black dots in Fig. 2a, whereas the one with 99.9997% purity is second.
As shown in Fig. b, the crystal grains were scarcely missing.
In addition, 2 in FIG. 1 is an organic insulating film (polyimide film), 3 is a ceramic substrate, and 4 in FIGS. 2a and 3b are crystal grains.

<発明の効果> 本発明は、以上説明したように構成されているので、真
空蒸着法により高純度銅膜を形成することにより、銅膜
と有機絶縁膜の密着性に優れ、製品の信頼性が向上する
とともに、残留応力が小さいからエッチングが均一に進
行する。
<Effects of the Invention> Since the present invention is configured as described above, by forming a high-purity copper film by a vacuum deposition method, the adhesion between the copper film and the organic insulating film is excellent, and the product reliability is high. And the residual stress is small, so that the etching proceeds uniformly.

また、エッチング時の結晶粒の欠落が少なく、パターニ
ング性のよい銅膜が得られる。その上、従来法にくらべ
微細配線が可能となるという効果を奏する。
In addition, a copper film having less crystal grains during etching and good patterning properties can be obtained. In addition, there is an effect that fine wiring becomes possible as compared with the conventional method.

銅膜形成の前に有機絶縁膜の表面をイオンボンバード処
理すれば、銅膜の密着性が格段に向上するという効果を
奏する。
If the surface of the organic insulating film is subjected to the ion bombardment treatment before the formation of the copper film, the adhesiveness of the copper film is significantly improved.

【図面の簡単な説明】[Brief description of drawings]

第1図はパターニング時のリードのサイド面の説明図で
ある。 第2a図および第2b図はそれぞれ純度99.997%および99.9
997%の銅膜におけるリードのサイド面の部分拡大図で
ある。 符号の説明 1……リード、1a……サイド面、 2……有機絶縁膜(ポリイミド膜)、 3……セラミック板、4……結晶粒
FIG. 1 is an explanatory diagram of a side surface of a lead at the time of patterning. Figures 2a and 2b show 99.997% and 99.9% purity, respectively.
It is a partial enlarged view of the side surface of the lead in the copper film of 997%. Explanation of symbols 1 ... Lead, 1a ... Side surface, 2 ... Organic insulating film (polyimide film), 3 ... Ceramic plate, 4 ... Crystal grain

───────────────────────────────────────────────────── フロントページの続き (72)発明者 御田 護 茨城県日立市助川町3丁目1番1号 日立 電線株式会社電線工場内 (56)参考文献 特開 昭53−135840(JP,A) 特公 昭55−41275(JP,B2) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor, Mamoru Mita, 3-1-1 Sukegawa-cho, Hitachi City, Ibaraki Prefecture, Hitachi Cable Electric Wire Co., Ltd. (56) Reference JP-A-53-135840 (JP, A) KOSHO 55-41275 (JP, B2)

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】セラミック基板上に有機絶縁膜を形成し、
次に該有機絶縁膜上に真空蒸着法により純度99.999%以
上の銅膜を形成したのち、フォトエッチング法によりパ
ターニングを行うことを特徴とする銅・有機絶縁膜配線
板の製造方法。
1. An organic insulating film is formed on a ceramic substrate,
Next, a method of manufacturing a copper / organic insulating film wiring board, which comprises forming a copper film having a purity of 99.999% or more on the organic insulating film by a vacuum deposition method and then performing patterning by a photoetching method.
【請求項2】セラミック基板上に有機絶縁膜を形成し、
次に諸有機絶縁膜の表面を不活性ガスまたは弱酸化性ガ
ス雰囲気下でイオンボンバード処理したのち、この有機
絶縁膜上に真空蒸着法により純度99.999%以上の銅膜を
形成し、続いてフォトエッチング法によりパターニング
を行うことを特徴とする銅・有機絶縁膜配線板の製造方
法。
2. An organic insulating film is formed on a ceramic substrate,
Next, the surface of each organic insulating film is subjected to an ion bombardment treatment in an atmosphere of an inert gas or a weak oxidizing gas, and then a copper film having a purity of 99.999% or more is formed on this organic insulating film by a vacuum deposition method, and then a photo film is formed. A method for manufacturing a copper / organic insulating film wiring board, which comprises patterning by an etching method.
【請求項3】前記有機絶縁膜がポリイミド膜である請求
項1または2記載の銅・有機絶縁膜配線板の製造方法。
3. The method for producing a copper / organic insulating film wiring board according to claim 1, wherein the organic insulating film is a polyimide film.
JP18305288A 1988-07-22 1988-07-22 Copper / organic insulation film wiring board manufacturing method Expired - Lifetime JPH0767003B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18305288A JPH0767003B2 (en) 1988-07-22 1988-07-22 Copper / organic insulation film wiring board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18305288A JPH0767003B2 (en) 1988-07-22 1988-07-22 Copper / organic insulation film wiring board manufacturing method

Publications (2)

Publication Number Publication Date
JPH0232590A JPH0232590A (en) 1990-02-02
JPH0767003B2 true JPH0767003B2 (en) 1995-07-19

Family

ID=16128896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18305288A Expired - Lifetime JPH0767003B2 (en) 1988-07-22 1988-07-22 Copper / organic insulation film wiring board manufacturing method

Country Status (1)

Country Link
JP (1) JPH0767003B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE552717T1 (en) 2002-04-19 2012-04-15 Mitsubishi Materials Corp CIRCUIT BOARD, PROCESS FOR THEIR PRODUCTION AND POWER SUPPLY MODULE
JP4206915B2 (en) * 2002-12-27 2009-01-14 三菱マテリアル株式会社 Power module substrate

Also Published As

Publication number Publication date
JPH0232590A (en) 1990-02-02

Similar Documents

Publication Publication Date Title
JP3096699B2 (en) Aluminum alloy wiring layer, method for producing the same, and aluminum alloy sputtering target
JP3570802B2 (en) Copper thin film substrate and printed wiring board
US6331811B2 (en) Thin-film resistor, wiring substrate, and method for manufacturing the same
JPH0826889A (en) Formation of metallic film and metallic film for wiring
JPH0767003B2 (en) Copper / organic insulation film wiring board manufacturing method
JPH05251844A (en) Manufacture for flexible circuit board
JP3447075B2 (en) Flexible circuit board
JPH07105584B2 (en) Copper / organic insulation film wiring board manufacturing method
JPH0247257A (en) Method for coating a substrate with a metal layer
JP2562588B2 (en) Tantalum metal thin film circuit
JPH0661600A (en) Flexible circuit board
DE4115316A1 (en) THIN FILM MULTI-LAYER CIRCUIT AND METHOD FOR PRODUCING THIN FILM MULTI-LAYER CIRCUITS
JPS58130502A (en) Temperature depending resistor
JPH1056247A (en) Glass wiring board and production thereof
US4812388A (en) Process to obtain thin film lines
JPS63188814A (en) Production of thin film magnetic head
JP2802181B2 (en) Method of forming conductive film on ceramic circuit board
JP2536604B2 (en) Copper / organic insulation film wiring board manufacturing method
JPS63303730A (en) Polyether imide film metallized with metallic thin film
JPH0799378A (en) Resistor thin film layer formation of printed board
JP3218698B2 (en) Copper metallization method
JPS58145014A (en) Method of producing electrode plate
JPH05251843A (en) Manufacture of flexible circuit board for utilizing glow discharge
JPH08139422A (en) Flexible circuit board having metallic oxide layer
JPH0680565B2 (en) Substrate with conductor