JPH0766769A - Demodulating device - Google Patents

Abstract

PURPOSE:To receive a signal from a base station without interrupting it and to improve an SN ratio by allowing each demodulating part to temporarily store demodulated data and output the stored data synchronously with the output timing of demodulated data from another demodulating part and adding respective outputted demodulated data. CONSTITUTION:A celluler telephone set is provided with three demodulating parts 1a to 1c e.g. and three paths corresponding to the number of demodulating parts 1a to 1c and having high receiving levels e.g. out of plural paths from one base station received through an antenna and respective paths from plural base stations are respectively demodulated by the demodulating parts 1a to 1c. Respective demodulated data demodulated by the demodulating parts 1a to 1c are outputted to a data synthesizing part 2 together with a deskew data validating signal. The demodulated data are outputted from the demodulating parts 1a to 1c at the timing based upon address updating signal supplied from a data synthesizing part 2. The data synthesizing part 2 synthesizes (adds) respective demodulated data outputted from the demodulating parts 1a to 1c and outputs the synthesized (added) data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device suitable for use in a demodulation part for receiving and demodulating a signal in, for example, a cellular telephone.

[0002]

2. Description of the Related Art For example, in a digital cellular telephone, a CDMA (Cord Division Multiple Acces) capable of securing a large number of lines within a predetermined frequency band.
s) method is used as the multiplexing method. C
In the DMA method, a PN (pseudo-random) code is used to spread a modulated signal, which is a narrow band signal, into a wide band signal, that is, a spread spectrum signal is transmitted and received as a transmission signal or a reception signal.

The signal multiplexed by the CDMA system is
Since the interference resistance is high and the resolution is high even in multipaths which normally cause mutual interference (noise), the base station A, which is formed between the cellular phone and the base station as shown in FIG. The direct path P ₁ of the base station, the paths P ₂ and P ₃ reflected by the reflector, and the path P ₄ from another base station B can be distinguished from each other. The higher path is selected and used for communication.

[0004]

However, when the cellular telephone is, for example, a point distant from the base stations A and B shown in FIG. The path selected by the cellular telephone may be the path from the base station A or the base station B. For this reason, the signal received by the cellular telephone becomes a discontinuous signal, and there is a problem that the user feels uncomfortable.

Further, in this case, even though the path having the highest reception level among the paths formed for the cellular telephone is located, since the cellular telephone is located at a point distant from the base stations A and B, The S / N is poor, that is, the received signal contains a lot of noise, and there is also a problem that the user feels uncomfortable.

The present invention has been made in view of such a situation, and is to receive a signal from a base station without interruption and improve the S / N thereof.

[0007]

A demodulator according to claim 1 demodulates a received signal and outputs demodulated data as a plurality of demodulators 1a to 1c and demodulators 1a to 1c. A demodulator having adders 23 and 24 as adding means for adding the demodulated data output from the respective demodulators, wherein each of the demodulators 1a to 1c temporarily stores the demodulated data itself and stores the demodulated data. Of the demodulators 1a to 1c are output in synchronization with the output timing of the demodulated data by the memory 1
7 is provided.

According to a second aspect of the demodulation apparatus, the input validity judging circuit 21a (21b or 21c) as a judging means for judging the validity of the demodulated data, and the input validity judging circuit 2
Based on the determination result of 1a (21b or 21c), the input control circuit 22a (22b) as a control unit that controls the input of the demodulated data output from the demodulation unit 1a (1b or 1c) to the adders 23 and 24. Or 22c) is further provided.

In the demodulating device according to the third aspect, the input control circuit 22a (22b or 22c) determines whether the input validity determining circuit 21a (21b or 21c) determines the result.
0 or demodulated data output from the demodulation unit 1a (1b or 1c) is output to the adders 23 and 24.

In the demodulator according to a fourth aspect of the present invention, the demodulated data is data composed of a predetermined unit such as a frame unit, and the memory 17 provided in the demodulation unit 1a (1b or 1c) stores the demodulated data. It is characterized in that the output of the stored demodulated data is started at a predetermined timing after starting from the data of the delimiter part such as the head part of the frame.

[0011]

In the demodulator according to the first aspect, each of the demodulation units 1a to 1c temporarily stores the demodulation data demodulated by itself, and the demodulation data is stored in the other demodulation units 1a to 1c.
c outputs the demodulated data in synchronization with the output timing. Then, the demodulated data output from each of the demodulation units 1a to 1c is added. Therefore, demodulated data with improved S / N can be obtained.

In the demodulator according to the second aspect, the validity of the demodulated data is judged, and based on the judgment result,
It controls the input of the demodulated data output from the demodulation unit 1a (1b or 1c) to the adders 23 and 24. Therefore, it is possible to prevent the deterioration of the S / N of the demodulated data due to the addition of the ineffective demodulated data having a very bad S / N.

In the demodulator according to the third aspect, the input control circuit 22a (22b or 22c) is set to 0 or the demodulation section 1a (1b or 2b) based on the determination result of the input validity determination circuit 21a (21b or 21c). The demodulated data output from 1c) is output to the adders 23 and 24. Therefore, for example, the S / N of demodulated data due to the addition of ineffective demodulated data having a very poor S / N.
Can be prevented from deteriorating.

In the demodulating device according to the fourth aspect, the demodulated data is data consisting of a predetermined unit such as a frame unit, and the memory 17 included in the demodulating unit 1a (1b or 1c) stores the demodulated data. After starting from the data of the frame delimiter, the output of the stored demodulated data is started at a predetermined timing. Therefore, since the same demodulation data is output from the demodulation units 1a to 1c at the same timing, it is possible to easily obtain demodulation data with good S / N by simply adding them.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a CDM to which the demodulation device of the present invention is applied.
It is a block diagram which shows the structure of one Example of the cellular phone of A system. In a base station (not shown), a signal (voice signal) supplied via another base station connected to the base station or the public network is used as a spread spectrum signal, which is transmitted in, for example, a frame unit, and is transmitted by an antenna of a cellular telephone. Be received.

As described with reference to FIG. 9, for this cellular telephone, a plurality of paths (paths P _{1 to} P ₃ from the base station A in FIG. 9) are formed from _one base station, A path is formed with each of the plurality of base stations (base stations A and B in FIG. 9).

Here, a method of combining a plurality of paths formed with one base station to improve the S / N of the received signal (improvement of speech quality) is diversity (RAKE).
It is called the reception method. A method of combining paths formed with each of a plurality of base stations to improve the S / N of a received signal is called soft handoff.

The cellular telephone shown in FIG. 1 has, for example, three demodulation units 1a to 1c.
Then, among the paths received from the antenna from the plurality of base stations and the paths from each of the plurality of base stations, for example, the same number as the number of the demodulation units 1a to 1c having a high reception level is set to 3 Are demodulated respectively.

That is, for example, as shown in FIG. 9, when paths P _{1 to} P ₄ are formed with respect to the cellular telephone, three of the higher reception levels among them are demodulators 1a to 1c, respectively. Demodulated at. Demodulation unit 1
Each of the demodulated data demodulated by a to 1c is output to the data synthesizing unit 2 together with a deskew data valid signal described later. The demodulated data is demodulated at the demodulators 1a to 1a at a timing based on an address update signal (read address update signal) described later, which is supplied from the data synthesizing unit 2.
It is output from c.

The data synthesizing unit 2 synthesizes (adds) the demodulated data from the demodulating units 1a to 1c and outputs the synthesized data.
As a result, demodulated data with an improved S / N can be obtained.

By the way, the demodulation units 1a to 1c do not always demodulate signals along the same path, and the path is switched according to the reception level, for example, as described above. Further, not all of the demodulation units 1a to 1c are always performing the demodulation operation, but they are designed to operate as necessary (for example, a signal along one path has a sufficient S / N ratio). Is obtained, any one of the demodulation units 1a to 1c
If one of the demodulators 1a to 1c operates, or if it is necessary to add a plurality of demodulated data and earn S / N, two or all of the demodulators 1a to 1c operate.

Therefore, the outputs of the demodulators 1a to 1c may or may not be supplied to the data synthesizer 2. That is, the demodulation units 1a to 1c and the data synthesis unit 2 are, so to speak, connected or disconnected.

On the other hand, the path lengths of the paths P _{1 to} P ₄ formed with respect to the cellular telephone are not usually the same, and the cellular telephone is used while moving unlike the case of a wired telephone. To be done. Therefore, the demodulation units 1a to 1c
In each case, the timing at which the signal is received is different. Therefore, if the received signal is demodulated and output to the data synthesizing unit 2 as it is, the demodulated data at the same timing (bits having the same meaning) are not necessarily required.
Is not always added, and accurate demodulated data may not be obtained.

Therefore, in the data synthesizing section 2, it is possible to add demodulated data at the same timing,
It is necessary to synchronize each of the demodulation units 1a to 1c and the data synthesis unit 2. Further, when the output of the synthesized data (demodulated data) from the data synthesizing unit 2 is stopped when this synchronization is taken, the finally obtained audio signal is interrupted, so that the demodulating units 1a to 1a Each time 1c and the data synthesizing unit 2 are connected as described above, the output of the synthetic data (demodulated data) from the data synthesizing unit 2 must be synchronized without stopping.

Therefore, the demodulators 1a to 1c respectively
It is configured as shown in FIG. 2 and operates as shown in the timing chart of FIG. That is, the signal received by the antenna (received signal) is the demodulator 11 and the delay time detector 1.
3 is supplied. The delay time detector 13 detects the delay time of the received signal along various paths, for example, at the beginning of the frame with respect to a predetermined absolute time, and supplies it to the CPU 12. The CPU 12 identifies the path currently being received based on the delay time supplied from the delay time detector 13. Then, the path of the reception signal to be demodulated by the demodulator 11 is determined, and a demodulation start timing signal for starting the demodulation operation is output to the demodulator 11 together with the path determination signal indicating the path. Further, the CPU 12 has the demodulator 1
The timing generator 14 is notified of the start timing of the frame of the received signal corresponding to the path to be demodulated to 1.

Further, the CPU 12 supplies the same start signal as the demodulation start timing signal output to the demodulator 11 to the control circuit 15, whereby the control circuit 15 has started the demodulation processing of the demodulation circuit 11. Let me know.

The timing generator 14 includes the CPU 1
A demodulation timing signal for demodulating the received signal based on the timing of the head of the received signal notified from 2.
Alternatively, the start timing signal (FIG. 3A) and the write timing signal are generated and output to the demodulator 11 or the control circuit 15, respectively.

The demodulation timing signal means the demodulator 1
1 is a clock for performing demodulation processing, and the start timing signal is, for example, as shown in FIG.
This is, for example, an active high signal indicating the timing of the beginning of the frame of the received signal to be demodulated by the demodulator 11. Further, the write timing signal means the control circuit 1
Reference numeral 5 is a periodic signal for generating a write signal (FIG. 3 (f)) supplied to the write terminal (WR) of the memory 17.

On the other hand, when the path determination signal and the demodulation start timing signal are supplied from the CPU 12, the demodulator 11 starts the demodulation processing of the reception signal of the path represented by the path determination signal. Then, in the demodulator 11, demodulation processing is performed in synchronization with the demodulation timing signal (clock) of a predetermined cycle supplied by the timing generator 14, and the demodulated data is output to the data terminal (DIN) of the memory 17.

Further, the demodulator 11 determines the validity of the demodulated demodulated data, and activates the demodulated data valid signal (FIG. 3B) only when it determines that the demodulated data is valid (in FIG. 3). The demodulated data valid signal is an active high signal), and the CPU 12
And output to the control circuit 15. That is, the demodulation circuit 11
Is, for example, smaller than the level of the received signal being demodulated (for example, smaller than a frame unit (for example, about 400 symbols), for example, 2
The demodulated data valid signal (Fig. 3 (b)) is detected only when the level of the demodulated data such as about 0 symbols is detected and the level is larger than a predetermined threshold value.
Is activated and output to the CPU 12 and the control circuit 15.

While the demodulation circuit 11 determines that the demodulated data is not valid, the non-active (LOW level) demodulated data valid signal (FIG. 3B).
Is output to the CPU 12 and the control circuit 15. In the CPU 12, the demodulation data valid signal is non-effective even if a predetermined time has elapsed after the supply of the demodulation start timing signal to the demodulator 11 was started. When it remains active, the path of the reception signal to be demodulated by the demodulation circuit 11 is changed.

When the control circuit 15 receives the start signal from the CPU 12, that is, when the demodulation process of the demodulator 11 is started, the control circuit 15 receives the start timing signal (FIG. 3A) supplied from the timing generator 14. , The demodulated data valid signal (Fig. 3 (b)) is confirmed, and it is determined whether or not it is active. Then, the control circuit 15
If the demodulation data valid signal is determined to be active at the timing of the start timing signal, the demodulator 11
The deskew data valid signal (FIG. 3 (c)) indicating that the demodulated data output from the output is valid is made active (in FIG. 3, the dequeue data valid signal is an active HIGH signal) and the counter is activated. It outputs to the reset terminals (Reset) of 16 and 18, and the data synthesizer 2 (FIG. 1).

Further, in this case, the control circuit 15 sends the write timing signal from the timing generator 14 to the active LOW write signal (see FIG. 3).
As (f)), while outputting to the memory 17, the write signal is delayed by a predetermined time, for example, the write address update signal of active LOW (FIG. 3D),
Output to the up terminal (UP) of the counter 16.

The counter 16 receives a non-active deskew data valid signal from the control circuit 15 (FIG. 3 (c)).
While receiving, the count value (Fig. 3 (e))
Is reset to, for example, 0 as an initial value, and when the active deskew data valid signal (FIG. 3C) is received, the reset state is released. When the reset state of the counter 16 is released, the counter 16 increments its count value by 1 at the timing when the write address update signal (FIG. 3D) is supplied from the control circuit 15.

Count value of the counter 16 (FIG. 3 (e))
Is output to the write address terminal (WRADDR) of the memory 17 as a write address.

The memory 17 is a FIFO (First In First
Out) and absorbs the timing deviation of the reception signals demodulated by the demodulation units 1a to 1c, and is a memory for 100 μs from the demodulator 11 continuously.
It has a capacity capable of storing demodulated data output during a strong period (about 3 to 4 symbols). And
In the memory 17, at the timing when the write signal is received from the control circuit 15, the address indicated by the write address (count value) from the counter 16 (FIG. 3E) is changed to
Demodulated data from the demodulator 11 is written.

Therefore, in the memory 17, after the demodulated data becomes valid (after the level of the received signal becomes larger than a predetermined threshold value), writing is sequentially performed from the head data of the frame of the valid demodulated data. It will be.

The timing deviation due to the difference in the path paths of the received signals demodulated by the demodulators 1a to 1c is at most about 10 μs, while the frame length of the signal transmitted / received by the CDMA system is about 26 ms. It is a degree. Therefore, the timing of the demodulated data output from each of the demodulators 1a to 1c cannot be shifted by one frame or more. Therefore, if the demodulated data is valid, the demodulator 1
The memory 17 of a to 1c always starts to store the demodulated data from the head data of the same frame.

On the other hand, similarly to the counter 16, the counter 18 uses the count value as an initial value while receiving the non-active deskew data valid signal (FIG. 3C) from the control circuit 15. Reset to 0 and the active deskew data valid signal (see Figure 3
When (c)) is received, the reset state of itself is released. Then, when the counter 18 is released from the reset state, the counter 18 receives, for example, the active LO
The read address update signal of W described later (see FIG.
(G)) is supplied, so that the count value of the counter 16 is chased (see FIG. 3).
(H)) is incremented by 1.

Count value of the counter 18 (FIG. 3 (h))
Is output to the read address terminal (RADDR) of the memory 17 as a read address.

The memory 17 reads the demodulated data written at the address indicated by the read address (count value) (FIG. 3 (h)) from the counter 18 and continues to output it to the data synthesizing section 2. If the demodulated data is not valid and the counter 18 is in the reset state, the memory 1
To 0, 0 is supplied as a read address as an initial value of the count value. Therefore, in this case, the undefined value stored in the address 0 of the memory 17 is continuously output to the data synthesizing unit 2.

Therefore, if the demodulated data output from the demodulator 11 is not valid, an indeterminate value is output from the memory 17. If the demodulated data is valid, the memory 1
The data reading from 7 is performed in the order in which the demodulation data is written in the memory 17, that is, from the head data of the frame of the effective demodulation data.

Here, the count value of the counter 16 or 18 as a write address or a read address for the memory 17 is basically incremented at different timings, but it may be incremented at the same timing. In addition, these count values are the final addresses of the memory 17 (the memory 17
In the address space of (1), when the value becomes the same as the highest address when address 0 is the lowest address, it becomes 0 as the initial value again at the next increment.

The read address update signal for counting up the read address (FIG. 3 (g)) is delayed in time compared with the write address update signal for counting up the write address (FIG. 3 (d)). The read address does not overtake the write address.

Furthermore, in order to prevent the write address that precedes in time from making a round in the address space of the memory 17 and overtaking the read address that follows in time, the write to the memory 17 is performed. If the reading from that is not done for a certain time or more, the CPU 1
2 recognizes that the device is in an abnormal state, stops the output of the write signal to the control circuit 15, and causes the demodulator 11
Stop the demodulation operation of.

As described above, in each of the demodulation units 1a to 1c shown in FIG. 1, the demodulation data from the beginning of the frame is temporarily stored in the memory 17, and then the data synthesis unit 2 at the timing of the read address update signal. Is output to.

Next, the data synthesizing unit 2 of FIG. 1 is configured as shown in FIG. 4, and operates as shown in the flowchart of FIG. 5, for example. The input validity determination circuit 2 shown in FIG.
1a, input control circuit 22a, input validity determination circuit 21
b and the input control circuit 22b, or the input validity determination circuit 21c and the input control circuit 22c are the demodulation unit 1a of FIG.
1 to 1c, and perform the same processing respectively, the input valid determination circuit 21a and the input control circuit 22a among them will be described here.

Further, the input validity judging circuits 21a to 21c.
The data validity determination timing signal supplied to the output signal of the demodulation unit 1a to 1c of FIG.
It is a periodic signal whose timing is the earliest in time but is delayed by a predetermined time, such as about 100 μs, from the timing of the beginning of the frame. Therefore, the data validity determination timing signal is 100 μs when the start timing signal (FIG. 3A) generated by the timing generator 14 (FIG. 2) of each of the demodulation units 1a to 1c has the most advanced phase. It is a signal delayed by a predetermined time such as degree.

The input validity judging circuit 21a is shown in FIG.
At the timing of the active-HIGH data validity determination timing signal as shown in (a), the deskew data valid signal (FIG. 5B) supplied from the demodulation unit 1a is confirmed, and whether or not it is active, That is, the validity of the demodulated data (FIG. 5 (e)) demodulated by the demodulator 1a is determined.

The input validity judging circuit 21a is active high.
When the deskew data valid signal (FIG. 5B) supplied from the demodulation unit 1a is active at the timing of the IGH data validity determination timing signal, the demodulation unit 1a
It is determined that the demodulated data (FIG. 5 (e)) demodulated in step S1 is valid, and the active HIGH input permission signal (FIG.
(C)) is output.

Here, FIG. 5 (e) shows that the demodulation unit 1a which has become valid from the data in the middle of the (f-1) th frame before the leading (0th) data df _{, 0} of the fth frame. The demodulation data of is shown.

When the input validity judging circuit 21a starts outputting the HIGH-level input permission signal, it supplies a clock (composite data latch signal) (FIG. 5 (g)) for causing the latch circuit 25 described later to latch data. The clock output from the clock circuit 26 is delayed by a predetermined time and the read address update signal (see FIG.
(D)) (FIG. 3 (g)) is output to the demodulation unit 1a.

As a result, as described above, the demodulation data is written from the memory 17 of the demodulation unit 1a shown in FIG. 2 in the order in which the demodulation data is written, that is, from the head data of the frame of the effective demodulation data. The data is sequentially read and output to the input control circuit 22a of the data synthesizing unit 2.

As described above, the demodulation units 1a to 1a
The timing deviation of the received signal demodulated by c is about several tens of microseconds at the most, and the start timing signal (the timing of the beginning of the frame of the demodulation data with the most advanced phase among the demodulation units 1a to 1c ( Demodulation data from the demodulation units 1a to 1c (memory 17) at the timing of the data validity determination timing signal (FIG. 5A) delayed by about 100 μs (about 3 to 4 symbols) from FIG. 3A). Of the demodulation units 1a to 1
The count value of the counter 18 is counted up before the effective demodulated data is written to the memory 17 (FIG. 2) of c, and the data stored in the memory 17 is not read as the effective demodulated data. .

As shown in FIG. 5 (f), the input control circuit 22a outputs 0 while the input permission signal (FIG. 5 (c)) is LOW level. This is the input permission signal (Fig.
When (c)) is at the LOW level, the deskew data valid signal (FIG. 5 (b)) is also at the LOW level, and as described above, the counter 18 of the demodulation unit 1a in FIG. 2 is in the reset state. Since the indeterminate value stored at the address 0 is read out as demodulated data from the memory 17 and input to the input control circuit 22a, this indeterminate value is not used by the adders 23 and 24 described later. To do so.

Then, when the input permission signal (FIG. 5 (c)) becomes HIGH level, the input control circuit 22a receives the effective demodulation data (FIG. 5) supplied from the demodulation section 1a (memory 17) as described above. (E)) is output as it is as shown in FIG.

The output of the input control circuit 22a is the adder 23.
Is supplied to. The output of the input control circuit 22b is supplied to the adder 23 in addition to the output of the input control circuit 22a, and these two outputs are added and output to the adder 24. The adder 24 adds the output of the adder 23 and the output of the input control circuit 22c and outputs the result to the latch circuit 24.

Here, the input control circuit 22b or 22c
As in the case of the input control circuit 22a, 0 is output when the demodulation data of the demodulation unit 1b or the demodulation unit 1c is not valid, and the valid demodulation data is output when the demodulation data is valid.

Then, the deskew data valid signal is HI.
In the GH level demodulation units 1a to 1c, the built-in memory 17 (FIG. 2) always stores valid demodulation data from the beginning data of the same frame.

Therefore, of the demodulators 1a to 1c, the effective demodulated data is always supplied from the leading data of the same frame to the input control circuits 22a to 22c at the subsequent stage where the deskew data valid signal is at the HIGH level. It will be. That is, of the demodulation units 1a to 1c, the effective demodulation data of the same timing is supplied to the subsequent input control circuits 22a to 22c whose deskew data valid signal is HIGH level.

From the above, in the adders 23 and 24, of the demodulated data demodulated by the demodulators 1a to 1c, valid data are added at the same timing, and the added data (hereinafter referred to as composite data) is added. , To the latch circuit 25.

In the latch circuit 25, the write signal output from the control circuit 15 of FIG. 2 from the clock circuit 26 (see FIG. 3).
A clock (FIG. 5 (f)) synchronized with (f)) is supplied. Then, the latch circuit 25 latches the combined data output from the adder 24 at the timing of the clock supplied from the clock circuit 26. As a result, from the latch circuit 25, as shown in FIG.
Demodulated data obtained by adding (combining) the demodulated data demodulated in a to 1c at the same timing ... D _{f-1, N- 2} , D
_{f-1, N-1} , D _{f-1, N} , D _{f, 0} , D _{f, 1} , D _{f, 2} , ... (where D _{f, n} is the _nth from the beginning of the fth frame D _{f- 1, N} is the combined data obtained by adding the demodulated data of
The final combined data of the (f-1) th frame) is output.

As described above, as shown in FIG. 6, demodulated data having different timings to be demodulated by the demodulators 1a to 1c are added and output at the same timing in the data synthesizing section 2.

As described above, according to the cellular telephone shown in FIG. 1, effective demodulated data are added at the same timing without stopping the output of the combined data from the data combining section 2, so that the base station can Signal can be demodulated without interruption, and the S / N of the demodulated data can be further improved.

Next, FIG. 7 is a timing chart for explaining the operation when the demodulation data of the demodulation units 1b and 1c is valid and the demodulation data of the demodulation unit 1a is not valid, and the demodulation data becomes valid. Is. In the figure, d
_{f, n} means the n-th data from the beginning (0th) of the f-th frame, and d _{f, N} means the last data of the f-th frame.

First, the demodulated data (FIGS. 7D to 7F) demodulated by the demodulation units 1a to 1c are written in the built-in memory 17 (FIG. 2) and read from the data synthesis unit 2. It is input to the input control circuits 22a to 22c (FIG. 4) at the timing of the address update signal. here,
As described above, this demodulated data is read such that the data at the beginning of the frame is read at the timing of the data validity determination timing signal (FIG. 7 (g)).

When the demodulation data of the demodulation unit 1a is not valid and the demodulation data of the demodulation units 1b and 1c are valid, the data output by the demodulation unit 1a (see FIG. 7).
Since (d) is an undefined value (invalid data), the input control circuit 22a outputs 0 (FIG. 7 (h)), and the input control circuit 2
2b or 22c outputs the demodulated data (effective demodulated data) from the demodulator 1b or 1c, respectively (FIG. 7).
(I) or FIG. 7 (j)).

As a result, the data synthesizer 2 (latch circuit 2
From 5), as described above, the demodulation units 1b and 1
The demodulated data from c is added at the same timing, and the combined data (FIG. 7 (k)) is output.

Next, from the above state, when the demodulated data of the demodulator 1a becomes valid, that is, the demodulator 1 of the demodulator 1a.
When the demodulated data valid signal (FIG. 7 (b)) output from 1 becomes HIGH level, after that timing,
The deskew data valid signal (FIG. 7 (c)) of the demodulation unit 1a is set to HIGH level at the timing when the start timing signal (FIG. 7 (a)) indicating the beginning of the frame of the demodulation data of the demodulation unit 1a becomes HIGH level. It

Deskew data valid signal (FIG. 7 (c))
Is set to the HIGH level, the demodulated data demodulated by the demodulation unit 1a (FIG. 7 (d)) is regarded as valid, and writing to the memory 17 (FIG. 2) built in the demodulation unit 1a is started. .

Then, the deskew data valid signal (see FIG.
Immediately after (c)) becomes HIGH level, at the timing when the data validity determination timing signal (FIG. 7 (g)) becomes HIGH level, the input control circuit 22a replaces 0 which has been output so far, The demodulation data (FIG. 7 (d)) supplied from the demodulation unit 1a is directly output.

As a result, in the data synthesizer 2, the demodulated data output from the demodulators 1a to 1c are added at the same timing from the head data of the frame immediately after the demodulated data of the demodulator 1a becomes valid. The combined data (FIG. 7 (k)) is output.

As described above, when the demodulation data of the demodulation units 1b and 1c are valid and the demodulation data of the demodulation unit 1a is not valid, when the demodulation data of the demodulation unit 1a is valid, the demodulation units 1b and 1c are effective. The effective demodulation data of the demodulation unit 1a is added to the demodulation data without affecting the operation of 1. to generate combined data.

Next, FIG. 8 is a timing chart for explaining the operation when only the demodulation data of the demodulation unit 1a becomes invalid after the demodulation data of the demodulation units 1a to 1c are all valid.

First, the demodulated data (FIGS. 8D to 8F) demodulated by the demodulation units 1a to 1c are written in the built-in memory 17 (FIG. 2) and read from the data synthesis unit 2. It is input to the input control circuits 22a to 22c (FIG. 4) at the timing of the address update signal. The demodulated data is read out as described above so that the head data of the frame is read out at the timing of the data validity determination timing signal (FIG. 8 (g)).

When all the demodulated data of the demodulators 1a to 1c are valid, the input control circuits 22a to 22 are provided.
c (FIG. 4) outputs the demodulated data (effective demodulated data) from the demodulators 1a to 1c, respectively (FIG. 8 (h)).
Through FIG. 8 (j).

As a result, the data synthesizer 2 (latch circuit 2
From 5), as described above, the demodulated data from the demodulation units 1a to 1c ..., D _{f-1, N} , d _{f, 0} , d _{f, 1} ,.
, D, which is the summed data at the same timing
_{f-1, N} , D _{f, 0} , D _{f, 1} , ... (FIG. 8 (k)) are output.

Next, from the above state, when the demodulation data of the demodulation unit 1a becomes invalid, that is, the demodulation data valid signal output from the demodulator 11 of the demodulation unit 1a (see FIG. 8).
When (b)) becomes the LOW level, the deskew data valid signal (FIG. 8) of the demodulation unit 1a is immediately output regardless of the start timing signal (FIG. 8A) indicating the beginning of the frame of the demodulation data of the demodulation unit 1a. 8 (c)) is set to LOW level.

Here, as described above, the demodulated data is
When it becomes valid from invalid, it is necessary to start writing to the memory 17 (FIG. 2) from the timing of the start timing signal immediately after that, that is, from the data at the beginning of the frame. When the data changes from the valid data to the invalid data, the writing to the memory 17 can be stopped without specifying the timing.

Deskew data valid signal (FIG. 8 (c))
Is set to the LOW level, the demodulation data (FIG. 8 (d)) demodulated by the demodulation unit 1a becomes invalid (invalid data), and the data output from it to the input control circuit 22a (FIG. 8 ( Since d)) is an undefined value, the input control circuit 2
2a outputs 0 (FIG. 8 (h)).

On the other hand, the input control circuit 22b or 22c
Continue to output the demodulated data (effective demodulated data) from the demodulator 1b or 1c, respectively (FIG. 8 (i) or FIG. 8 (j)), and as a result, the data synthesizer 2 (latch From the circuit 25), the combined data (FIG. 8 (k)) obtained by adding the demodulated data from only the demodulators 1b and 1c at the same timing is output.

As described above, when the demodulation data of the demodulation unit 1a becomes invalid after the demodulation data of the demodulation units 1a to 1c are all valid, the operation of the demodulation units 1b and 1c is not affected. The demodulated data of the demodulation unit 1a is deleted (set to 0) to generate the synthetic data.

The case where the demodulation device of the present invention is applied to a cellular telephone has been described above, but the present invention can be applied to a demodulation device for demodulating a signal other than the cellular telephone.

In this embodiment, the multiplexing method of the cellular telephone is the CDMA method, but the invention is not limited to this.

Further, in the present embodiment, the cellular telephone having the three demodulation units 1a to 1c has been described, but the number of demodulation units can be three, two, or four or more. However, it is necessary to provide the input validity determining circuit and the input control circuit of the data synthesizing unit 2 according to the number of demodulating units provided in the cellular telephone.

Further, in the present embodiment, the data at the beginning of the frame is stored in the memory 17, but the present invention is not limited to this. Considering a data unit larger than the deviation of the timing of the received signal, the beginning of the data is considered. It is possible to store the data in the memory 17 from the data of the delimiter part such as the end or the end.

[0087]

According to the demodulating device of the first aspect, each of the plurality of demodulating means temporarily stores the demodulated data demodulated by itself, and the other demodulating means outputs the demodulated data. Output in synchronization with timing. Then, the demodulated data respectively output from the plurality of demodulation means are added. Therefore, demodulated data with improved S / N can be obtained.

According to the second aspect of the demodulation device, the validity of the demodulated data is determined, and the input of the demodulated data output from the demodulating means to the adding means is controlled based on the determination result. Therefore, it is possible to prevent the deterioration of the S / N of the demodulated data due to the addition of the ineffective demodulated data having a very bad S / N.

According to the demodulating device of the third aspect, the control means outputs 0 or the demodulated data output from the demodulating means to the adding means based on the determination result of the determining means. Therefore, for example, the S / N of demodulated data due to the addition of ineffective demodulated data having a very poor S / N.
Can be prevented from deteriorating.

According to the demodulating apparatus of the fourth aspect, the demodulated data is data consisting of a predetermined unit, and the synchronizing unit included in the demodulating unit stores the demodulated data in the data of the delimiter portion of the predetermined unit. Then, the output of the stored demodulated data is started at a predetermined timing. Therefore,
Since the same demodulation data is output from a plurality of demodulation means at the same timing, it is only necessary to add them.
Demodulated data with good S / N can be easily obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a cellular telephone to which the present invention has been applied.

FIG. 2 is a more detailed block diagram of a demodulation unit 1a (1b or 1c) in the embodiment of FIG.

FIG. 3 is a timing chart illustrating the operation of the demodulation unit 1a (1b or 1c) shown in FIG.

FIG. 4 is a more detailed block diagram of the data synthesizing unit 2 in the embodiment of FIG.

5 is a timing chart explaining the operation of the data synthesizing unit 2 in FIG.

6 is a diagram showing the relationship between the timing of demodulated data demodulated by the demodulators 1a to 1c of FIG. 1 and the timing of output of synthesized data from the data synthesizer 2.

FIG. 7 is a timing chart illustrating the operation of the device.

FIG. 8 is a timing chart illustrating the operation of the device.

FIG. 9 is a diagram illustrating a path formed in communication of a cellular phone.

[Explanation of symbols]

 1a to 1c Demodulator 2 Data combiner 11 Demodulator 12 CPU 13 Delay time detector 14 Timing generator 15 Control circuit 16 Counter 17 Memory 18 Counter 21a to 21c Input validity determination circuit 22a to 22c Input control circuit 23, 24 Adder 25 Latch circuit 26 Clock circuit

Claims (4)

[Claims] 1. A demodulator having a plurality of demodulation means for demodulating a received signal and outputting demodulation data, and an addition means for adding the demodulation data output from each of the plurality of demodulation means. Each of the plurality of demodulation means includes a synchronization means for temporarily storing the demodulation data demodulated by itself and outputting the demodulation data in synchronization with a timing at which the other demodulation means outputs the demodulation data. A demodulator characterized by. 2. Judging means for judging the validity of the demodulated data, and control means for controlling the input of the demodulated data output from the demodulating means to the adding means based on the judgment result of the judging means. The demodulator according to claim 1, further comprising: 3. The control unit outputs 0 or demodulated data output from the demodulating unit to the adding unit based on the determination result of the determining unit. Demodulator. 4. The demodulated data is data composed of a predetermined unit, and the synchronization unit included in the demodulation unit starts storing the demodulated data from data of a delimiter portion of the predetermined unit, The demodulator according to any one of claims 1 to 3, wherein the output of the stored demodulated data is started at a predetermined timing.