JP3416642B2 - Memory interface circuit and method for writing despread symbols to memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interface circuit and a method for writing despread symbols to a memory. Especially, C that supports multi-rate transmission
The present invention relates to a memory interface circuit and a method of writing information symbols after despreading to a memory, which are applied to a DMA receiver or a CDMA receiver in which a data time period changes due to synchronous tracking.

[0002]

2. Description of the Related Art The ITU (International Telecommunication Union) is developing a world-wide standard for mobile communication, IMT2000, which is one of the IMT2000 compatible standards.
-CDMA (Wide band Code Division Multiple Access)
The scheme was approved.

One of the features of the W-CDMA system is so-called multi-rate transmission, in which the spreading factor of information symbols is changed according to the amount of information to be transmitted.

On the transmitter side, information symbols are spread and modulated by a certain spreading code and then transmitted, and on the receiver side, the same spreading code is multiplied by a despreader and integrated by the number of chips multiplied by one information symbol. By doing so, the information symbol is demodulated. At this time, the number of chips multiplied by one information symbol is the spreading factor, and the transmission method that allows the number of chips multiplied by one information symbol to be variable is multi-rate transmission.

In the case of multi-rate transmission, since the data cycle after spreading (that is, one chip period) is constant, the cycle of the information symbol after despreading changes depending on the spreading factor.

[0006] For example, the amount of information in data communication is much larger than that in voice communication. In such a case, for voice information having a small amount of information, the spread rate is increased to reduce the power per chip to reduce the communication power. on the other hand,
In data communication that requires high accuracy, communication is performed by reducing the spreading factor and reducing the number of integrations required to restore one symbol. That is, in the case of data communication, one symbol period is shortened and many symbols are communicated per unit time.

FIG. 8A shows an example of chip and symbol data periods during multirate transmission.

As in the example shown in FIG. 8A, the number of chips per second (hereinafter, chip rate) is 3.84 Mc.
In the case of ps (chip per sec), the number of symbols per second of information symbols having a spreading factor of 4 (hereinafter, referred to as symbol rate) is 960 ksps (symbol per sec), and one symbol period T2 is about 104 ns.

Similarly, the symbol rate of the information symbol having the spreading factor of 32 is 128 ksps, which is 1 symbol period T.
5 is about 7.81 μs. As described above, the spreading factor is reduced as the amount of information to be transmitted is increased, and the spreading factor is increased as the amount of information is reduced.

By the way, the information symbols despread and demodulated in the receiver are usually processed in a fixed unit such as a slot or a frame (for example, Rake combining processing), and therefore need to be written (stored) in a memory once. There is.

In multi-rate transmission, the symbol rate differs depending on the situation, so the means for storing in the memory is assumed to have the lowest spreading factor, that is, the shortest period of one information symbol after despreading. In general, writing (storing) to the memory is performed at time intervals shorter than that.

Further, in a CDMA receiver in a mobile device, it is necessary to perform synchronization tracking (tracking) so as to prevent loss of synchronization. Delay Lock Loop (Delay Lo
In a tracking circuit using ckedLoop), two sets of correlators are used, and each of the correlators is a code whose phase is advanced by, for example, half a chip based on a spreading code (PN code) used for despreading. (Early code) and a code delayed by half a chip (late code) are injected, and the correlation with those codes is detected. When the reception timing is changed due to such synchronization tracking, the symbol time period seen from the receiver becomes apparently long or short, and in this case as well, the same consideration as the above-mentioned multi-rate transmission is required. . This point will be described with reference to FIG.

The change of the reception timing by the synchronization tracking is as follows.
It is not always performed, but is performed intermittently at a predetermined interval. When the synchronization follow-up operation occurs and the synchronization timing is shifted in a direction that advances in time (that is, when obtaining the correlation with the early code), the period of one symbol at that moment is apparently shorter than usual. That is, when tracking for synchronous tracking occurs, the symbol appears to be shortened (or lengthened), and thus the symbol period changes as in the multirate case.

Therefore, in order to write (store) the information symbol in the memory without leaking it, it is necessary to write in the same time period, assuming that the time of one symbol is shortened by the synchronization follow-up.

That is, as shown in FIG. 8B, assuming that one symbol period is normally "4 chips", it becomes "3.5 chips" in the tracking period, and the normal "4 chips" is assumed.
Timing with "chip" as the cycle (S1, S2, S3)
If data is being written to the memory, data that would otherwise be captured will be missed at the timing of S3. In order to eliminate such inconvenience, it is necessary to write to the memory at intervals of "3.5 chips" from the beginning.

[0016]

In the worst case from the beginning, when a method of writing data into the memory at a cycle matched to the shortest symbol period is adopted, a constant cycle is obtained at any symbol rate. Since the writing is performed by the method, the circuit can be easily configured, but the following problems occur.

First, when data having a high spreading factor (long period of one information symbol) is received, a write operation is performed many times on the same information symbol, resulting in useless processing. Occurs. That is, originally, it is sufficient to generate the memory access only once for one symbol, but if the access is generated at a shorter cycle, the data of the same symbol is written (overwritten) in the memory a plurality of times. As a result, useless processing occurs.

In order to solve this problem, it is conceivable to make the writing cycle variable in accordance with the symbol rate. In this case, the information of the symbol rate is given to the memory interface section so that each memory interface section can obtain the information. Since it is necessary to switch the control method for each symbol rate, control becomes complicated.

Secondly, in the receiver in the mobile device, the data period (one symbol period) may be apparently shortened due to the synchronization follow-up. Therefore, in order to write the information symbol without leakage, a shorter period is required. However, the write operation to the memory must be performed, but since the data cycle is not always shortened, in other cases, wasteful power is similarly consumed. In addition, if the writing cycle is made variable in consideration of the synchronization tracking, the control becomes more complicated.

Such a problem will be described with reference to FIGS. 9 and 10. 9 and 10 are timing charts when the lowest spreading factor is assumed to be "4" and the data period is shortened by one chip due to the synchronous tracking.

In FIG. 9, in the tracking operation, assuming that the data period is shortened by one chip, the information symbol is sampled at a three-chip period even though the information symbol having the spreading factor of 4 is received. FIG. 7 is a diagram showing a timing when performing the above operation and writing the data in the memory.

As shown in the figure, the despread information symbol is output in synchronization with the negative edge (time t1, t4, t6, t8) of the symbol output pulse. During the one symbol period, when a sampling pulse for instructing data acquisition to the memory is output (time t2, t4, t
5, t7, t9), the write enable signal (NWE) changes to low level and becomes active (time t).
3, t5, t6, t8, t10). Then, data is written to the memory while the write enable signal is active.

As described above, in consideration of the fluctuation of the symbol period at the time of tracking, when sampling is performed at a short cycle even in the period in which tracking is not performed, time t in FIG.
At 5 and time t6, the same data (FOB) write access occurs. Access (A) that occurs at time t6 is useless processing.

Similarly, FIG. 10 shows the minimum spreading factor (= spreading factor) of multi-rate transmission when data with a spreading factor of 8 (one symbol consists of 8 chips) is received, despread and stored in the memory. Considering the rate 4), the timing when the sampling pulse is generated every four chips is shown.

In this case, useless access (B1) for writing the same data (FOA) at times t4 and t5
And (B2) occur, and similarly at time t7,
Useless access for writing the same data (FOB) occurs.

As described above, if the method of performing writing at a constant cycle assuming the minimum spreading factor is adopted at any symbol rate, in the case of FIG. 10, at least once every two times is wasted. Processing occurs. Then, the higher the spreading factor, the more the number of unnecessary processes increases, and the spreading factor 25
In the case of 6, 63 of the 64 write processes are wasted.

As described above, even when the spreading factor is high or the synchronous tracking operation does not occur, the spreading factor is the lowest, and the despreading is performed in the time cycle assuming that the data time cycle is shortened in the synchronous tracking operation. Since the subsequent information symbol is written (stored), a wasteful processing amount occurs.
On the other hand, making the write cycle variable according to the symbol rate has a problem that the control becomes complicated.

The present invention has been made on the basis of such a consideration. By eliminating waste of the processing amount of writing symbols to the memory after despreading, the processing amount can be reduced as a whole, and a simpler circuit can be obtained. The purpose is to realize this.

[0029]

According to the present invention, a signal indicating a symbol rate output timing (hereinafter referred to as a symbol output signal) and a signal indicating a sampling timing (data fetch timing) for writing to a memory ( (Hereinafter, referred to as sampling signal), and a write enable flag (write enable signal) to the memory
By masking, the processing amount in the memory can be reduced.

That is, when the information symbol sampled by the sampling pulse is a symbol which has already been written to the memory once and is the same information symbol which does not need to be written by the second and subsequent samplings, a write operation is performed. Mask the enable signal.
As a result of such an operation, it is possible to prohibit the write operation of the same information symbol to the memory cell, and it is possible to completely eliminate the useless operation of the memory cell.

[0031]

According to one aspect of the present invention, the start of the active period of a write enable mask signal is determined based on a symbol output signal indicating the output timing of a received information symbol, and the active period of the write enable signal is determined. Of the sampling signals used for writing the information symbols in a constant cycle when storing the information symbols in the memory, is determined by the sampling signal first output for the same information symbol, The write enable signal becomes active only when the sampling signal is output while the write enable mask signal is active, thereby enabling the writing of the information symbol in the memory.

The write enable mask signal is turned on by the first sampling signal output for the same information symbol. This allows for a second,
Even if the third sampling pulse is output, the activation of the write enable signal is prohibited. The write enable mask is released when the next symbol is output. Therefore, at any symbol rate, write enable is activated and writing is allowed only once for the same information symbol. Therefore, the processing amount can be reduced. In addition, it is possible to completely eliminate wasteful power consumption and
It is possible to extend the service life of the A receiver.

Further, the symbol output signal is a signal which is always provided in the despreading section in order to give an integration end timing after despreading. The sampling pulse is an essential signal for writing data in the memory.
Since a mask signal for write enable is generated by using such a signal naturally required, it can be realized by a simple logic circuit.

Storing the despread data from a plurality of receiving fingers in the memory can be easily realized by time division control by the selector. As the time-division control signal of the selector, for example, the count output of the n-ary counter can be used as it is. The output of this n-ary counter can also be used as a sampling pulse. Therefore, it is possible to realize a CDMA communication rake receiver that allows multi-rate transmission with a simple configuration.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a memory interface circuit according to a first embodiment of the present invention. The configuration and operation of the memory interface circuit in FIG. 1 will be described below.

As shown in FIG. 1, the memory interface circuit 1 is a circuit that receives the information symbol data output from the despreader 2 and outputs the information symbol data to the information symbol storage memory 3. A sampling signal generator 5, a register 6, an NWE mask generator 7,
It is composed of the NWE generator 8. Where "NWE"
Means a write enable signal. N is "negativ
It is an acronym for "e." That is, NWE is
This represents a negative logic write enable signal (WE).

The despreader 2 comprises a complex despreading section 2a and an integrating (sum of products operation) section 2b. The symbol output signal generation unit 4 generates a symbol output signal indicating that the product-sum calculation is completed and the information symbol is demodulated based on the period information and the timing information of the received data, and the integration unit 2b of the despreader 2 is generated. Give to.

The despreader 2 receives the symbol output signal, completes the integration (product-sum operation) of the despread chip, and outputs the demodulated information symbol to the memory interface circuit 1.

The sampling signal generator 5 generates a sampling signal at a constant period that can surely write the information symbol to the memory 3 even when the time period of the information symbol output from the despreader 2 is the shortest, and then to the register 6. Output.

The register 6 holds the information symbol,
The information symbol is output to the memory 3 at the timing of the sampling signal, but since the cycle of the sampling signal is shorter than the cycle of the information symbol, the information symbol is oversampled and output to the memory 3.

By the way, the symbol output signal and the sampling signal are also input to the NWE mask generator 7. NWE
The mask generation unit 7 generates an NWE mask signal (write enable mask signal) based on the symbol output signal and the sampling signal, and the NWE generation unit 8 based on the NWE mask signal, at the timing of the sampling signal NWE.
(Write enable signal) is output to the memory 3.

At this time, when the information symbol sampled by the register 6 is a symbol which has already been written to the memory 3 once and is the same information symbol which does not need to be written by the second and subsequent samplings, NWE is masked so that the write operation to the memory 3 does not occur.

FIG. 2 shows a concrete configuration example of the circuit of the main part of FIG. The NWE mask generation unit 7 is composed of a reset set flip-flop (RSFF) 101, a symbol output pulse is input to the set terminal, and Q is input at this input.
Make the output active (low level). Further, the sampling signal is input to the reset terminal, and the Q output is reset by this input. Therefore, after being reset by the first sampling signal, the reset state is maintained until the next symbol output pulse is input.

The NWE generator 8 is composed of a 2-input NAND gate 103 having an inverter added to one input. The output (NWE) of this NAND gate 103 is N
Only when the sampling pulse is output while the WE mask signal is at low level (active), the signal becomes low level (active).

When the NWE mask signal is high level, N
The output of the AND gate 103 is fixed to the high level (non-active) regardless of the presence or absence of the sampling pulse. Reference numeral 102 is a delay device for timing adjustment.

The memory 3 is provided with a tri-state buffer 104, which is a NW.
When the E signal (write enable signal) is at a high level (inactive), its output is in a high impedance state, and writing to the memory cell 105 is prohibited. That is, only when the NWE signal (write enable signal) is low level (active), the memory cell 10
Write access to 5 becomes possible.

Details of the operation for generating the NWE (write enable signal) will be described with reference to FIGS. 3 and 4.

FIGS. 3 and 4 are views corresponding to FIGS. 9 and 10 described above, respectively, and the conditions are the same. That is, assuming the lowest spreading factor is 4,
Further, in FIG. 3, the time period of the data is 1 due to the synchronous tracking.
The chip is expected to be shorter. Further, in FIG. 4, although a signal in which one symbol consists of 8 chips is actually received, write access to the memory is generated at intervals of 4 chips in consideration of reception of a signal having a minimum spreading factor. It shows the timing when it is made.

First, in FIG. 3, as described above, the information symbols are sampled and written in the memory 3 in a cycle of 3 chips assuming that the time cycle of data is shortened by 1 chip.

The NWE mask signal is output at the timing (time t1, t4, t7, t1) at which the symbol output pulse is output.
It becomes low level (write enable level) at 0). Then, this state is held until the first sampling pulse is output. That is, after the time point (time t2, t5, t9, t11) at which the first sampling pulse is output, the write disable level is maintained, and the state is maintained until the next symbol output signal is output.

The write enable signal (NWE) is the same as the information symbol output from the register 6 to the memory 3,
It is output at the timing of the sampling signal. At this time, the NWE mask signal is referred to, and if the NWE mask signal is the permission level, the write enable signal (NWE) becomes the write permission level. Further, if the NWE mask signal is the write disable level, the write enable signal (N
WE) is a write disapproval level.

By performing the above control, the time t2
Although writing to the memory is permitted at t5, t9, and t11, the access (A) at time t7 is NWE.
Is prohibited because it is high level (write disable level). Therefore, the second access to the same information symbol FOB does not occur. That is, it is possible to eliminate the useless writing process that has occurred in FIG.

Therefore, only in the case of the example of FIG. 3, considering that the time cycle in which the synchronous tracking operation occurs is sufficiently longer than the time cycle of the sampling signal, the processing amount in the memory 3 is about 3 /. The power consumption in the memory 3 can be reduced to about 3/4 as a result.

Similarly, in FIG. 4 as well, the unnecessary accesses (B1), (B2) and (B3) that have occurred in FIG. 10 are prohibited because the NWE becomes the write disable level (in FIG. 4). Times t4, t6, t10). Therefore, it is possible to eliminate unnecessary writing processing.

Therefore, in the example of FIG. 4, the write processing amount in the memory 3 can be reduced to 1/2. The higher the diffusion rate, the greater the processing amount reduction effect, and the processing amount when the diffusion rate is 256 can be reduced to 1/64 as compared with the case before the present invention. As a result, excellent power consumption can be reduced.

Although the write enable level of the NWE mask signal is "L" in FIGS. 3 and 4,
This can be anything. Also, the write permission level is set to L in NWE, but this may be any value. Regarding the NWE generation method, any generation method may be used as long as the condition that the writing is permitted by the symbol output signal and the writing is not permitted by the sampling signal until the next symbol output signal comes thereafter.

In FIGS. 5A and 5B, the diffusion rates "4" to "" are shown.
5A and 5B schematically show a processing amount reduction effect when a 512 "information symbol is received. In FIGS. 5A and 5B, the processing amount when the memory write cycle is a spreading factor of" 4 "is shown. 5A shows the processing amount (power consumption) before the present invention, and FIG. 5B shows the processing amount (power consumption) according to the present invention.

In FIG. 5A, always considering the fluctuation of one symbol period due to the synchronous tracking (tracking) operation,
Since memory access is generated in the minimum chip cycle,
The processing amount (power consumption) is always constant and wasteful.

According to the present invention, as clearly shown in FIG. 5A, the processing amount (power consumption) of the S portion and the T portion is large.
Can be reduced. Here, the S portion is a portion that can be reduced by eliminating useless processing (useless access that occurs in a period in which tracking is not performed) that accompanies memory access in consideration of the synchronous tracking operation.

Further, the T portion is a portion which can be reduced by eliminating unnecessary processing of storing the same symbol in the memory many times when the actually received signal has a high spreading factor.

As is clear from the figure, the higher the diffusion rate, the greater the processing amount reduction effect of the present invention. Speaking only in this example, even when the diffusion rate is 8, the processing amount is at least 1/2 that of the conventional method. In the case of the diffusion rate of 512, the processing amount can be at least 1/128 or less of the conventional one.

As described above, according to the present invention, the processing amount at the time of writing the information symbol after despreading into the memory is optimized in accordance with the spreading factor, so that the power consumption of the CDMA receiver can be reduced. Therefore, it is possible to extend the life of the call time of the mobile phone. In other words, by completely eliminating the wasteful power consumption associated with enabling advanced data communication, the demand for longer life, which is strictly required for mobile phones, is satisfied, and the present invention is used. As a result, a mobile phone compatible with the multirate transmission system is realized.

(Second Embodiment) FIG. 6 is a block diagram of a memory interface circuit according to a second embodiment of the present invention.

The memory interface circuit of the present embodiment receives despread data output from the plurality of receiving fingers F1 to Fn and outputs / writes it to the memory 11. Each reception finger has a despreader (10a
-10n) and the integration part (11a-11n).

The same number of symbol output signal generation units 12a to 12n as the reception fingers and NWE mask generation units 13a to 1 are provided.
3n, selectors 18a and 18b, sampling signal generator 14, register 15, and NWE generator 16
And an n-ary counter section 17.

The difference from the memory interface circuit according to the first embodiment is that the selector sections 18a and 18b and the n-ary counter section 17 are provided, and the selectors are time-division controlled by the output of the n-ary counter. . Regarding the operation, there is a part that overlaps with the first embodiment, so that part is omitted and only the characteristic part will be described.

The n-ary counter 17 counts up at a timing synchronized with the cycle of the sampling signal output from the sampling signal generator 14.

Each symbol output signal generator 12a-12n
The symbol output signal output from is supplied to each of the NWE mask generation units 13a to 13n. Each of the NWE mask generation units 13a to 13n operates in a time division manner with reference to the count value of the n-ary counter 17.

The selector unit 18a refers to the count value of the n-ary counter, switches the input in time division for each count, and selects one of the NWE mask signals (Ma to Mn) output from the NWE mask generation units 13a to 13n. Is output to the NWE generation unit 16.

Similarly, the selector section 18b refers to the count value and selects the output data (Da to Dn) from each reception finger in a time division manner for each count, and the register 15
Output to.

The sampling signal generator 14 also generates a sampling signal at a timing corresponding to each receiving finger and supplies it to the NWE generator 16 and the register 15.

By the above operation, the output data of a plurality of receiving fingers can be written in one memory in a time division manner, which enables the rake combined reception.
Since unnecessary writing processing does not occur for each of the output data of a plurality of fingers, it is possible to effectively reduce the power consumption. (Third Embodiment) In the third embodiment of the present invention, the memory interface circuit shown in the first or second embodiment is replaced by the CDM.
This is an example applied to the A receiver.

The third embodiment of the present invention will be described below with reference to FIG.

The CDMA receiver according to the third embodiment has a receiving antenna 19, a high frequency signal processing section 20 for filtering at a predetermined frequency and demodulating into a baseband signal, and an A / D conversion for converting an analog signal into a digital signal. Part 21
A searcher 22 for acquiring synchronization of reception timing and synchronization tracking; a despreading unit 23 for despreading a received signal at predetermined timing to demodulate data; and a control for writing information symbols after despreading to a memory. Form 1 or 2
A memory interface section 24 including any one of
A memory 25 for accumulating information symbols; a synchronous detection / rake combining unit 26 for performing RAKE combining after estimating the phase of the information symbols for each multipath path and performing synchronous detection;
It is composed of a channel codec unit 27 that performs channel decoding.

The received signal is demodulated into a baseband signal in the high frequency signal processing section 20, A / D converted and converted into digital data, and then input to the despreading section 23. In the despreading unit 23, the despreader for the desired number of multipaths and the number of multiplex codes despreads and demodulates the data. The demodulated data is stored in the memory 25 via the memory interface unit 24, and then the synchronous detection /
The rake combining unit 26 compensates the phase for each of the multipaths, performs rake combining, and the channel codec unit 27 performs channel decoding.

The memory interface section 24 has the same structure as that of the first or second embodiment, and thus the power consumption of the entire mobile phone can be reduced. Also,
The memory interface unit 24 can be configured by a simple logic circuit that uses a general-purpose signal in a circuit around the memory without relying on control by a higher-level device (upper layer), so that the circuit configuration is simple and the size of a mobile phone is small. It does not hinder the conversion.

[0077]

INDUSTRIAL APPLICABILITY As described above, the present invention is applied to a multi-rate compatible CDMA receiver or a CDMA receiver in which the time period of data changes due to synchronous tracking, and the information symbols after despreading are applied. As a method of writing to the memory, by always writing (storing) the same information symbol to the memory only once at any symbol rate, it is possible to completely eliminate unnecessary writing processing. It is possible to realize it with a simpler circuit. Further, even when the time period of the data is shortened by the synchronous tracking, it is possible to completely eliminate the unnecessary writing process. Therefore,
The processing amount (power consumption) can be efficiently reduced as a whole.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory interface circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of a main part of the memory interface circuit according to the first embodiment.

FIG. 3 is a timing chart showing an operation in the memory interface circuit according to the first embodiment when a write access to a memory is performed in a 4-chip cycle in consideration of a tracking operation.

FIG. 4 is a diagram illustrating a case where write access to a memory is performed in a 4-chip cycle in consideration of a minimum spreading factor in the memory interface circuit according to the first embodiment when data of 1 chip includes 8 chips. Timing diagram showing the operation of

FIG. 5A is a diagram showing a processing amount (power consumption) corresponding to a spreading factor in the memory interface circuit before the present invention. (B) A processing amount (consumption amount) corresponding to the spreading factor in the memory interface circuit of the present invention. Power)

FIG. 6 is a block diagram of a memory interface circuit according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing the configuration of a CDMA receiver using the memory interface circuit of the present invention.

FIG. 8A is a diagram for explaining a difference in symbol period due to a difference in spreading factor during multirate transmission, and FIG. 8B is a symbol period variation due to a tracking operation.
Diagram for explaining the inconveniences associated with

FIG. 9 is a timing chart for explaining that useless processing occurs when a memory access corresponding to synchronization tracking is performed without using the present invention.

FIG. 10 is a timing diagram for explaining that useless processing occurs when receiving data having a high spreading factor without using the present invention.

[Explanation of symbols]

1 Memory interface circuit 2 despreader 3 memory 4 symbol output signal generator 5 Sampling signal generator 6 registers 7 NWE mask generator 8 NWE generator

Claims (6)

(57) [Claims] 1. Information received when a CDMA communication signal adopting a multi-rate transmission system in which a spreading rate of information symbols is changed according to the amount of communication information is received, despread and stored in a memory. The writable period to the memory is controlled based on the symbol output signal indicating the output timing of the symbol and the sampling signal which is first output for one information symbol and which instructs the data to be taken into the memory. A method of writing a symbol after despreading into a memory, which is characterized in that 2. When receiving a signal of a CDMA communication adopting a multi-rate transmission system in which a spreading rate of an information symbol is changed according to the amount of information in the communication, despreading and storing the signal in the memory, Write enable / disable is controlled by a write enable signal, and a period during which the write enable signal is active is controlled by using a write enable mask signal. The start of the active period of the write enable mask signal is received. And the end of the active period of the write enable mask signal is used for writing the information symbols at a constant cycle when storing the information symbols in the memory. First of all the sampled signals for the same information symbol The write enable signal is activated only when the sampling signal is output while the write enable mask signal is active. The method of writing a symbol after despreading to a memory, which enables writing of the information symbol of 1. 3. A symbol output signal generator that generates a symbol output signal in synchronization with a cycle of a received information symbol that changes depending on the amount of communication information, and information is stored at a constant cycle when the information symbol is stored in a memory. A sampling signal generation unit that generates a sampling signal used for writing a symbol, a write enable mask generation unit that generates a write enable mask signal using the symbol output signal and the sampling signal, the sampling signal and the write And a write enable signal generation unit that generates a write enable signal for permitting writing to the memory by using the enable mask signal. 4. The write enable mask generator according to claim 3, wherein the write enable mask generator determines the start of the active period of the write enable mask signal based on the symbol output signal, and outputs the same information symbol first. The write enable signal generator determines the end of the write enable signal according to the sampling signal, and the write enable signal generator is configured to perform the write enable only when the sampling signal is output during the active period of the write enable mask signal. A memory interface circuit, characterized in that a signal is made active, thereby making it possible to write an information symbol to the memory. 5. The counter unit according to claim 3, wherein the counter unit counts in synchronization with the sampling signal output from the sampling signal generation unit, and the data of a plurality of despreaders is determined by the counter value of the counter unit. A memory interface circuit characterized in that a plurality of despreader output data are written in a single memory in a time division manner by further providing a selector section for selecting. 6. A reception antenna, a high-frequency signal processing unit for filtering at a predetermined frequency and demodulating into a baseband signal, an A / D conversion unit for converting an analog signal into a digital signal, synchronization acquisition and synchronization tracking of reception timing. 6. A searcher for performing the above-described operation, a despreading section for despreading a received signal at a predetermined timing to demodulate data, and write control of information symbols after despreading into a memory are controlled. A memory interface circuit, a memory for accumulating information symbols, a phase of the information symbols is estimated for each multipath path, and coherent detection is performed, and then a coherent detection / rake combining unit for Rake combining and channel decoding are performed. And a channel codec section.