JPH0766416A - Insulated-gate transistor and its manufacture - Google Patents

Abstract

PURPOSE:To prevent the sticking of a picture image due to parasitic capacitance between a gate and a drain, by forming an insulating layer as an etching stopper by selectively etching an amorphous silicon layer containing impurities. CONSTITUTION:A gate insulating film 24, amorphous silicon 25, and an amorphous silicon layer 26 containing a lot of impurities are deposited. After photosensitive resin 28 is stuck, a photosensitive resin pattern 28' having an aperture part 30 slightly narrower than a gate pattern 11 is formed by irradiation of ultraviolet rays 29. The amorphous silicon layer 26 containing impurities is turned into a silicon oxide layer by anodic oxidation in a dark room. A silicon oxide layer 31 slightly narrower than the gate pattern is selectively formed on only the gate 11. The amorphous silicon layer 26 containing impurities is selectively eliminated, island parts 25', 26' are formed, the gate insulating layer 24 is exposed, and a source wiring 12 and a drain wiring 23 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel having an image display function, and more particularly, to an insulated gate transistor which is effective in a liquid crystal image display device using a thin film type insulated gate transistor as a switching element on one substrate, and its The present invention relates to a manufacturing method.

[0002]

2. Description of the Related Art Due to recent advances in microfabrication technology, liquid crystal materials, packaging technology, etc., although the size is about 3-15 inches, television images and various image displays that are practically usable on liquid crystal panels are commercially available. Already obtained. A so-called active type liquid crystal panel in which a color display is easily realized by forming a colored layer of RGB on one of two glass plates constituting the liquid crystal panel, and a switching element is incorporated for each picture element. Guarantees images with low crosstalk and a high contrast ratio.

In such a liquid crystal panel, a matrix organization of 120-960 scanning lines and 240-2000 signal lines is standard. For example, as shown in FIG. 4, the liquid crystal panel 1 is constructed. Of the chip-on-glass (C
OG) method or a method of fixing a connection film 4 having a terminal group (not shown) of gold-plated copper foil based on, for example, a polyimide-based resin thin film while being pressed against the electrode terminal group 5 of the signal line with an adhesive. An electric signal is supplied to the image display unit by mounting means such as. Here, for convenience, two mounting methods are illustrated at the same time, but it goes without saying that either mounting method is actually selected. Numerals 7 and 8 are wiring paths for connecting between the image display portion in the center of the liquid crystal panel 1 and the electrode terminal groups 5 and 6 of the signal line and the scanning line, which are not necessarily made of the same conductive material as the electrode terminal group. There is no.

Reference numeral 9 is another glass plate having a transparent conductive counter electrode which is common to all liquid crystal cells, and two glass plates 2 and 9 are spacers such as quartz fiber and plastic beads. Are formed with a predetermined distance of about several μm, and the gap is a closed space sealed with a sealing material made of an organic resin and a sealing material, and the closed space is filled with liquid crystal. ing. To realize color display,
On the closed space side of the glass plate 9, an organic thin film containing one or both of a dye and a pigment called a colored layer is applied to provide a color display function, and in that case, the glass substrate 9 is also called a color filter. be called. Depending on the properties of the liquid crystal material, a polarizing plate is attached to either the upper surface of the glass plate 9 or the lower surface of the glass plate 2 or both surfaces thereof, and the liquid crystal panel 1 functions as an electro-optical element.

FIG. 5 is an equivalent circuit diagram of an active liquid crystal panel in which an insulated gate transistor 10 is arranged as a switching element for each pixel. The element drawn by the solid line is formed on one glass substrate 2, and the element drawn by the broken line is formed on the other glass substrate 9. Scan line 11
(8) and the signal line 12 (7) use, for example, amorphous silicon (a-Si) as a semiconductor layer and a silicon nitride layer (SiN).
x) as a gate insulating film TFT (thin film transistor)
It is formed on the glass substrate 2 simultaneously with the formation of 10. The liquid crystal cell 13 includes a transparent conductive picture element electrode 14 formed on the glass substrate 2, a transparent conductive counter electrode 15 formed on the color filter 9, and a closed glass plate composed of two glass plates. It is composed of a liquid crystal 16 that fills the space and is electrically treated like a capacitor. Several configurations can be selected for the configuration of the storage capacitor. For example, in FIG. 5, the storage capacitor 22 is composed of the gate (scanning line) at the previous stage and the pixel electrode 14.

In FIG. 5, the storage capacitor 22 is not always an indispensable constituent element for an active type liquid crystal panel, but the utilization efficiency of the driving signal source is improved, the disturbance of the stray parasitic capacitance is suppressed, and at the time of high temperature operation. It is effective in preventing image flicker and is practically used.

FIG. 6 is a sectional view of a main part of a color liquid crystal image display device. As described above, the colored layer 18 made of the dyed photosensitive gelatin or the colored photosensitive resin has RGB colors corresponding to the pixel electrodes 14 on the closed space side of the color filter 9.
The three primary colors are arranged according to a predetermined arrangement. The counter electrode 15 common to all the pixel electrodes 14 is formed on the colored layer 18 as shown in order to avoid the voltage distribution loss due to the presence of the colored layer 18. The polyimide resin thin film layer 19 having a film thickness of, for example, about 0.1 μm, which is attached to the two glass plates in contact with the liquid crystal 16, is an alignment film for aligning liquid crystal molecules in a predetermined direction. In addition, when the twisted nematic (TN) type liquid crystal 16 is used, two polarizing plates 20 are required above and below.

When a low-reflectivity opaque film 21 is arranged at the boundary between the RGB colored layers 18, the signal lines 12 on the glass substrate 2 are arranged.
It is possible to prevent the reflected light from the wiring layer such as, and improve the contrast ratio, and to prevent the increase of the leak current at the time of OFF due to the external light irradiation of the switching element 10, and it is possible to operate even under the strong external light. It has been put to practical use as a black matrix. There are many possible configurations of the black matrix material, but considering the occurrence of steps at the boundaries of the colored layers and the light transmittance, the cost will increase, but it will be 0.1.
A Cr thin film having a thickness of about μm is simple.

Incidentally, in order to simplify understanding in FIG. 6, in addition to the thin film transistor 10, the scanning line 11, and the storage capacitor 22, main factors such as a light source and a spacer are omitted. Reference numeral 23 is a conductive thin film for connecting the pixel electrode 14 and the drain of the thin film transistor 10 and is generally formed of the same material as the signal line 12 at the same time. Although not shown here, the counter electrode 15 is connected to an appropriate conductive pattern on the TFT substrate 2 via an appropriate conductive paste at a corner slightly outside the image display portion, and the electrode terminal group 5 is formed. , 6 to provide electrical connection.

It is difficult to say that the insulating gate type transistor, which is a switching element, has been industrially standardized in terms of material and process. However, FIG. 7 shows one typical example. The plane pattern arrangement drawing is shown. Here, the storage capacitor 22 is composed of the preceding scanning line 11 ′ and the pixel electrode 14. 8 is a process sectional view taken along line AA of FIG. 7, and the manufacturing process of the TFT substrate for liquid crystal image display including the insulating gate type transistor will be described below.

First, as shown in FIG. 8A, a metal layer 11 serving as a gate electrode of an insulated gate transistor and a scanning line is formed on one main surface of the glass substrate 2 by a vacuum film forming apparatus such as sputtering. Using 0.1 μm thick chromium (C
In step r), deposition is performed to perform selective pattern formation.

Next, as shown in FIG. 8B, a silicon nitride layer (SiNx) to be the gate insulating layer 24, an amorphous silicon (a-Si) layer 25 containing almost no impurities, and a large amount of impurities. Amorphous silicon layer (n ⁺ a-Si) containing 26
Of the three layers of, for example, 0.4-
It is continuously deposited with a film thickness of 0.05-0.05 μm.

Then, as shown in FIG.
The amorphous silicon layer is selectively formed in an island shape in the vicinity of the gate 11 to form 25 'and 26'.
Expose.

Although this position is not always optimum in the manufacturing process, as shown in FIG. 8D, a transparent conductive film having a film thickness of 0.1 μm is formed by using a vacuum film forming apparatus such as sputtering. ITO is applied and selective pattern formation is performed to form pixel electrodes 14.

After that, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connection to the scanning line 11, and then, as shown in FIG. Chromium (Cr) having a film thickness of 0.1 μm including the above openings
And a gate wiring (not shown) formed of two layers of aluminum (Al) with a thickness of 0.5 μm and a pair of source / drain wiring 1
2 and 23 are selectively deposited so as to overlap a part of the gate 11, and as shown in FIG. 8F, the wiring is used as a mask to form an island-shaped amorphous silicon layer 25 'containing no impurities.
The insulating gate type transistor is completed by selectively removing the amorphous silicon layer 26 'containing the above impurities.

FIG. 9 shows another typical plane pattern layout. Here again, the storage capacitor 22 is composed of the preceding scanning line 11 ′ and the pixel electrode 14. A sectional view taken along the line AA 'of FIG. 9 is shown in FIG. 10, and the manufacturing process of the liquid crystal image display TFT substrate including the insulating gate type transistor will be described below.

First, as shown in FIG. 10A, a metal layer 11 which also serves as a gate electrode of an insulated gate transistor and a scanning line is formed on one main surface of the glass substrate 2 by a vacuum film forming apparatus such as sputtering. Using 0.1 μm thick chromium (C
In step r), deposition is performed to perform selective pattern formation.

Next, as shown in FIG. 10B, a first silicon nitride layer (SiNx) to be the gate insulating layer 24,
The first amorphous silicon (a-S containing almost no impurities)
i) The three layers of the layer 25 and the second silicon nitride layer (SiNx) 27 serving as the etching stopper are, for example, 0.4-
It is continuously deposited with a film thickness of 0.05 to 0.1 μm using a plasma CVD apparatus.

Then, as shown in FIG. 10C, the second SiNx layer, which is thinner than the gate and is selectively left on the gate 11, is 27 ', and the first amorphous silicon layer containing no impurities is formed. After exposing 25, a second amorphous silicon layer 26 containing, for example, phosphorus (P) as an impurity is deposited on the entire surface.

Subsequently, as shown in FIG. 10D, the two amorphous silicon layers are selectively formed in the shape of islands around the gate 11 to form islands 25 'and 26', and the gate insulating layer 24 is formed.
To expose. Further, although this position is not always optimum in the manufacturing process, a transparent conductive ITO film having a film thickness of 0.1 μm is deposited using a vacuum film forming apparatus such as a sputtering device to selectively form a pattern. The pixel electrode 14 is formed.

After that, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connecting to the scanning line 11, and then, as shown in FIG. Chromium (Cr) with a film thickness of 0.1 μm including the opening
And a gate wiring (not shown) formed of two layers of aluminum (Al) with a thickness of 0.5 μm and a pair of source / drain wiring 1
2 and 23 are selectively deposited so as to partially overlap the second SiNx layer 27 ', and the impurities on the second SiNx layer 27' are used as a mask as shown in FIG. By selectively removing the second amorphous silicon layer 26 ′ containing silicon, an insulating gate type transistor is completed. In removing the second amorphous silicon layer 26 ′, it is difficult to increase the selection ratio with respect to the first amorphous silicon layer 25 ′, and it is usually due to over-etching of the amorphous silicon layer 26 ′. The first amorphous silicon layer 25 'disappears, and the amorphous silicon layer exists only directly under a part of the source / drain wirings 12 and 23 in the plan view shown in FIG. Second SiNx
Since the layer 27 'has a function of protecting the amorphous silicon layer 25' which does not include impurities serving as a channel of the insulated gate transistor against over-etching of the amorphous silicon layer 26 ', it is an etching stopper. Often referred to as.

In the two manufacturing methods described above, two types of amorphous silicon layers are formed in an island shape to expose the gate insulating layer, and then an opening for connecting to a gate (scan line) is formed. Is being carried out, but the manufacturing process (especially the photo-etching process)
It is also possible to form the opening by etching a multilayer of two types of amorphous silicon layer and gate insulating layer at once without forming the amorphous silicon layer in an island shape for the purpose of shortening Is. Although the formation of the opening becomes slightly complicated by etching the multilayer film, and there is a problem that it is more reliable to use dry etching, but the process of forming the amorphous silicon layer in an island shape This is because the can be omitted. However, in the latter case, in consideration of the opacity of the amorphous silicon layer, the pixel electrode is formed after the unnecessary amorphous silicon layer between the wirings is removed by using the gate wiring and the source / drain wiring as a mask. It's easy to understand.

In the above two examples, the storage capacitor 22 has a structure in which the scanning line 11 'and the pixel electrode 14 in the preceding stage are used as electrodes and the gate insulating layer 24 is used as an insulator. Further, in order to improve the reliability of the active liquid crystal panel, it is common to further form an insulating layer such as SiNx for ensuring a passivation function after the completion of the above-mentioned insulated gate transistor, but the details will be described here. Omit it. In order to improve the heat resistance of the insulating gate type transistor, Cr is used as a heat resistant barrier metal between the source / drain wirings 12 and 23 and the amorphous silicon layer 26 'containing impurities.
In addition, a metal thin film layer such as Ti (titanium) or a silicide thin film layer is often used. Details of the heat-resistant barrier metal technology are also omitted here.

[0024]

In any of the insulated gate transistors introduced as a prior art example, since the source / drain wiring is formed to partially overlap the gate in a plane, the gate / source and the gate / drain are Parasitic capacitance is generated in. Moreover, since the degree of overlap is determined by the alignment accuracy in the exposure process, when the screen size becomes large, it is restricted by 1) mask accuracy, 2) aligner accuracy of the exposure machine, and 3) thermal contraction and thermal expansion of the glass substrate. It is not unusual for the total alignment accuracy to reach several μm. The parasitic capacitance between the gate and the source increases the signal line capacitance, resulting in an increase in power consumption, and the parasitic capacitance between the gate and the drain modulates the potential of the pixel electrode with a gate pulse to print an image or to expose a device. If a stepper is used as the screen joint, any of them will cause serious quality defects. Therefore, together with the improvement of the aperture ratio for securing a bright screen, a self-aligned TFT having a small parasitic capacitance is desired. There is.

Further, due to the structure of the insulated gate transistor,
It will be easily understood by comparing both of FIGS. 8 and 10 that the manufacturing process shown in FIG. 8 is shorter. However, the step of etching only the amorphous silicon layer containing impurities to leave the amorphous silicon layer containing no impurities is extremely difficult to control because the selection ratio is small, and practically no impurities are included. Under the present circumstances, a crystalline silicon layer is deposited to a thickness of 0.2 μm or more so as to have a considerable margin against over-etching of an amorphous silicon layer containing impurities. Therefore, the generation of particles in the plasma CVD apparatus greatly affects the yield, and the etching of the amorphous silicon layer containing impurities has to be dry etching in order to ensure uniformity. . On the other hand, in FIG. 10, the plasma CVD apparatus forms three layers (SiNx, a-S).
i, SiNx) and n ⁺ a-Si formation, a total of two units are required, and although there is a problem that the photo-etching process for forming the etching stopper and the SiNx etching process increase, there is no impurity. As described above, the crystalline silicon layer can be thinly deposited, and it is not difficult to control the etching of the amorphous silicon layer containing impurities, and the production management is relatively easy.

[0026]

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and an amorphous layer containing impurities is formed instead of forming an insulating layer as an etching stopper by plasma CVD as in the conventional case. This problem is avoided by selectively oxidizing the silicon layer to form it. Further, in order to reduce the parasitic capacitance between the gate and the source / drain, the selective mask formation in the oxidation step is carried out in a self-aligned manner by backside exposure using a gate pattern.

[0027]

The photosensitive resin pattern self-aligned by the back surface exposure using the gate pattern can have almost the same width as the gate. Therefore, the photosensitive resin pattern is used as a mask to form an amorphous layer containing no impurities. In order to selectively anodize the amorphous silicon layer containing impurities on the high-quality silicon layer and convert it into a silicon oxide layer, unlike the conventional mask alignment using an exposure machine, the planar overlap with the gate is extremely large. It became possible to form small source and drain.

[0028]

Embodiments of the present invention will be described below with reference to FIGS. For the sake of convenience, the same parts are given the same numbers as in the conventional example.

In the first embodiment of the present invention, first, as shown in FIG. 1A, a metal layer 11 serving as a gate electrode of an insulated gate transistor and a scanning line is formed on one main surface of a glass substrate 2. Is deposited with chromium (Cr) having a film thickness of 0.1 .mu.m using a vacuum film forming apparatus such as sputtering to form a selective pattern.

Next, as shown in FIG. 1B, a silicon nitride layer (SiNx) to be the gate insulating layer 24, an amorphous silicon (a-Si) layer 25 containing almost no impurities, and a large amount of impurities. Amorphous silicon layer (n ⁺ a-Si) containing 26
3 layers are sequentially deposited with a film thickness of 0.4-0.05-0.05 μm.

Then, as shown in FIG. 1C, after the negative type photosensitive resin 28 is applied on the entire surface, ultraviolet rays 29 are irradiated from the rear surface of the glass substrate 2 and the upper surface of the glass substrate 2 is usually exposed. In combination with the exposure using the photomask of
As shown in (d), it is slightly smaller than the gate pattern (about 0.5 to 1 μm) corresponding to the pattern of the gate 11.
A photosensitive resin pattern 28 'having an opening 30 having a narrow width is obtained. In the exposure process, a region where the photosensitive resin 28 is removed is secured in the peripheral region of the glass substrate 2 by an appropriate treatment, and the region is sandwiched by a clip or the like to perform anodization in the chemical conversion liquid.

The amorphous silicon layer containing no impurities has almost no electrical conductivity in a dark place, but has electrical conductivity due to photoexcited electrons in a bright place. On the other hand, the amorphous silicon layer containing impurities can be selectively anodized only by using the property that the amorphous silicon layer containing impurities always has electrical conductivity regardless of light and dark.

Specifically, when anodization is performed in a dark place, due to the difference in conductivity, only the amorphous silicon layer containing impurities is anodized to become a silicon oxide layer. An amorphous silicon layer containing 500 Å impurities has a formation voltage of 100 if constant voltage formation.
It becomes a 1000 Å silicon oxide layer at V. After the formation current converges to a steady value, a bright light of about 10.000 lux is irradiated to add anodic oxidation for about 1 to 3 minutes to oxidize the amorphous silicon layer containing no impurities to only a few tens of liters. Good results are obtained. This is because the trace amount of impurities (P) diffused from the amorphous silicon layer containing impurities into the amorphous silicon layer containing no impurities is taken into silicon oxide, and the electrical conductivity of the amorphous silicon layer containing no impurities is increased. This is a treatment for increasing the purity.

After the anodization is completed, the state where the photosensitive resin pattern 28 'is removed is shown in FIG. 1 (e). Only on the gate 11 is 0.5 to 1 μm than the gate pattern.
The thin silicon oxide layer 31 can be selectively formed.

Thereafter, as shown in FIG. 1 (f), the two amorphous silicon layers are selectively removed to form islands 25 ', 2'.
6 ', and the gate insulating layer 24 is exposed. As described above, this position is not always optimal in the manufacturing process, but a transparent conductive ITO film having a film thickness of 0.1 μm is deposited using a vacuum film forming apparatus such as sputtering to selectively form a pattern. , The pixel electrode 14 is formed.

After that, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connecting to the scanning line 11, and then, as shown in FIG. A gate wiring (not shown) is formed on the gate insulating layer 24 including the opening portion, a source wiring 12 is formed on the gate insulating layer 24 including the amorphous silicon layer 26 ′ containing impurities, and a non-containing source wiring 12 is also formed. The drain wiring 23 is formed on the gate insulating layer 24 including the crystalline silicon layer 26 'and a part of the pixel electrode 14, for example, chromium (Cr) having a thickness of 0.1 μm and aluminum (having a thickness of 0.5 μm). By selectively depositing with a wiring consisting of two layers of Al), the insulating gate type transistor according to the first embodiment is completed. Here, the source / drain wirings 12 and 23
Is designed not to overlap with the gate 11 in a plane to reduce the parasitic capacitance.

In the first embodiment, the source / drain wiring 1 is formed on the entire surface of the amorphous silicon layer 26 'containing impurities to be the source / drain of the insulated gate transistor.
Since Nos. 2 and 23 are formed, there is a limit in reducing the source / drain resistance. Therefore, in the second embodiment of the present invention, the overlap between the source / drain wiring and the amorphous silicon layer containing impurities is accurately increased by backside exposure using a gate pattern for forming the source / drain wiring. Will be described as a second embodiment.

In the second embodiment of the present invention, the same manufacturing process is performed up to FIG. 1 (f) of the first embodiment.
The scanning line 11 is formed by selectively removing a part of the gate insulating layer 24.
After forming an opening (not shown) for connection to the positive electrode, a positive photosensitive resin 32 is formed on the entire surface as shown in FIG.
2 is applied, exposed from the back surface of the glass substrate 2 and developed, a photosensitive resin pattern 32 'corresponding to the pattern of the gate 11 can be obtained as shown in FIG.

The width of the photosensitive resin pattern 32 ′ obtained in this back surface exposure is larger than that of the silicon oxide layer 31 and smaller than that of the gate 11 (about 0.5 to 1 μm as in the first embodiment). It is necessary.
Because, if the former condition is not satisfied, the silicon oxide layer 3
The source / drain wirings to be formed later are overlapped on 1 to increase the parasitic capacitance, and if the latter condition is not satisfied, the source / drain wirings become amorphous silicon layer 26 'containing impurities. This is because the length formed in parallel becomes shorter and the source / drain resistance becomes higher.

After the photosensitive resin pattern 32 'is formed, for example, two layers of chromium (Cr) having a film thickness of 0.1 μm and aluminum (Al) having a film thickness of 0.5 μm are used by a vacuum film forming apparatus such as sputtering. To cover the entire surface. Since it is easy to set the thickness of the photosensitive resin pattern 32 ′ to 1 μm or more, the photosensitive resin pattern 3 ′ can be removed together with the removal of the photosensitive resin pattern 32 ′.
After selectively removing the Cr / Al laminated portion on 2'by lift-off, the gate wiring (not shown) and the source / drain wirings 12 and 23 are subjected to normal photolithography as shown in FIG. 2 (c). The insulating gate type transistor according to the second embodiment is completed by adopting the steps to selectively form it.

In the third embodiment of the present invention, a silicide layer is formed on the entire surface of the amorphous silicon layer 26 'containing impurities to further reduce the source / drain resistance. Is described below.

In the third embodiment of the present invention, the same manufacturing process is performed up to FIG. 1 (e) of the first embodiment.
After that, as shown in FIG. 3A, a refractory metal layer 33 such as tantalum, tungsten, molybdenum, chromium, or titanium capable of forming silicide is formed on the entire surface by, for example, 0 using a vacuum film forming apparatus such as sputtering. Deposition with a thickness of 1 μm. Thereafter, when the glass substrate 2 is heated to a temperature of 200 ° C. or higher, a large amount of hydrogen containing the impurity-containing amorphous silicon layer 26 and the refractory metal layer 33 is contained in the impurity-containing amorphous silicon layer 26. While the silicide is formed at a low temperature of 200 ° C. or higher, the refractory metal layer 3
Since the silicon oxide layer 31 does not react with the silicon oxide layer 31, if the unnecessary refractory metal layer on the substrate 2 is removed after the silicide layer is formed, the silicide layer is selectively formed on the surface of the amorphous silicon layer 26 containing impurities. And it can be formed in a self-aligned manner.

Subsequently, as shown in FIG. 3B, a silicide layer 34, an amorphous silicon layer 26 'containing impurities, and an amorphous silicon layer 25' containing no impurities are formed in an island shape to form a gate insulating layer. Expose 24. Although this position is not always optimum in the manufacturing process, a transparent conductive ITO film having a film thickness of 0.1 μm is formed by using a vacuum film forming apparatus such as sputtering.
To form a selective pattern on the pixel electrode 14
To form. Since the drain made of the silicide layer has a low resistance value, the pixel electrode 14 may be formed to include the drain.

After that, as shown in FIG. 3C, a part of the gate insulating layer 24 is selectively removed to form an opening (not shown) for connection to the scanning line 11, and then, A gate wiring (not shown) is formed on the gate insulating layer 24 including the opening, and a source wiring 12 is formed on the gate insulating layer 24 including the silicide layer 34 serving as a source. (Cr) and aluminum with a thickness of 0.5 μm (A
The insulating gate type transistor according to the third embodiment is completed by selectively depositing with the wiring consisting of two layers of l).

As described above, according to the present invention, since the source / drain made of the amorphous silicon layer containing the impurities is formed in a self-aligned manner, the source / drain wiring is used as a mask to prevent the non-containing of the impurities from being included. Another major feature is that it is not necessary to selectively etch the crystalline silicon layer.

[0046]

As described above, in the present invention, the insulating layer for protecting the channel of the insulated gate transistor is formed in a self-aligned manner with the gate by anodizing the amorphous silicon layer containing impurities. . Therefore, the planar overlap between the source / drain made of the amorphous silicon layer containing impurities and the gate can be 1 μm or less regardless of the size of the device. Baking can be virtually eliminated. Also, from the viewpoint of simplifying the manufacturing process, it is possible to form an insulated gate transistor with one plasma CVD apparatus, and in addition, an amorphous silicon layer containing no impurities may be formed thin, so that the yield is improved. Excellent effects such as a significant contribution to improving productivity and productivity were obtained.

Needless to say, there are no particular restrictions on the material of the gate wiring and the source / drain wiring, as is apparent from the gist of the present invention.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of an insulated gate transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of an insulated gate transistor according to an embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process of an insulated gate transistor according to an embodiment of the present invention.

FIG. 4 is a perspective view showing a mounting means on a liquid crystal panel.

FIG. 5 is an equivalent circuit diagram of an active liquid crystal panel.

FIG. 6 is a sectional view of a main part of the same panel for color display.

FIG. 7 is a plan pattern diagram on a conventional TFT substrate corresponding to FIG.

8 is a cross-sectional view of the manufacturing process on line A-A 'in FIG.

FIG. 9 is a plan pattern diagram on another conventional TFT substrate.

FIG. 10 is a sectional view of the manufacturing process on the line A-A ′ in FIG. 9;

[Explanation of symbols]

 1 Liquid Crystal Panel 2 Glass Plate 3 Semiconductor Chip 4 Connection Film 5, 6 Electrode Terminal 9 Color Filter 10 Insulation Gate Type Transistor 11 Scan Line 12 Signal Line 13 Liquid Crystal Cell 14 Picture Element Electrode 15 Counter Electrode 16 Liquid Crystal 17 Common Electrode Line 18 Coloring layer 19 Alignment film 20 Polarizing plate 23 Drain wiring 24 Gate insulating layer 25 Amorphous silicon layer containing no impurities 26 Amorphous silicon layer containing impurities 27 Insulating layer as an etching stopper 28 Negative photosensitive resin layer 29 Ultraviolet 30 Opening of Photosensitive Resin Layer 31 Silicon Oxide Layer Containing Impurities 32 Positive Photosensitive Resin Layer 33 Refractory Metal Layer 34 Silicide Layer as Source / Drain

Claims (6)

[Claims] 1. A first metal layer which also serves as a scanning line and serves as a gate is selectively formed on one main surface of an insulating substrate, and impurities are contained through the first insulating layer which serves as a gate insulating layer. Not first
An amorphous silicon layer is formed on the gate, and the second insulating layer including impurities is formed on the first amorphous silicon layer and is thinner than the gate and is self-aligned. A second amorphous silicon layer containing a pair of impurities as a source / drain, and a source / drain wiring that includes the source / drain and does not overlap the gate on the first insulating layer; Insulated gate type transistor characterized in that the metal layer is selectively formed. 2. A step of selectively forming a first metal layer which also serves as a scanning line on a main surface of an insulating substrate and serves as a gate, a first insulating layer which serves as a gate insulating layer, and impurities. Not first
Sequentially depositing the amorphous silicon layer and the second amorphous silicon layer containing impurities; applying a negative photosensitive resin on the second amorphous silicon layer; A step of forming a photosensitive resin pattern having an opening portion smaller than the gate on the gate including exposure from the other main surface of the insulating substrate; and the second step using the photosensitive resin pattern as a mask. A step of selectively anodizing the amorphous silicon layer to form an impurity-containing silicon oxide layer; and, after removing the photosensitive resin pattern, a first layer containing the impurity so that the gate does not overlap with the gate in a planar manner. 2. A method of manufacturing an insulated gate transistor, comprising the step of selectively forming a second metal layer to be a source / drain wiring on the amorphous silicon layer 2. 3. A first metal layer which also serves as a scanning line and serves as a gate is selectively formed on one main surface of an insulating substrate, and impurities are contained through the first insulating layer which serves as a gate insulating layer. Not first
An amorphous silicon layer is formed on the gate, and the second insulating layer including impurities is formed on the first amorphous silicon layer and is thinner than the gate and is self-aligned. A second amorphous silicon layer containing a pair of impurities is used as a source / drain, and the source / drain is self-aligned so as to partially overlap the gate on the first insulating layer including the source / drain. An insulated gate transistor, wherein a second metal layer to be a wiring is selectively formed. 4. A step of selectively forming a first metal layer which also serves as a scanning line and serves as a gate on one main surface of an insulating substrate, a first insulating layer which serves as a gate insulating layer, and impurities. Not first
Sequentially depositing the amorphous silicon layer and the second amorphous silicon layer containing impurities; applying a negative photosensitive resin on the second amorphous silicon layer; A step of forming a first photosensitive resin pattern having an opening portion smaller than the gate on the gate including exposure from the other main surface of the insulating substrate; and masking the first photosensitive resin pattern As a step of selectively anodizing the second amorphous silicon layer to form a silicon oxide layer containing impurities, and after removing the first photosensitive resin pattern, a negative photosensitive resin is formed on the entire surface. And a step of forming a second photosensitive resin pattern which is thinner than the gate and is removed from the gate by exposure from the other main surface of the insulating substrate, and a second metal on the entire surface. A step of selectively forming a layer, and the second step Method of manufacturing insulated gate transistor comprising the step of selectively forming a source and drain wiring after selectively removing said second metal layer by the removal of the optical resin. 5. A first metal layer which also serves as a scanning line and serves as a gate is selectively formed on one main surface of the insulating substrate, and impurities are contained through the first insulating layer which serves as a gate insulating layer. Not first
An amorphous silicon layer is formed on the gate, and the second insulating layer including impurities is formed on the first amorphous silicon layer and is thinner than the gate and is self-aligned. And a second silicide layer formed on the second amorphous silicon layer containing impurities as a source / drain and forming a source / drain wiring on the first insulating layer including the source / drain. Insulated gate type transistor characterized in that the metal layer is selectively formed. 6. A step of selectively forming a first metal layer which also serves as a scanning line on a main surface of an insulating substrate and serves as a gate, a first insulating layer which serves as a gate insulating layer, and impurities. Not first
Sequentially depositing the amorphous silicon layer and the second amorphous silicon layer containing impurities; applying a negative photosensitive resin on the second amorphous silicon layer; A step of forming a photosensitive resin pattern having an opening portion smaller than the gate on the gate, including exposure from the other main surface of the insulating substrate; and the second non-mask using the photosensitive resin pattern as a mask. A step of selectively anodizing the crystalline silicon layer to form a silicon oxide layer containing impurities; a step of depositing a second metal layer on the entire surface after removing the photosensitive resin pattern; Heating the substrate to selectively form the second amorphous silicon layer and the second metal layer into a silicide layer; and removing the second metal layer and then forming a source line or a source line on the silicide layer. Third gold to be source / drain wiring Method of manufacturing insulated gate transistor comprising the step of selectively forming a layer.