JPH076221A - Reader/writer for ic card - Google Patents

Abstract

PURPOSE:To provide the reader/writer for an IC card in which a communication processing time is reduced even for data communication between a host device whose interface has a different communication specification and the IC card. CONSTITUTION:An interface SCI1 of a host device side makes data communication of 8-bit data and the data are sent to an IC card via an interface SCI2 of the IC card side. In this case, when 7-bit data are sent to the IC card side, a reader/writer 300 buffers data by one bit only and sends the resulting data in a transparent form. Thus, the processing speed is improved more than the case that all data are buffered.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication specification of a reader / writer for an IC card, for example, a communication speed of an interface on the modem side is 2400 bps and that on the IC card side is 9600.
The present invention relates to the improvement of an IC card reader / writer, such as bps, in which the communication speed at the interface on the IC card side and that at the host device side are different.

[0002]

2. Description of the Related Art IC card reader / writers used in recent IC card systems are classified into a transparent type and a buffering type. In the former case, when data communication is performed from the host device to the IC card, only level conversion processing is performed for the operating voltage between the operating voltage level of the RS-232C interface for the host device and the operating voltage level of the TTL interface for the IC card. Is to do. Therefore, in this type of reader / writer, the processing speed of data communication between the host device and the IC card is improved as compared with the latter case. In the latter case, the latter buffers the data from the host device in the memory in the reader / writer, and then transmits the buffered data to the IC card. Further, the data from the IC card is similarly buffered and then transmitted to the host device.

Therefore, when the signal transmission speed (communication speed) of the interface on the host device side is different from that on the IC card side in this transparent type reader / writer, the communication speed on the host device side is set to the same 9600 bps as that on the IC card side. Alternatively, the frequency of the clock signal on the IC card side is lowered to make the communication speed the same.

Further, in the buffering type, since communication data is buffer-controlled and the data is temporarily saved in the buffer memory, it is possible to communicate at different communication speeds.

[0005]

However, the above-mentioned transparent type reader / writer has a problem that the communication specifications (communication protocol etc.) are limited depending on the IC card. Alternatively, there is a problem that the communication processing time becomes long by reducing the communication speed or the clock frequency.

On the other hand, the buffering type has a problem that the communication processing time is about twice as long as that of the transparent type due to the work of storing the communication data in the buffer memory.

Therefore, the present invention provides an IC card reader / writer which can shorten the communication processing time even for data communication between a host device having a communication specification having a different interface and an IC card. , Its purpose is.

[0008]

The invention described in claim 1 is connected to a host device 100 and an IC card 200 as shown in FIG. 1, and is capable of data communication with each of them. In the IC card reader / writer 300, the interface device 3 connected to the host device 100 and / or the IC card 200.
The interface device 310 includes a communication specification between the host device 100 and the IC card 200 and an IC when communicating data between the host device 100 and the IC card 200.
Detecting means 311 for detecting a difference from the card 200 and buffer means 31 for temporarily holding communication data.
2 and communication data having a data amount corresponding to the difference between the amount of data that can be transmitted and received per unit time between the host device 100 and the amount of data that can be transmitted and received per unit time between the IC card 200. A reader / writer for an IC card, which has a buffer control unit 313 held by the buffer unit 312.

According to a second aspect of the invention, the IC card reader / writer according to the first aspect is characterized in that the difference in the communication specifications is determined based on a protocol including at least a communication speed, a character configuration, a transmission format, and a code system. Is.

According to a third aspect of the invention, the amount of data that can be transmitted / received to / from the host device 100 per unit time,
The difference between the communication specifications is detected by comparing it with that of the IC card 200, and the buffer means 312 holds the communication data of the data amount corresponding to the difference of these data amounts. Is an IC card reader / writer.

According to a fourth aspect of the invention, the detecting means 3 is provided.
11 detects whether the interface device 310 is in the receivable state, and when it is not in the receivable state, the communication data having the data amount corresponding to the difference in the data amount is determined as the communication specifications are different. Buffer means 312
The IC card reader / writer according to claim 1 or 3, wherein the IC card reader / writer is held by.

The invention according to claim 5 is characterized in that the interface device 310 is provided on each of the connection side to the host device 100 and the connection side to the IC card 200. The reader / writer for an IC card according to claim 3 or claim 4.

Further, in the invention described in claim 6, the communication specification for the host device 100 side is equivalent to that for the IC card 200 side, or one of the host device 100 and the IC card 200 is used. In the case where data communication is performed from the host device 100 or the IC card 200 on the upstream side to the other one via the reader / writer 300, the amount of data that can be transmitted / received per unit time to the host device 100 on the upstream side or the IC card 200 is The IC according to any one of claim 1, claim 2, claim 3, claim 4, and claim 5 in which data communication is performed without operating the interface device 310 when the size is smaller than that for the device 100. It is a card reader / writer.

[0014]

The IC card reader / writer according to the present invention receives data from the host device 100 and transmits the data to the IC card 200. For example, host device 1
The communication specification of the interface for 00 is IC card 2
If it is different from that for 00, the data from the host device 100 is buffered in the buffer memory 312 and transmitted to the IC card 200 as necessary. For example, by comparing the amount of data that can be transmitted / received with the host device 100 per unit time with that with the IC card 200, a difference in communication specifications is detected. Then, the buffer memory 312 holds the communication data having the data amount corresponding to the difference in these data amounts. In addition, when the transmission and reception of all data is completed, the host device 10 transmits the response from the IC card 200 while receiving the response.
Send to 0. Also in this case, if necessary, the IC card 2
Buffer control data from 00.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a reader / writer for an IC card according to the present invention will be described below with reference to FIGS. First, the configuration of the reader / writer 300 will be described with reference to FIGS. 2 and 3. This reader / writer (R / W) 300 is an RS
-232C, TXD (transmission data), RXD
(Reception data), each pin of GND, and wiring are connected to the host device 100. When it is necessary to support a modem as the host device 100, CTS (transmission is possible),
The control is performed via each pin of RTS (transmission request) and wiring. The level conversion circuit MAX232 is used for level conversion of the operating voltage between RS-232C (for example, 12 V) which is an interface to the host device 100 and TTL level (for example, 5 V).

The reader / writer 300 is an IC card 2
00 for power supply port VCC and ground port GN
D, the clock signal supply port CLK, the data transmission / reception port I / O, and the reset signal supply port RST. Further, the reader / writer 300 has a RAM for buffer in addition to the CPU, MAX232, and CLK.

As the CPU according to this embodiment, the H8 series (H8 / 520) manufactured by Hitachi, Ltd. is used. In the CPU, SCI (serial communication interface) 1 indicates a communication interface on the host device 100 side, and SCI 2 indicates an IC card side interface. The communication interface SCI1 on the host device 100 side is the above TXD, RXD, P2.
0 and P21 pins are included. Also, I
The C card side interface SCI2 is the above TXD, R
It is configured to include each pin of XD, P30, P31, and P32.

FIG. 4 shows a communication format in the IC card system. NAD (node address) indicates a source address and a destination address. The PCB (protocol control byte) is a communication control byte and is used for controlling the communication layer such as a retransmission request at the time of a communication error. LEN is IN
The length of the FORMATION section (data section) is shown. EDC is an EXOR from NAD to the last byte of the INFORMATION part, and is a code used for detecting a communication error.

The operation of the reader / writer having the above configuration will be described with reference to FIGS.
This will be described based on the flowchart of FIG.

FIG. 5 shows a main flowchart. When the reader / writer is turned on, the communication interface SCI1 on the host device side is initialized (S501),
Next, the interface SCI2 on the IC card side is initialized (S502). For example, transfer formats such as communication speed, parity, stop bit, and character configuration are set. In addition, the transmission data register (TDR1) and the reception data register (RDR1) of the interface SCI1 are made operable (TE = 1, RE =
1). Further, the reception data register (RDR2) of the interface SCI2 is made operable (RE =
1).

Then, the address initial value (RDPT) of the reception pointer is set in the register 2 (R2), and the address initial value (TDPT) of the transmission pointer is set in the register 3 (R3) (S503). In this state, a host reception routine for receiving data from the host device 100 is executed (S
504). This subroutine is shown in FIG.

Then, it is judged whether the received data from the host device 100 is addressed to the reader / writer (S505), and if the data is not addressed to the reader / writer (R / W), this is the IC card 200. This is a case where the data from the host device should be transmitted to the host device 100. Therefore, the address initial value (RDPT) of the reception pointer is set in the register 2
In (R2), the initial value of the address of the transmission pointer (TDP
T) is set in the register 3 (R3) (S506).
Then, the transmission routine to the host device 100 is executed (S507). A transmission routine to the host device 100 is shown in FIG. If the data is addressed to the reader / writer (S
If YES at 505, the process at the reader / writer is executed (S
508), the processed contents are transmitted from the reader / writer to the host device 100 side (S509). Then, the process returns to the state of waiting for data reception (return to S503).

Host device 1 shown in step S504
7 shows a host reception routine for receiving data from 00 and transmitting it to the IC card 200. First, it is determined whether the receive data register full (RDRF1), which is a flag of the host-side interface SCI1, is 1, and if it is 1, 1 byte is received (YES in S701), and the received data is stored. Data is set in the register 1 (R1) from the received data register (RDR1) (S702).

Then, it is determined whether this data (communication format "NAD") is addressed to the reader / writer to the IC card (S703). Register 1 for reception
When the data of (R1) is addressed to the reader / writer (R / W) (YES in S703), the receiving process (IC card reset, etc.) in the reader / writer (R / W) is executed (S).
713), sends a response to the host device, and returns to reception.

When the received data is addressed to the IC card (S70
No in 3), the transmission data register (TDR2) of the IC card side interface SCI2 is made operable (S704). That is, data can be transmitted to the IC card by setting TE (Transmit Enable) = 1. In addition, the communication counter (TCT) is cleared.
Then, the 1-byte transmission routine is executed (S70).
5). The routine is shown in FIG.

Next step S706 shows an HRIT routine (host device reception IC card transmission). In this routine and step S707, 3 bytes (NAD, PCB, LEN) from the head of the data are received and transmitted to the IC card. . In step S707, the communication counter (TC
It is determined whether the value of T) has become 3. Counter is 3
Until, the routine for receiving the data from the host side is executed (S706). When reception / transmission of 3-byte data is completed (YES in S707), 4 bytes are added to the reception register R1 to indicate the length of the total number of data (S708). That is, LE
When N is received, the value of the register (R1) is changed to (R1 + 4 (N
AD, PCB, LEN, EDC)) (S70
8). Then, register (R0) with this register (R
The value of 1) is set (S709). Furthermore, HR
The IT routine is executed (S710), and the counter T
It is determined whether the CT value is equal to the register R0 value (S711). The total number of bytes is transmitted to the IC card. When the information section and the EDC are received and then transmitted to the IC card, and the communication counter (TCT) becomes equal to the value of the register 0 (R0) (YES in S711), the flag TE of the interface SCI2 is set to 0 (S712). ), The data from the IC card can be received, and the process returns to the main routine.

In the 1-byte transmission routine shown in FIG. 6, first, the transmit data register empty (TDR
It is determined whether or not E2) is 1 (S601), and if this flag is 1 (YES in S601), register 1 (R1)
Of the data is set in the transmission data register (TDR2) (S602). Next, 0 is set in the transmit data register empty (TDRE2) (S60
3) Further, the communication counter (TCT) is incremented by 1 (S604). If the transmit data register empty (TDRE2) is 0 (NO in S601), the value of register 1 (R1) is set to register 2 (R2).
The register 2 (R2) is incremented (@ R2 +) (S605). Then, the process returns to the data reception routine from the host device (S706 in FIG. 7).

The HRIT routine is shown in FIG. This routine receives data from the host device and sends this data to the IC card. First, it is determined whether or not the receive data register full (RDRF1) is 1 (S801). When the reception data register RDR is full, this flag becomes 1 (YES in S801),
The value of the reception data register (RDR1) is set in the register 1 (R
1) is set (S802). Then, the receive data register full (RDRF1) flag is cleared (S803). Next, it is determined whether or not the transmit data register empty (TDRE2) is 1 (S80).
4). It is to check whether data can be transmitted to the IC card. If 1 (YES in S804)
Transmission is possible, and the value of the reception pointer of the register 2 (R2) is compared with the value of the transmission pointer of the register 3 (R3) (S805). This is to determine whether or not there is data to be transmitted in the buffer.

When the values indicated by these pointers are different (NO in S805), the data indicated by the register 1 (R1) is saved in the buffer (@ R2 +) (S812),
Register 1 (R1) from address of register 3 (R3)
(S813). Then, step S806
Proceed to.

If the value of the reception pointer is the same as the value of the transmission pointer (YES in S805), that is, if there is no data to be transmitted in the buffer, the flow advances to step S806 to increment the register 3 (R3) (@ R3).
Then, the register 1 (R1) is set in the reception data register (TDR2). Furthermore, the communication counter (T
CT) is incremented (S807), the transmit data register empty (TDRE2) is cleared (S808), and the process returns to the host side reception routine (S707). This means that 1-byte transmission has been completed.

In step S804, if the transmit data register empty (TDRE2) is 0, the transmission data register TDR is full, so that the IC card is not transmitting or is transmitting. In this case, the received data in register 1 (R1) is buffered (@R
2+) (S811), and the process returns to the host side reception routine (S707). That is, the data of the register R1 is stored in the address of the register R2 and the received data is buffered.

If the receive data register full (RDRF1) is 0 in step S801, the transmit data register empty (TDR)
If E2) is 1 (YES in S809), register 2
The value of (R2) is compared with the value of register 3 (R3) (S810). The contents of the reception pointer are compared with those of the transmission pointer. If these values are different (NO in S810), the flow advances to step S813 to set the 1-byte data from the start address (@ R3 +) of the register R3 in the register 1 (R1). Furthermore, the value of register 1 (R1) is set to the transmission data register (TDR2).
(S806), the communication counter (TCT) is incremented (S807), and the transmit data register empty (TDRE2) is set to 0 (S).
808) Return to the host-side reception routine (S707). I
One byte is sent to the C card side.

FIG. 9 shows a routine for receiving data from the IC card. In this case, first, the communication counter (TCT) is cleared (S901), 3 bytes (NA
D, PCB, LEN) is received by the IRHT routine (IC card reception host transmission routine) and transmitted to the host device (S902, S903).

When LEN is received (R1 + 4 (NAD,
(PCB, LEN, EDC)) (S904), and the data in the register (R1) is set in the register (R0) (S905). In addition, the information section and EDC
Is received and transmitted to the host device (S906). When the communication counter (TCT) reaches (R0), the transmission is completed, and the process returns to the main routine.

The IRHT routine is shown in FIG. When the flag (RDRF2) becomes 1 (YE in S1001)
S), the data of the register (RDR2) is set in the register (R1) for transmission (S1002), and this flag (R
DRF2) is cleared (S1003). This flag (RDRF2) indicates whether or not data is received from the IC card.

Next, if the flag (TDRE1) is 1 (S1004), data can be transmitted to the host device. Therefore, the value of the receive pointer of the register (R2) and the transmit pointer of the register (R3) are set. Compare with the value (S1
006), if they are the same, there is no transmission data in the buffer, so the data in the register R1 is set in the transmission data register TDR1 (S1007). Then, the communication counter TCT is incremented (S1008),
The flag TDRE is cleared (S1009). By this step S1007, 1-byte data is transmitted to the host.

When the pointer value is different (NO in S1006), the value of the register (R1) is buffered (@ R2 +).
(S1010). Set the address of the register (R3) to the register (R1), and register (R3)
Is incremented (@ R3 +) (S1011). Then, in step S1007, the data in the register (R1) is set in the reception data register (TDR1),
The counter (TCT) is incremented (S100
8), clear the flag (TDRE1) (S100
Return from 9).

If the flag (TDRE1) is 0 (NO in S1004), the data in the register (R1) is buffered in the buffer (@ R2 +) and the process returns (S105). When the data is being transmitted, the data is buffered.

In step S1001 described above,
When the flag (RDRF2) becomes 0, the flag (TDRE
It is checked whether 1) is 1 (S1012). When the flag (TDRE) becomes 1, the value of the transmission pointer and the value of the reception pointer are compared (S1013). If these values are different (NO in S1013), 1 byte is registered from the start address of the buffer (@ R3 +). Set to (R1) (S1011) and register (R1) to register (TD
R1) (S1007) and flag (TDRE)
1 is set to 0 (S1009), and the counter (TC
T) is incremented (S1008) and the process returns.

FIG. 11 shows the format of communication data used in this system. When the communication format is different, for example, when the communication speed (baud rate) is different between the interface on the host device side and that on the IC card side, the stop bit, the data configuration (8-bit data or 7-bit data), and the parity are different. However, according to the present embodiment, data communication is performed by buffering only an appropriate number of data, so that the processing speed can be increased. The detection of the difference in the communication specifications can also be performed by determining the receivable state by referring to the SCI reception flag, for example. Alternatively, it may be determined by comparing the positions of the buffer pointers.

FIG. 12 shows a host device in this embodiment,
6 is a timing chart for explaining the exchange of data between a reader / writer and an IC card. FIG.
(A) and (B) show the conventional case. As shown by comparing FIGS. 12 and 13, in the case of the present invention, when the communication specifications are different, for example, when 8-bit data is received and transmitted as 7-bit data,
Only one bit is buffered and transmitted. As a result, the processing speed in the reader / writer can be significantly improved as compared with the buffering type of FIG. 13B. In the above embodiment, when the communication specifications for the host device are the same as those for the IC card, the data communication is performed without performing the buffering operation. Also, in the case where the communication specifications for the host device and the IC card are lower than the communication specifications for the transmission side compared to those for the reception side, buffering is not performed in the same manner.
Data communication is executed.

[0042]

In the IC card reader / writer according to the present invention, the IC card side interface and the host device side interface have different communication specifications (communication speed, parity, stop bit and other communication protocols). On the other hand, an optimum interface can be provided without reducing the processing speed in communication and the processing speed of the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an IC card system according to the present invention.

FIG. 2 is a block diagram showing an IC card system according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a reader / writer for an IC card according to an embodiment of the present invention.

FIG. 4 is a diagram showing a format of communication data according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation of the reader / writer according to the embodiment of the present invention.

FIG. 6 is a flowchart showing a 1-byte transmission routine according to an embodiment of the present invention.

FIG. 7 is a flowchart showing a data reception routine from a host device according to an embodiment of the present invention.

FIG. 8 is a flowchart showing a procedure of receiving data from the host device and transmitting the data to the IC card according to the embodiment of the present invention.

FIG. 9 is a flowchart showing a procedure for receiving data from the IC card according to the embodiment of the present invention.

FIG. 10 is a flowchart showing an IC card reception host device transmission routine according to an embodiment of the present invention.

FIG. 11 is a diagram showing commands of a reader / writer according to an embodiment of the present invention.

FIG. 12 is a timing chart for explaining the operation of the interface of the reader / writer according to the embodiment of the present invention.

FIG. 13 is a timing chart for explaining the operation of the reader / writer in the conventional IC card system.

[Explanation of symbols]

 100 host device 200 IC card 300 reader / writer 310 interface device 311 detection means 312 buffer means 313 buffer control means

Claims (6)

[Claims] 1. A reader / writer for an IC card, which is connected to a host device and an IC card and is capable of performing data communication with each of them, and an interface device connected to the host device and / or the IC card. The interface device includes a detection unit that detects a difference between a communication specification between the host device and the IC card and a communication specification between the host device and the IC card when the data communication is performed between the host device and the IC card. Communication of a data amount corresponding to the difference between the amount of data that can be transmitted / received per unit time between the buffer means for temporarily holding and the host device and the amount of data that can be transmitted / received per unit time between the IC card And a buffer control means for holding data by the buffer means. . 2. The reader / writer for an IC card according to claim 1, wherein the difference in communication specifications is determined based on a protocol including at least a communication speed, a character configuration, a transmission format, and a code system. 3. A difference in the communication specifications is detected by comparing the amount of data that can be transmitted and received per unit time with the host device with that between the IC card and the data amount of these data. The IC according to claim 1, wherein communication data having a data amount corresponding to a difference is held by the buffer means.
Card reader / writer. 4. The detecting means detects whether or not the interface device is in a receivable state, and when the interface device is not in a receivable state, the data corresponding to the difference in the data amount is regarded as the communication specification being different. The IC card reader / writer according to claim 1 or 3, wherein a certain amount of communication data is held by the buffer means. 5. The interface device according to claim 1, wherein the interface device is provided on each of a connection side to the host device and a connection side to an IC card. An IC card reader / writer according to item 1. 6. A communication specification for the host device side,
When it is equivalent to that for the IC card side, or when data communication is performed from one of the host device and the IC card to the other via the reader / writer, the host device or IC card on the upstream side The amount of data that can be sent / received per unit time is
6. The data communication is performed without operating the interface device when the size is smaller than that for the card side or the host device, according to claim 1, claim 2, claim 3, claim 4, or claim 5. IC card reader / writer.