JP2001105661A - Serial communication apparatus and data processor with communication apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial communication apparatus which can deal with an expected communication operation without requiring alteration of system clock SC, alteration of communication baud rate or design revision depending on presence/absence of a parity in data format. SOLUTION: A register control section 1 controls read/write of transmitting/ receiving data register or a register for setting the conditions of transmitting/ receiving operation. A transmission control section 3 converts parallel data into serial data and outputs the serial data at a specified baud rate while a receiving control section 4 operates reversely. At the time of altering the SC frequency, the register control section 1 rewrites the SC clock number DATA of a register designated by an ADRS depending on the alteration of frequency and generates a communication reference clock from the SC at a constant baud rate based on the clock number value. Alteration of baud rate and parity processing are carried out similarly through setting of a register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication device provided with serial communication control means,
Even if the system clock frequency of the device is changed, a serial communication device capable of responding to an intended operation by changing the setting of the device and a data processing device equipped with the serial communication device (for example, a printer, a digital copying machine) Such as a machine for processing digital data).

[0002]

2. Description of the Related Art Conventionally, in a system printer, serial communication of data is performed with a print engine. Here, a serial communication control device that performs communication control in accordance with a transmission / reception reference clock generated based on a system clock is used. When starting the design of this communication control device, the communication accuracy is examined according to the clock frequency that is to be used, and the device is designed.
When the serial communication controller was completed, there were changes in the specifications, the clock of the planned frequency was discontinued, or a clock with a higher frequency than the planned May be required to change the frequency of the system clock, for example, because it is now available at low cost. In such a case, in the past, the design had to be redesigned, and the design period was extended, resulting in a problem that the cost was increased. Also, when the above serial communication controller is designed as an ASIC, the same ASIC cannot be used for a system with a different system clock even if the ASIC can be used for the target system at the time of design. Although it was small, it had to renew its ASIC, which caused high development costs and long development days.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the conventional serial communication control apparatus, and has as its object to change the system clock, and further change the communication baud rate and data format. An object of the present invention is to provide a serial communication device capable of responding to an intended operation without requiring a device design change for (presence or absence of parity), and a data processing device provided with the serial communication device.

[0004]

According to a first aspect of the present invention, there is provided a communication system for generating a transmission / reception reference clock determined by a communication port rate based on a system clock, and performing a control operation of serial data communication in accordance with the generated transmission / reception reference clock. In the serial communication device having the control means, the number of system clocks corresponding to one clock of the transmission / reception reference clock is set so that the transmission / reception reference clock is kept constant even when the adopted system clock is changed. And a communication control unit that generates the transmission / reception reference clock based on a set clock number.

According to a second aspect of the present invention, in the serial communication device according to the first aspect, the setting of the communication port rate is made variable, and the communication control means adjusts the transmission / reception reference clock according to the set port rate. And a serial communication device characterized by being used.

According to a third aspect of the present invention, in the serial communication device according to the first or second aspect, a parity bit is inserted into either odd-numbered or even-numbered field data in the format of the communication data, or the parity bit is added. Inserting either odd-numbered or even-numbered data, or setting the parity bit not to be inserted is variable, and the communication control means performs a control operation according to the set format. Serial communication device.

According to a fourth aspect of the present invention, there is provided a data processing apparatus comprising the serial communication device according to any one of the first to third aspects.

According to a fifth aspect of the present invention, there is provided a data processing apparatus according to the fourth aspect, wherein the data processing apparatus is a printer, and the communication control means controls serial communication with a print engine. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described based on the following embodiments shown in the accompanying drawings. FIG. 1 is a block diagram showing an outline of a circuit of an embodiment of a serial communication control device according to the present invention. This serial communication control device includes a register control unit 1, an interrupt control unit 2, a transmission control unit 3, and a reception control unit 4. The register control unit 1 controls reading / writing of registers such as a transmission / reception data register and a register for setting operating conditions relating to transmission / reception operations. The interrupt controller 2 receives the received data 8 bits and writes it to the received data register, or when the transmitted data 8 bits have been transmitted and the transmitted data register becomes empty, the host 2 (not shown). This controls the operation of requesting the reading and writing of data. The transmission control unit 3 controls the conversion of 8-bit parallel data into serial data by a transmission shift register and outputs the serial data at a constant speed. The reception control unit 4 performs control for converting serial data sent at a constant speed into 8-bit parallel data by a reception shift register. In this serial communication control device, conditions are set so that the transmission accuracy is within ± 1% and the reception accuracy is within ± 3%, and the transmission / reception operation is performed.

Here, the contents of the signal shown in FIG. 1 will be described. SBRK_ is a signal for selecting whether or not to transmit a break when the power is turned on. ADRS is an address that specifies each register. DATA is data to be written to or read from each register. R / W is a register read / write (READ / WRITE) signal. INT_ is used to notify the host when 8-bit receive data is written to the receive data register or when 8-bit transmit data is read from the transmit data register and is empty. Signal. TXD is 1-bit transmission data, and RXD is 1-bit reception data.
FIG. 2 shows an embodiment of a register controlled by the register control unit 1 of FIG. Each register (Control, Stat
us, Data, ArtCLK) control data ADRS, DATA (data format),
It is shown in relation to R / W.

Next, an example of a transmission sequence of the serial communication control device will be described with reference to FIG. In FIG.
WRITE indicates the time of R / W WRITE in FIG. 1, and TxRDY indicates a transmission ready flag which becomes "1" when the transmission data is written to the transmission hold register (TxData indicated in the data register at address 2 in FIG. 2). , TxC represent a communication reference clock. In this transmission sequence, in S1,
The WRITE signal is input, and data1 is written to the transmission hold register. TxRDY is cleared (0) by writing. S2
In, the data in the transmission hold register is transferred to the transmission shift register, TxRDY is set, and TXD is set to L (start bit). In S3, data1 in the transmission shift register starts to be transmitted serially. At this time, according to the communication reference clock TxC, a sequence composed of 11 bits of 1 start bit, 8 data bits, 1 parity bit, and 1 stop bit is executed. At S4, a WRITE signal is input, and data2 is written to the transmission hold register. TxRDY is cleared (0) by writing.

The communication reference clock TxC used to execute this sequence is generated based on the system clock frequency. Therefore, when the system clock frequency is changed, it is necessary to operate at a predetermined baud rate. It is necessary to change the number of clocks of the system clock to be referred to in order to create a reference clock used for communication. For example, consider the case where the system clock is 44 MHz and the baud rate is 19200 bps. In this case, 1920
At 0 bps, it takes 52083.33 ns to send one bit. When 52083.33 ns is calculated as the number of 44 MHz system clocks, the result is 52083.33 ÷ 1000/44 = 2291.66. Therefore, the communication reference clock TxC is generated from the system clock by specifying this clock value, that is, by specifying the clock number. The number of clocks is specified by setting the number of clocks in a register indicated as ArtCLK at address 3 in FIG. 2 (register ArtCLK).
Is represented by 8 bits). Also, the system clock
If the frequency was 66 MHz, similarly, 52083.33 ÷ 1000/66 = 347
It becomes 2.39. Here, the set reference clock is 2291.6
If it is within ± 1% of 6 or 3347.39, the transmission accuracy can be protected. From this, 2063 (= 2291.66 × -1%)
By configuring the register ArtCLK so that the number of system clocks between 3819 (= 3472.39 × + 1%) can be set and generating the transmission reference clock, the system clock
A transmission control unit of a serial communication control device capable of efficiently performing transmission in a system within the range of 44 to 66 MHz can be configured.

Next, an example of the reception sequence will be described with reference to FIG. READ in FIG. 4 indicates the time of READ of R / W in FIG. 1, and RxRDY is a read ready read data which becomes “1” when the receive data is written in the receive hold register (RxData of address 2 in FIG. 2). Represents the flag, SampleP
Represents a sampling pulse for extracting the reception data RXD. In this reception sequence, in S1, the stop
RxRDY is set (1) at the same time that the bits are sampled and the received data is transferred from the reception shift register to the reception hold register. In S2, RxRDY is cleared (0) by reading the reception data of the reception hold register. FIG. 5 shows the sampling operation of the reception data in this reception sequence. In this operation example, the received data RX
The value of D is sampled at certain intervals, and when the start bit (L) is detected, the data is read at different sampling intervals. In the present embodiment, the start bit is detected by one reference clock (= 229 system clocks, that is, 1/10 of the baud rate clock), and then the detected start bit is detected by the four reference clocks as an erroneous signal (so-called,
Check whether the start bit is really not Rather than beard, that is, whether RXD is L, and from the next data 0, detect whether the received data is H or L with 10 reference clocks (that is, baud rate clock), Data 1 to Data 7,
Detects parity and stop bits at the same interval. After the stop bit is detected, the start bit is detected again by one reference clock. As shown in FIG. 5, this sampling operation is timed around the RXD (reference). Therefore, the slowest received data and the fastest received data that can be detected are the RXD shown in FIG.
(Slowest) and RXD (fastest), and the receiving operation with acceptable accuracy is performed in this range.

The sampling interval of the start bit is such that the baud rate is 19200 bps, that is, 52 bits are required to send one bit.
083.33 ns, so when the system clock is 44 MHz, 52083.33 ÷ 1000/44 ÷ 10 = 2291.66 ÷ 10 = approximately 229 clocks, and when 66 MHz, 52093.33 ÷ 1000/66 ÷ 10 = 3472.39 ÷ 10
= About 347 clocks. This is used as a reference clock used for reception. After detecting the start bit, 4 reference clocks until sampling to check if the start bit was a real start bit, not a beard. After that, 1 until the stop bit
Sampling is performed every 0 reference clocks. The slowest received data that can be received by this method is ｛(4 + 10 ×
10) x number of system clocks + (number of system clocks-1)｝ ÷
10 × system clock (ns), the fastest received data per bit ｛(4 + 10 × 10) × number of system clocks｝ ÷ 11 ×
It becomes the system clock (ns). When the reception accuracy is obtained from the above equation, the case of 44 MHz and the case of 66 MHz are both -5.52 to 4.
It is 92%, which satisfies ± 3%. In order to reduce the number of parts and reduce costs, the reference clock for reception and transmission is shared, and the reference clock for transmission is 229 × 10
(44 MHz) and 347 × 10 (66 MHz), the number of bits of the register for setting the reference clock also decreases. For example, in the example of FIG.
Can be expressed in bits. In other words, in this example, 44MHz to 66MHz
It can correspond to any frequency in between, transmission accuracy within 1%,
A communication control device having a reception accuracy within 3% can be obtained by setting a value in the register of FIG.

In the above embodiment, the baud rate is fixed (19
200 bps), but in the following example, the baud rate is made variable so that the same accuracy can be obtained at other baud rates. To realize this, a baud rate setting register is provided. FIG. 6 shows an example of a register configuration provided with a baud rate setting register. As shown in FIG. 6, address 0 in the register group
The setting is performed with the Baud Rate of D29 in the Control register of. In this example, if "0" is set here, 9600b
ps baud rate is set. When the baud rate is set to 9600 bps, the reference clock for transmission and reception is set to 1920 as shown in the previous example.
Assuming that it is used in common with 0 bps, during transmission, 20 reference clocks (reference clock = 229 system clocks,
At a period of 19200 bps, 10 reference clocks), the data is output starting from the start bit, and the data is output one bit at a time in the order of eight bits, one bit at a time from the lower order, and parity bit and stop bit when parity is present. When data is written to the transmission data register, the above-described transmission operation is performed. When calculating the transmission accuracy when the system clock is 44 MHz, it is 104166.66 ns per bit at 9600 bps, so (104166.66-229 × 20 × 1000/44) ÷ 104166.66 = 0.
00072 (0.072%), which satisfies 1% or less.

FIG. 7 shows the sampling operation of the received data in this case. The sampling operation during reception is
As shown in FIG. 7, a start bit is detected at an interval of one reference clock, and then the reference bit is set to 9 reference clocks until sampling to check whether the start bit is a real start bit, not a beard,
Thereafter, sampling is performed every 20 reference clocks until the stop bit. The slowest received data that can be received by this method is per bit ｛(9 + 20 × 10) × number of system clocks + (number of system clocks -1)｝ ÷ 10 × system clock
(ns), the fastest received data is ｛(9 + 20 × 1
0) x number of system clocks / 11 x system clock (ns)
Becomes When the receiving accuracy is obtained from the above equation, for example, 44MH
-5.07 to 4.92% for z, -4.10 to 5.99 for 66MHz
%, Which satisfies ± 3%. Thus, by taking the register configuration of FIG. 6, for example, the operation of the above-described embodiment is performed at 19200 bps, and the operation of this embodiment is performed at 9600 bps. Can be obtained.

In the above embodiment, the baud rate is variable (96
00 bps / 19200 bps), but in the following example, if there is more parity bits,
EN or ODD can be selected, and the same accuracy as in the above two examples can be obtained. To realize this, a parity setting register is provided. FIG. 8 shows a register configuration example provided with a parity setting register. As shown in FIG. 8, Contr at address 0 in the register group
The setting is performed by the 2-bit parity of D30 and D31 in the ol register. FIG. 9 shows a sampling operation of received data in this embodiment. As shown in the figure, when there is no parity, one transfer is constituted by a total of 10 bits including a start bit, data 0 to 7, and a stop bit. The sampling operation at the time of reception is when the baud rate is 19200 bps,
As shown in FIG. 9, a start bit is detected at an interval of one reference clock, then four reference clocks are used until sampling to check whether the start bit is a true start bit, and then a stop bit is used. Performs sampling every 10 reference clocks.

In this operation example, other than that there is no parity, the other conditions are the same as those in the above-described embodiment when the system clock is 44 MHz and the baud rate is 19200 bps. When the transmission / reception accuracy is calculated for this case, the transmission accuracy per bit is the same as in the above embodiment, and (52083.33-229 × 10 × 1
000/44) ÷ 52083.33 = 0.00073 (0.073%), which satisfies 1% or less. At this time, the reception accuracy is 1 for the slowest reception data.
Per bit ｛(4 + 10 × 9) × 229 + (229-1)｝ ÷ 9 × 1000/44
= 54934.34 (ns), so 54934.34 ÷ 52083.33 = 1.00547 (5.47
%), The fastest received data per bit ｛(4 + 10 × 9)
× 229｝ ÷ 10 × 1000/44 = 48922.73 (ns), so 48922.73 ÷ 5
2083.33 = 0.9393 (-6.07%), which satisfies ± 3%.
From this, the transmission / reception accuracy can be within the allowable range with or without parity, so by adopting the register configuration of FIG. 8, it is possible to select any of no parity, even parity, or ODD parity, and A serial communication control device that can support any of the data formats can be obtained.

[0019]

(1) Effects corresponding to the first aspect of the invention Even if the frequency of the system clock changes, the reference clock for transmission and reception according to the baud rate of communication can be changed by changing the value (the number of system clocks) set in the register. Can be generated, so that it is possible to cope with an intended communication operation without changing the design of the circuit, which is conventionally performed when the clock frequency is changed. In addition, the circuit design can be performed only once, and the same circuit can be applied to many models, so that there is no need to perform a new design, and as a result, the design period is shortened,
It leads to cost reduction. (2) Effects corresponding to the second aspect of the invention In addition to the effects of the above (1), setting of the baud rate data in a register for setting the baud rate without changing the circuit even if the transfer speed of the connection partner of the serial communication changes. By changing the parameter, it is possible to cope with the intended communication operation, so that the applicable range is expanded, the speed of the system can be increased, and the cost can be reduced. (3) Effects corresponding to the third aspect of the invention In addition to the effects of the above (1) and (2), even if the parity processing at the connection partner of the serial communication changes, the presence / absence of parity and the presence / absence of parity are By simply setting the data for selecting EVEN / ODD in the register, it is possible to respond to the expected communication operation, so that the applicable range is expanded, the speed of the system can be increased, and the cost can be reduced. (4) Effects According to Claims 4 and 5 The effects (1) to (3) can be realized in serial communication in a data processing device or serial communication with a print engine in a printer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an outline of a communication control unit of a serial communication device according to the present invention.

FIG. 2 shows an example of a configuration of a register controlled by a register control section 1 of FIG.

FIG. 3 shows an example of a transmission sequence of the serial communication device according to the present invention.

FIG. 4 shows an example of a reception sequence of the serial communication device according to the present invention.

FIG. 5 is an explanatory diagram of a sampling operation of reception data in a reception sequence.

FIG. 6 shows another example of the configuration of the register controlled by the register control unit 1 of FIG.

FIG. 7 is an explanatory diagram of a sampling operation of reception data in a reception sequence.

FIG. 8 shows another example of the configuration of the register controlled by the register control unit 1 of FIG.

FIG. 9 is an explanatory diagram of a sampling operation of reception data in a reception sequence.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Register control part, 2 ... Interrupt control part, 3 ... Transmission control part, 4 ... Reception control part.

Claims (5)

[Claims] 1. A serial communication apparatus comprising a communication control unit for generating a transmission / reception reference clock determined by a communication port rate based on a system clock and performing a control operation of serial data communication in accordance with the generated transmission / reception reference clock. Means for setting the number of system clocks corresponding to one clock of the transmission / reception reference clock so that the transmission / reception reference clock remains constant even when the system clock to be changed is changed. A serial communication device for generating the transmission / reception reference clock based on the determined clock number. 2. The serial communication device according to claim 1, wherein the communication port rate is set variable, and said communication control means adjusts and uses said transmission / reception reference clock according to the set port rate. Serial communication device. 3. The serial communication device according to claim 1, wherein a parity bit is inserted into the data of the odd-numbered or even-numbered field in the format of the communication data, or the parity bit is inserted into the odd-numbered or even-numbered field. A serial communication device, wherein the setting of whether any one of the data is inserted or the parity bit is not inserted is made variable, and the communication control means performs a control operation according to a set format. 4. A data processing device comprising the serial communication device according to claim 1. 5. The data processing device according to claim 4, wherein the data processing device is a printer, and the communication control unit controls serial communication with a print engine.