JPH0765135A - Reader writer for ic card - Google Patents

Abstract

PURPOSE:To shorten the time of a communication process between host equipment and an IC card which have different transmission formats by holding communication data whose amount corresponds to the difference between the transmission formats in a buffer means. CONSTITUTION:A detecting means 312 in an interface device 310 detects the difference between the transmission formats of the host equipment 100 and the IC card 200. A buffer control means 313 holds the communication data in the buffer means 311 by the data amount corresponding to the difference between those transmission formats. The IC card reader writer 300 buffers data from the host equipment 100 in the buffer means 311 at need and sends the data to the IC card 200. When data are sent from the IC card 200 to the host equipment 100, the data from the IC card 200 are brought under buffer control when necessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC card reader / writer, and more particularly to an IC card reader / writer capable of transparent data communication when the transmission format of an interface on the IC card side and that on the host device side are different. .

[0002]

2. Description of the Related Art IC card reader / writers used in recent IC card systems are classified into a transparent type and a buffering type. In the former case, when data communication is performed from the host device to the IC card, only level conversion processing is performed for the operating voltage between the operating voltage level of the RS-232C interface for the host device and the operating voltage level of the TTL interface for the IC card. Is to do. Therefore, in this type of reader / writer, the processing speed of data communication between the host device and the IC card is improved as compared with the latter case. In the latter case, the latter buffers the data from the host device in the memory in the reader / writer, and then transmits the buffered data to the IC card. Further, the data from the IC card is similarly buffered and then transmitted to the host device.

[0003]

However, the above-mentioned transparent type reader / writer has a problem that the communication specification (transmission format) is limited depending on that of the IC card. This is because, in the reader / writer, if the transmission format of the host device side interface is different from that of the IC card side, communication will be disabled.

On the other hand, the buffering type also has a problem that the communication processing time is about twice as long as that of the transparent type due to the operation of storing the communication data in the buffer memory.

Therefore, the present invention provides a reader / writer for an IC card, which can shorten the communication processing time even for data communication between a host device having a different transmission format and an IC card. Has an aim.

[0006]

The invention described in claim 1 is connected to a host device 100 and an IC card 200 as shown in FIG. 1, and is capable of data communication with each of them. In the IC card reader / writer 300, the interface device 3 connected to the host device 100 and / or the IC card 200.
The interface device 310 includes a buffer unit 311 for temporarily holding communication data, a transmission format between the host device 100 and the IC card 200 when data communication between the host device 100 and the IC card 200, and I
The detection means 312 for detecting the difference between the C card 200 and the IC card 200, and the buffer for transferring the communication data of the data amount corresponding to the difference between the transmission format between the host device 100 and the IC card 200. IC having buffer control means 313 held by means 311
It is a card reader / writer.

[0007]

The IC card reader / writer according to the present invention receives data from the host device 100 and transmits the data to the IC card 200. For example, host device 1
If the transmission format for 00 is different from that for the IC card 200, if necessary, the host device 10
The data from 0 is buffered in the buffer means 311 and transmitted to the IC card 200. For example, host device 1
00 and each ATR information from the IC card 200 are compared to detect a difference in transmission format.
Then, the buffer means 311 holds the communication data of the data amount corresponding to the difference of these transmission formats. Further, when the transmission / reception of all data is completed, this is transmitted to the host device 100 while receiving the response from the IC card 200. In this case as well, the data from the IC card 200 is buffer-controlled as necessary.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a reader / writer for an IC card according to the present invention will be described below with reference to FIGS. First, the configuration of the reader / writer 300 will be described with reference to FIGS. 2 and 3. This reader / writer (R / W) 300 is an RS
-232C, TXD (transmission data), RXD
(Reception data), each pin of GND, and wiring are connected to the host device 100. When it is necessary to support a modem as the host device 100, CTS (transmission is possible),
The control is performed via each pin of RTS (transmission request) and wiring. The level conversion circuit MAX232 is used for level conversion of the operating voltage between RS-232C (for example, 12 V) which is an interface to the host device 100 and TTL level (for example, 5 V).

This reader / writer 300 is an IC card 2
00 for power supply port VCC and ground port GN
D, the clock signal supply port CLK, the data transmission / reception port I / O, and the reset signal supply port RST. Further, the reader / writer 300 has a RAM for buffer in addition to the CPU, MAX232, and CLK.

As the CPU according to this embodiment, an H8 series manufactured by Hitachi Ltd. (for example, H8 / 520) is used. In the CPU, SCI (serial communication interface) 1 indicates a communication interface on the host device 100 side, and SCI 2 indicates an IC card side interface. The communication interface SCI1 on the host device 100 side is the above TXD, RXD, P2.
0 and P21 pins are included. Also, I
The C card side interface SCI2 is the above TXD, R
It is configured to include each pin of XD, P30, P31, and P32.

FIG. 4 shows an example of a transmission format in the IC card system. (A) is an IC based on ISO
This is the transmission format of the card, and "NAD (node address)" indicates the addresses of the transmission source and the reception destination.
"PCB (protocol control byte)" is a communication control byte and is used for controlling the communication layer such as a retransmission request at the time of a communication error. "LEN" means "INFORMATION section"
The length of (data part) is shown. "EDC" is "NA
EXOR is performed from the "D" to the last byte of the "INFORMATION section", which is a code used for detecting a communication error. (B) is a format of ATR (answer-to-reset) information from the IC card of this type.

In the figure, (C) is another type of IC.
It is a transmission format used for cards. "SR
"A" is the start flag (3Ah), "LEN" is the communication data length, that is, the sum of the number of bytes in the "INFORMATION section" and "BCC", and "BCC" is "LEN" for detecting a communication error. From "INFORMATI
It shows EXOR up to the last byte of "ON part".
(D) shows the format of ATR information by this type of IC card.

The operation of the reader / writer having the above configuration will be described with reference to FIGS.
This will be described based on the flowchart of FIG.

The protocol of each IC card is set when the IC card is reset in the read / write process. Figure 5
The processing of the IC card reset command will be described based on FIG. After supplying Vcc and CLK from the read / writer 300 to the IC card 200, first, a reset signal is sent from the RST (S501) and ATR information from the IC card 200 is received (S502). At this time, ICP
F (IC card protocol flag) is set to 0 (S503). The first 1 byte of this ATR information is "3F
In the case of "h" (YES in S504), 1 is set in ICPF (S505). This is the case of FIG. This flag “ICPF” is for making the reader / writer 300 discriminate the transmission format of the IC card 200.

FIG. 6 shows a main flowchart. When the reader / writer 300 is powered on, the host device 1
The communication interface SCI1 on the 00 side is initialized (S601), and then the interface SCI2 on the IC card 200 side is initialized (S602). For example, transfer formats such as communication speed, parity, stop bit, and character configuration are set. Also, the transmission data register (TDR1) of the interface SCI1
Then, the reception data register (RDR1) is made operable (TE = 1, RE = 1). Furthermore, the interface S
The reception data register (RDR2) of CI2 is enabled (RE = 1).

Then, the address initial value (RDPT) of the reception pointer is set in the register 2 (R2), and the address initial value (TDPT) of the transmission pointer is set in the register 3 (R3) (S603). Further, "2" is set in the register 4 (R4) (S604).

Here, it is checked whether or not the ICPF is 1 (S605). When the ICPF is 1, since data communication is performed with the IC card 200 having the format shown in the transmission format example 1 (FIG. 4A), the register 4 (R4) is incremented by 1. (S606). Other IC card 200
Since it has the format of FIG. 4C, for example, the routine proceeds to the data receiving routine from the host device 100 without incrementing the register 4 (S60).
7). With this ICPF, the length of the data to be received in the register 4 is set to 3 bytes (NAD, PCB, LEN) or 2 bytes (SRA, LEN). The host reception routine is shown in FIG.

Then, it is judged whether the received data from the host device 100 is addressed to the reader / writer 300 (S608), and if it is not the data addressed to the reader / writer (R / W), this is an IC card. This is the case where the data from 200 should be transmitted to the host device 100. For this reason,
The address initial value (RDPT) of the reception pointer is stored in the register 2 (R2) and the address initial value (TDP) of the transmission pointer is stored.
T) is set in the register 3 (R3) (S609).
Then, the transmission routine to the host device 100 is executed (S610). A transmission routine to the host device 100 is shown in FIG.

If the data is addressed to the reader / writer 300 (YES in S608), the process in the reader / writer 300 is executed (S611), and the contents after the process are read by the reader / writer 30.
It is transmitted from 0 to the host device 100 side (S612). Then, the process returns to the state of waiting for data reception (return to S603).

Host device 1 shown in step S607.
FIG. 8 shows a host reception routine for receiving the data from 00 and transmitting it to the IC card 200. First, it is determined whether the receive data register full (RDRF1), which is a flag of the host-side interface SCI1, is 1, and if it is 1, 1 byte is received (YES in S801), and the received data is stored. Data is set in the register 1 (R1) from the received data register (RDR1) (S802).

Then, it is determined whether this data (transmission format "NAD") is addressed to the reader / writer 300 or the IC card 200 (S803). Data in register 1 (R1) for reception is a reader / writer (R / W)
In the case of addressing (YES in S803), the reader / writer (R /
The reception process (IC card reset, etc.) in W) is executed (S815), a response is transmitted to the host device 100, and the process returns to reception.

When the received data is addressed to the IC card 200 (NO in S803), the IC card side interface SC
The I2 transmission data register (TDR2) is set to the operable state (S804). That is, data can be transmitted to the IC card 200 by setting TE (Transmit Enable) = 1. In addition, the communication counter (TCT) is cleared. Then, the 1-byte transmission routine is executed (S805). The routine is shown in FIG.

The next step S806 shows an HRIT routine (host device reception IC card transmission). In this routine and step S807, 3 bytes (NAD, PCB, LEN) from the beginning of the data are received and transmitted to the IC card 200. To do. In step S807, it is determined whether the value of the communication counter (TCT) has reached 3. Until the counter reaches 3, a routine for receiving data from the host device 100 side is executed (S806). When the reception / transmission of 3-byte data is completed (Y in S807)
ES), 2 bytes are added to the reception register (R1) to indicate the length of the total number of data (S80).
8). That is, when "LEN" is received, the register (R
The value of 1) is set to (R1 + 2) (S808).

Then, it is determined here whether the ICPF is 1 (S809), and if so, the value of the register R1 is advanced by 2 (S810). As a result, register R1
The value of is incremented by 4. When the ICPF is 0 (IC card corresponding to the format of Example 2 in FIG. 4), addition to the register (R1) is not performed.

Then, the value of the register (R1) is set in the register (R0) (S811). further,
The HRIT routine is executed (S812), and it is determined whether the value of the counter TCT is equal to the value of the register R0 (S813). IC card 20 for all bytes
It is transmitted to 0. After receiving the "Information section" and "EDC", use this for the IC card 2
00, and the communication counter (TCT) registers 0
When it becomes equal to the value of (R0) (YES in S813), the flag TE of the interface SCI2 is set to 0 (S81).
4) The data from the IC card 200 can be received, and the process returns to the main routine.

In the 1-byte transmission routine shown in FIG. 7, first, the transmit data register empty (TDR
It is determined whether E2) is 1 (S701), and if this flag is 1 (YES in S701), register 1 (R1)
Of the data is set in the transmission data register (TDR2) (S702). Next, 0 is set in the transmit data register empty (TDRE2) (S70
3) Further, the communication counter (TCT) is incremented by 1 (S704). If the transmit data register empty (TDRE2) is 0 (NO in S701), the value of register 1 (R1) is set to register 2 (R2).
The register 2 (R2) is incremented (@ R2 +) (S705). Then, a data reception routine from the host device 100 (S80 of FIG. 8)
Return to 6).

The HRIT routine is shown in FIG. This routine is for receiving data from the host device 100 and transmitting this data to the IC card 200. First,
It is determined whether the receive data register full (RDRF1) is 1 (S901). When the reception data register RDR is full, this flag becomes 1 (Y in S901).
ES) and the value of the reception data register (RDR1) are set in the register 1 (R1) (S902). Then, the receive data register full (RDRF1) flag is cleared (S903). Next, it is determined whether or not the transmit data register empty (TDRE2) is 1 (S904). It is to check whether data can be transmitted to the IC card 200. If 1 (S9
(YES in 04) Transmission is possible, and the value of the reception pointer of the register 2 (R2) is compared with the value of the transmission pointer of the register 3 (R3) (S905). This is to determine whether or not there is data to be transmitted in the buffer.

When the values indicated by these pointers are different (NO in S905), the data indicated by the register 1 (R1) is saved in the buffer (@ R2 +) (S906),
Register 1 (R1) from address of register 3 (R3)
(S907). Then, step S908
Proceed to.

When the value of the reception pointer is the same as the value of the transmission pointer (YES in S905), that is, when there is no data to be transmitted in the buffer, the process proceeds to step S908 and the register 3 (R3) is incremented (@ R3).
Then, the register 1 (R1) is set in the reception data register (TDR2). Furthermore, the communication counter (T
CT) is incremented (S909), the transmit data register empty (TDRE2) is cleared (S910), and the process returns to the host side reception routine (S807). This means that 1-byte transmission has been completed.

In step S904, if the transmit data register empty (TDRE2) is 0, it means that the transmission data register TDR is full, so that the IC card 200 is not transmitting or is transmitting. In this case, the reception data of the register 1 (R1) is set in the buffer (@ R2 +) (S911), and the process returns to the host side reception routine (S807). That is, the data of the register R1 is stored in the address of the register R2 and the received data is buffered.

When the receive data register full (RDRF1) is 0 in step S901, the transmit data register empty (TDR) is set.
If E2) is 1 (YES in S912), register 2
The value of (R2) is compared with the value of register 3 (R3) (S913). The contents of the reception pointer are compared with those of the transmission pointer. If these values are different (NO in S913), the flow advances to step S907 to set 1-byte data from the start address (@ R3 +) of the register 3 (R3) in the register 1 (R1). Further, the value of the register 1 (R1) is set to the transmission data register (T
DR2) (S908), communication counter (TC
T) is incremented (S909), 0 is set in the transmit data register empty (TDRE2) (S910), and the process returns to the host side reception routine (S807). One byte is transmitted to the IC card 200 side.

FIG. 10 shows a routine for receiving data from the IC card 200. In this case, first, the communication counter (TCT) is cleared (S1001), and 3 bytes (NAD, PCB, LEN) are set in the IRHT routine (I
It is received by the C card reception host transmission routine) and transmitted to the host device 100 (S1002, S1003).

When "LEN" is received, the register (R1)
Is set to (R1 + 2) (S1004) and ICPF is set to 1
It is checked whether or not (S1005). The type of the IC card 200 is checked by the transmission format. IC card 200 is ISO type (Fig. 4 (A))
If so (YES in S1005), 2 is further added to the value of the register (R1) (S1006).

Then, the data of the register 1 (R1) is set in the register (R0) (S1007). further,
Execute the IRHT routine and execute "Information section"
And "EDC" are received and transmitted to the host device 100 (S1008). When the communication counter (TCT) reaches (R0), the transmission is completed (YES in S1009), and the process returns to the main routine.

The IRHT routine is shown in FIG. When the flag (RDRF2) becomes 1 (YE in S1101)
S), the data of the register (RDR2) is set in the register (R1) for transmission (S1102), and this flag (R
DRF2) is cleared (S1103). This flag (RDRF2) indicates whether or not data is received from the IC card 200.

Next, if the flag (TDRE1) is 1 (S1104), data can be transmitted to the host device 100, so the value of the receive pointer of the register (R2) and the transmit pointer of the register (R3). Is compared (S1106), and if they are the same, there is no transmission data in the buffer, so the data in the register (R1) is set in the transmission data register TDR1 (S1107).
Then, the communication counter TCT is incremented (S1
108) and clear the flag TDRE1 (S110).
9). By this step S1107, 1-byte data is transmitted to the host device 100.

When the pointer value is different (NO in S1106), the value of the register (R1) is buffered (@ R2 +).
(S1110). And the register (R3)
Is set in the register (R1) from the address of and the register (R3) is incremented (@ R3 +) (S111).
1). Then, the process proceeds to step S1107, the data of the register (R1) is set in the reception data register (TDR1), and the counter (TCT) is incremented (S
1108), clear the flag (TDRE1) (S1
109) and return.

If the flag (TDRE1) is 0 (NO in S1104), the data in the register (R1) is buffered in the buffer (@ R2 +) and the process returns (S1105). When the data is being transmitted, the data is buffered.

In step S1101 described above,
When the flag (RDRF2) becomes 0, the flag (TDRE
It is checked whether 1) is 1 (S1112). When the flag (TDRE) becomes 1, the value of the transmission pointer and the value of the reception pointer are compared (S1113). If these values are different (NO in S1113), 1 byte is registered from the start address of the buffer (@ R3 +). Set to (R1) (S1111) and register (R1) to register (TD
R1) (S1107), counter (TCT)
Is incremented (S1108) and the flag (TD
0 is set in RE1) (S1109) and the process returns.

[0040]

With the IC card reader / writer according to the present invention, the processing speed of data communication and the entire system can be improved with respect to an IC card system having a different transmission format between the interface on the IC card side and that on the host device side. It is possible to provide an interface that enables data communication without reducing the processing speed of.
For example, high-speed data communication processing can be performed on various IC cards having different transmission formats.

[Brief description of drawings]

FIG. 1 is a block diagram showing an IC card system according to the present invention.

FIG. 2 is a block diagram showing an IC card system according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a reader / writer for an IC card according to an embodiment of the present invention.

FIG. 4 is a diagram showing a format of communication data according to an embodiment of the present invention.

FIG. 5 is a flowchart showing processing of a reset command of an IC card according to an embodiment of the present invention.

FIG. 6 is a flowchart showing a main routine in the reader / writer according to the embodiment of the present invention.

FIG. 7 is a flowchart showing a 1-byte transmission routine in the reader / writer according to the embodiment of the present invention.

FIG. 8 is a flowchart showing a data reception routine from a host device according to an embodiment of the present invention.

FIG. 9 is a flowchart showing a procedure of receiving data from the host device and transmitting the data to the IC card according to the embodiment of the present invention.

FIG. 10 is a flowchart showing a procedure for receiving data from the IC card according to the embodiment of the present invention.

FIG. 11 is a flowchart showing an IC card reception host device transmission routine according to an embodiment of the present invention.

[Explanation of symbols]

 100 Host Device 200 IC Card 300 Reader / Writer 310 Interface Device 311 Buffer Means 312 Detecting Means 313 Buffer Control Means

Claims (1)

[Claims] 1. A reader / writer for an IC card, which is connected to a host device and an IC card and is capable of performing data communication with each of them, and an interface device connected to the host device and / or the IC card. This interface device includes a buffer means for temporarily holding communication data, and a difference between a transmission format between the host device and the IC card and that between the IC card and the host device in data communication between the host device and the IC card. And a buffer control means for causing the buffer means to hold communication data having a data amount corresponding to the difference between the transmission format with the host device and that with the IC card. IC card reader / writer.