JPH0760866B2 - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device capable of writing and erasing data, and more particularly to a memory including an offset transistor. The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device having cells.

(Prior Art) A conventional nonvolatile semiconductor memory device will be described below with reference to FIGS. 11 to 14.

FIG. 11 is a sectional view showing the structure of a transistor used as a memory cell in a conventional EPROM.

In FIG. 11, an n-type source / drain region 102 having a conductivity type opposite to that of the substrate 101 is formed in a p-type semiconductor substrate 101. Further, a floating gate 104 made of a first polysilicon layer is formed on the substrate 101 with a first insulating film 103 interposed therebetween.
Further, a control gate 106 made of a second polysilicon layer is formed via a second insulating film 105.

In the memory cell having such a configuration, the threshold value of the transistor differs depending on whether or not electrons are stored in the floating gate 104. From now on, for the sake of convenience, a transistor composed of such a floating gate and a control gate will be referred to as a floating gate.
Call it a transistor. Data is read from the memory cell according to this difference in threshold value. For example, one word line is selected by the output of the row decoder, and 5V is applied to the control gate via this word line. At this time, whether the floating gate transistor is turned on or not is determined by the threshold value. Specifically, the bit line connected to the load element is connected to the drain of this floating gate transistor, and if the threshold value is low, the current flows through this load element to the floating gate transistor to cause the bit line to flow. Becomes a low potential. If the data is "1" in this case, this low potential is read by the sense amplifier and the stored data "1" is judged. If the threshold value is high, no current flows through the floating gate transistor, and the bit line is charged by the load element to become a high potential, and it is determined that data "0" is stored.

The method of accumulating electrons in the floating gate 104 is to inject the hot electrons into the floating gate 104 by applying high potential to the control gate 106 and the drain of the floating gate transistor to generate hot electrons. Accumulate.

In addition, a method of extracting electrons is such that electrons are emitted from the floating gate 104 to the drain by using the tunnel effect of the first insulating film 103 by applying 0V to the control gate of the floating gate transistor and applying a high potential to the drain. .

Since the electrons can be injected into and discharged from the floating gate 104 by the above two methods, the memory cell in FIG. 11 can electrically write and erase data.

This memory cell arranged in a matrix is the 12th
Shown in the figure.

In FIG. 12, RD is a row decoder, CD is a column decoder, C11 to C13, C21 to C23, C31 to C33 are memory cells, and WL.
1 to WL3 are word lines, and BL1 to BL3 are bit lines.

This memory is electrically erased by using a plurality of floating gate transistors connected to the same bit line as a unit. That is, when WL1 to WL3 are set to 0V and a high voltage is applied to BL2, the memory cells C21 to C23 are erased at once.

In order to extract electrons in the same bit line unit in this way, if there is a variation in the amount of electrons stored in the floating gate 104 on this same bit line, the floating gate in which the largest amount of electrons are stored is stored. Therefore, a high potential is applied to this bit line until all the electrons escape from. That is, in the floating gate 104 in which almost no electrons are accumulated, the electrons are excessively extracted and strongly charged in the positive direction. This is called an over-erased state. That is, the memory cell C21 has data “1”, the memory cell C2 has
Considering the case where C23 is data “0”, memory cell C22,
While the electrons are sufficiently stored in the floating gate 104 of C23, almost no electrons are stored in the floating gate 104 of the memory cell C21. In this state, when a high voltage is applied to BL2 and the memory cells C21 to C23 are collectively erased, the memory cell C21 is in the over-erased state and becomes depletion.
Since the threshold value becomes negative, current flows between the source and the drain even if the potential of the control gate 106, that is, the word line WL1 is 0 V (ground potential).

FIG. 12 shows an example in which an overerased memory cell exists and a malfunction occurs due to a cell current flowing through this memory cell.

In FIG. 12, RD is a row decoder, CD is a column decoder, C11 to C13, C21 to C23, C31 to C33 are memory cells, and WL.
1 to WL3 are word lines, and BL1 to BL3 are bit lines. Now
The memory cell C21 is in the over-erased state and the memory cell C22 is in the written state. Here, in order to select the memory cell C22 in the written state, for example, 2V is supplied to the bit line BL2 selected by the column decoder CD, and the other bit lines BL1, BL2
Is released (OPEN). Further, for example, 5V is supplied to the word line WL2 selected by the row decoder RD, and the other word lines WL1 and WL3 are set to the ground potential, for example, 0V. Since the memory cell C22 selected in this way is in the write state, the floating gate transistor is turned off, and the cell current does not flow, so the potential of the bit line BL2 does not originally change and the sense amplifier (not shown) is used. As a result of the sensing operation, data “0” is read. However, if an over-erased memory cell C21 exists on the same bit line BL2, the floating gate transistor of this memory cell C21 is depleted, and even if the control gate has a ground potential of 0 V, the cell current is It flows and changes the potential of the bit line BL2. Since the sense amplifier reads this change in potential, it is determined that the data “1” is stored in the selected memory cell C22. That is, it causes a malfunction. To prevent over-erasing due to such a difference in initial data (cells with "1" data and cells with "0" data are mixed), write to all memory cells before erasing. Then, the floating gates of all the memory cells are made to have a sufficient amount of electrons accumulated therein (this is called initialization), and then erasing is performed.

If the erasing time is too long, too many electrons will be extracted from the floating gate, and the over-erased state will still occur. Therefore, the erasing / verifying method is used. That is, at the time of electrical erasing, the high voltage applied to the drain is made into a short pulse waveform, and reading is performed every time this pulse waveform is applied. That is, the electron is gradually extracted from the floating gate, and the erased state is checked each time to avoid the over-erased state. However, these methods are very complicated and it takes a long time to complete the erasing, so that the function as a semiconductor memory is significantly deteriorated.

In order to solve such a problem, a transistor having no floating gate is provided adjacent to the floating gate transistor in the channel length direction. This transistor is called an offset transistor for convenience. The gate of this offset transistor is connected to the same word line as the control gate of the floating gate transistor.

A memory cell including the offset transistor will be described with reference to FIGS. 13 and 14.

In FIG. 13, an n-type source / drain region 102 having a conductivity type opposite to that of the substrate 101 is formed in a p-type semiconductor substrate 101. Further, a floating gate 104 made of a first polysilicon layer is formed on the substrate 101 with a first insulating film 103 interposed therebetween.
Further, a control gate 106 made of a second polysilicon layer is formed via a second insulating film 105. The control gate 106 also serves as the gate of the offset transistor without the floating gate 104 interposed.

In the memory cell having such a configuration, the floating gate 104 in the floating gate transistor section is in the over-erased state, and even if the floating gate transistor is depleted, the offset transistor adjacent to the floating gate transistor is not erased.
Since the threshold voltage does not change, the offset transistor does not turn on if the gate potential is the ground potential. Therefore, the floating gate 104 is over-erased,
Even if the floating gate transistor is made depletion, the cell current does not flow in the memory cell due to the provision of the offset transistor.

In FIG. 14, RD is a row decoder, CD is a column decoder, C11 to C13, C21 to C23, C31 to C33 are memory cells, and WL.
1 to WL3 are word lines, and BL1 to BL3 are bit lines. Now
The memory cell C21 is in the over-erased state and the memory cell C22 is in the written state. Here, in order to select the memory cell C22 in the written state, for example, 2V is supplied to the bit line BL2 selected by the column decoder CD, and the other bit lines BL1, BL2
Is released (OPEN). Further, for example, 5V is supplied to the word line WL2 selected by the row decoder RD, and the other word lines WL1 and WL3 are set to the ground potential, for example, 0V. Since the memory cell C22 selected in this way is in the write state, the floating gate transistor is turned off and no cell current flows, so the potential of the bit line BL2 does not change, and the sense operation by the sense amplifier (not shown) is performed. As a result, data “0” is read. At this time, the memory cell C21 in the over-erased state exists on the same bit line BL2, but since it has an offset transistor, it turns off if the control gate is at 0 V, which is the ground potential. Does not affect. Therefore, the selected memory cell C22 can read the stored data even if there is an over-erased memory cell on the same bit line.

However, in the memory cell provided with this offset transistor, since the offset transistor portion is formed in each element, the formation region must be secured within the element region, which is a problem in terms of miniaturization of the element. .

(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and an object thereof is to manufacture a nonvolatile semiconductor memory device capable of finely forming a memory cell including an offset transistor. To provide a method.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, in the present invention, a thin first insulating film is formed on a semiconductor substrate of a first conductivity type, and a first insulating film is formed. A first conductor film that will later become a floating gate is formed on the upper surface, the first insulating film and the first conductor film are patterned in stripes, and the portion patterned in stripes is used as a mask in the semiconductor substrate. An impurity isolation region for introducing memory cells of the second conductivity type into the semiconductor substrate by introducing impurities of the second conductivity type to separate the memory cells from each other between the portions patterned in the stripe pattern. Embedded with a second insulating film. Further, a mask layer is formed on at least a portion of the first conductor film that will later become a floating gate, and the mask layer and the exposed portion of the second insulating film are used as masks to form a striped pattern. Is removed to obtain a portion which will be an offset transistor portion of the memory cell later. Further, at least on the exposed portion of the first conductor film,
A third insulating film, which will later become an insulating layer for capacitively coupling the floating gate and the word line, is formed, and a second conductor film, which will later become the word line, is formed above the semiconductor substrate to form the second conductive film. The body film, the third insulating film, the first conductor film, and the first insulating film are patterned to obtain at least the offset transistor portion, the word line, and the floating gate. To introduce a first-conductivity-type impurity into the semiconductor substrate using the exposed portion as a mask to obtain a first-conductivity-type high-concentration semiconductor region which becomes an isolation region for later separating memory cells into the semiconductor substrate. Is characterized by.

Further, the mask layer is characterized in that it is formed only on the first conductor film which becomes the floating gate.

Further, when the mask layer is formed only on the first conductor film which becomes the floating gate, it is formed through either one of the portions formed on both sides of the floating gate, which will later become the offset transistor portion. Further comprising the step of introducing an impurity of the second conductivity type into the semiconductor substrate to obtain a semiconductor region of the second conductivity type in contact with the semiconductor region of the second conductivity type in the semiconductor substrate.

(Operation) According to the method of manufacturing the nonvolatile semiconductor memory device having the above-described configuration, the striped patterned portions serve as isolation regions for later separating memory cells from each other.
Embedded in the insulating film, and at least the word line and the floating gate are obtained, and the impurity of the first conductivity type is introduced into the semiconductor substrate using the word line and the exposed portion of the second insulating film as a mask. Since the first-conductivity-type high-concentration semiconductor region, which will later become an isolation region for isolating memory cells from each other, is obtained, it is not necessary to use the LOCOS method to form the isolation region for isolating memory cells. . Therefore, it is not necessary to consider the dimensional error due to the berth beak, which is a problem in the LOCOS method, and the element region in which the memory cell is formed can be set minutely.

Further, in particular, since the isolation region is formed in a self-aligned manner with respect to the structures that are sequentially produced while forming the memory cell, it is not necessary to consider misalignment of the mask when forming the isolation region. In the manufacturing method having the above-described structure, the isolation region in the channel length direction of the memory cells is formed into a second stripe-shaped portion including a portion to be a floating gate later.
In order to embed it with the insulating film, it is formed by self-alignment with the portion patterned in stripes. On the other hand, the isolation region in the channel width direction is formed in the word line and already obtained in order to introduce the impurity of the first conductivity type into the semiconductor substrate using the word line and the already obtained second insulating film as a mask. It is formed in self-alignment with the existing second insulating film.

Furthermore, the obtained offset transistor portion also has a self-aligning relationship with the isolation region in the channel length direction and with respect to the isolation region in the channel width direction.

First, the offset
The transistor portion includes a mask layer formed on at least a portion of the first conductor film to be a floating gate later,
The exposed portion of the second insulating film and the mask are formed by removing the above-described striped patterned portion, so that the second insulating film is formed in self-alignment with the isolation region in the channel length direction. On the other hand, the offset transistor portion has a self-aligned relationship with the isolation region in the channel width direction. This is because the isolation region in the channel width direction is formed using this as a mask after obtaining the word line. That is, the isolation region in the channel width direction is formed in self alignment with the offset transistor portion.

Furthermore, when the mask layer is formed only on the first conductor film that becomes the floating gate, the channel length of the floating gate obtained is always defined by the mask layer even if misalignment occurs in the mask layer. The channel length can be constant.

When the mask layer is formed only on the first conductor film, both sides of the obtained floating gate are offset.
It becomes the transistor section. In this case, among the offset transistor parts formed on both sides of the floating gate,
It is preferable to introduce impurities of the second conductivity type into the semiconductor substrate through one of them to further obtain a semiconductor region of the second conductivity type in contact with the semiconductor region of the second conductivity type.

(Embodiment) A nonvolatile semiconductor memory device according to an embodiment of the present invention and a method of manufacturing the same will be described below with reference to FIGS. 1 to 10.

(1) The first aspect of the present invention with reference to FIGS.
A non-volatile semiconductor memory device and a manufacturing method thereof according to the embodiment will be described.

FIG. 1 is a plan view of a nonvolatile semiconductor memory device according to the first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line A-- in FIG.
3 is a sectional view taken along the line A ', and FIG. 3 is a sectional view taken along the line BB' in FIG.

First, in the plan view of FIG. 1, a striped high-concentration n ⁺ type source / drain region 2 is formed in a p-type semiconductor substrate 1. Further, the word line 8 formed on the substrate 1
A p ⁺ -type region 3 having a higher concentration than that of the substrate 1 is formed for element isolation except for the portion hidden by the substrate and the source / drain region 2. The p ⁺ type region 3 separates elements in the channel width direction. Although not shown, it goes without saying that an interlayer insulating film is deposited on the entire surface of the device shown in FIG. 1 to insulate each element.

In FIG. 2, each memory cell has an inter-layer insulating film 4 over the area.
And the floating gate 6 made of the first polysilicon layer is formed in the element region via the insulating film 5. Further, a word line 8 as a control gate is formed by the second polysilicon layer via the insulating film 7. This word line 8
Is also the gate of an offset transistor which does not have the floating gate 6 adjacent to the floating gate transistor in the device region.

In FIG. 3, a p ⁺ -type diffusion layer 3 having a higher concentration than that of the substrate 1 is provided in the substrate 1 to separate the memory cells in the channel width direction. The source / drain region 2 is common. On the substrate 1, a floating gate 6 is formed via an insulating film 5, and a word line 8 as a control gate is further formed via an insulating film 7.

When writing data to this nonvolatile semiconductor memory device, a high voltage is ignited in both the control gate 8 and the source / drain region 2 to generate hot electrons and accumulate electrons in the floating gate 6 of the memory cell. . The accumulated electrons shift the potential of the floating gate 6 in the negative direction, raise the threshold value of the floating gate transistor having the floating gate 6, and at a given potential supplied to the control gate, the floating gate transistor is It will not turn on. This state is, for example, a state in which data “0” is stored.

Further, at the time of erasing, by applying a high potential to the source / drain region 2, the electrons accumulated in the floating gate 6 are utilized by utilizing the tunnel effect of the thin oxide film 5.
Emit out of.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described with reference to FIGS. 4 and 5.

4 (a) to 4 (g) are sectional views taken along the line AA 'in FIG.
5A to 5G are sectional views taken along the line
It is a cross-sectional view taken along the line BB 'in the drawing, which is shown in the order of manufacturing steps.

First, in FIGS. 4A and 5A, p-type semiconductor substrate 1 is ion-implanted with p-type impurities of the same conductivity type as substrate 1 such as B (boron) for threshold control. . Next, an oxide film 5 having a thickness of 100 Å, for example, is formed on the entire surface by a thermal oxidation method. Since this oxide film 5 is very thin,
Has a tunnel effect. Further, the first polysilicon layer 6 is deposited and formed on the entire surface by, eg, CVD method. Next, the first polysilicon layer 6 and the oxide film 5 are sequentially etched using a photoresist (not shown) having a predetermined shape as a mask. Next, by using this predetermined patterned portion as a mask, an n-type impurity of a conductivity type opposite to that of the source / drain region forming substrate 1, for example, As (arsenic) is ion-implanted and thermally diffused. ^{A +} type source / drain region 2 is formed.

In FIGS. 4B and 5B, an oxide film 4 is deposited and formed on the entire surface by, eg, CVD method. Next, the resist 9 is applied to the entire surface. Since the resist 9 is liquid, the surface after application is substantially flat.

In FIG. 4 (c) and FIG. 5 (c), the resist 9
The resist 9 and the CVD oxide film 4 are etched so as to have the same height as that of the first polysilicon layer 6 by using the same material as the CVD oxide film 4. At this time, the CVD oxide film 4 is formed so as to be embedded between the polysilicon layers 6. Next, photoresist 10 is applied, and the channel length of the floating gate is determined by mask alignment. At this time, the mask is adjusted so that the photoresist 10 remains on the region of the CVD oxide film 4.

Next, in FIGS. 4D and 5D, the polysilicon layer 6 and the oxide film 5 are sequentially etched by using the photoresist 10 as a mask. Next, an oxide film 7 having a thickness of about 500 Å is formed on the entire surface by, eg, thermal oxidation.
The oxide film 7 may have a three-layer structure of an oxide film, a nitride film, and an oxide film.

In FIG. 4 (e) and FIG. 5 (e), the
The polysilicon layer 8 is deposited and formed by, for example, the CVD method.

In FIGS. 4 (f) and 5 (f), the second polysilicon layer 8, the oxide film 7, the first polysilicon layer 6, and the oxide film 5 are predetermined using a photoresist (not shown) as a mask. Etching is sequentially performed.

4 (g) to 4 (g), the p-type impurity of the same conductivity type as the substrate 1, for example, B (boron) is ion-implanted by using the oxide film 4 and the word line 8 as a mask, By diffusion, a p ⁺ type region for element isolation having a higher impurity concentration than the substrate 1 is formed. At this time, since the interlayer insulating film 4 is present on the n ⁺ type source / drain region (not shown),
The ion-implanted B (boron) is shielded by this insulating film 4. After that, an interlayer insulating film (not shown) is deposited on the entire surface, contact holes are formed at predetermined positions, and a wiring layer made of, for example, Al (aluminum) is formed on the entire surface and patterned into a predetermined shape. A non-volatile semiconductor memory device according to the first embodiment of the present invention is manufactured by depositing and forming a surface protective film.

According to the electrically erasable nonvolatile semiconductor memory device manufactured by such a manufacturing method, the floating gate of the memory cell is in an over-erased state, and a current flows through the cell even if the control gate potential is the ground potential. The problem that the potential of the bit line changes to cause a malfunction is solved by providing an offset transistor having no floating gate. Also, in the past, selective oxidation was performed by the LOCOS method, and element isolation of memory cells was performed by a thick oxide film.
An oxide film formed in a stripe shape in a direction orthogonal to the word line,
Element isolation is performed by increasing the concentration of impurities in the substrate other than the intersection of the word line and this oxide film. When the element isolation of the memory cell is performed by such a method, the mask is used for the photo-etching process for patterning the word line and the mask for the photo-etching process for patterning the region of the interlayer oxide film 4 in a stripe pattern. The area of the cell region can be determined. Therefore, it is not necessary to consider the dimensional error due to the bird's beak between the oxidation resistant film and the oxide film, which is a problem in the LOCOS method, and the fringe of the floating gate first polysilicon in the channel width direction is not necessary. The area of the region is miniaturized. Therefore, data can be erased electrically, and even if the floating gate of the memory cell is over-erased, no current flows through the cell, and no malfunction occurs.

(2) Next, a non-volatile semiconductor memory device according to a second embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.

FIG. 6 is a plan view of a nonvolatile semiconductor memory device according to a second embodiment of the present invention, and FIG. 7 is a sectional view taken along line C- of FIG.
FIG. 8 is a sectional view taken along the line C ′, and FIG. 8 is a sectional view taken along the line DD ′ in FIG. 6. The first embodiment has a drawback that the width of the floating gate first polysilicon 6 varies due to the mask shift shown in FIG. 4C, but this embodiment improves this point.

First, in the plan view of FIG. 6, high-concentration n ⁺ type source / drain regions 2 are formed in stripes in a p-type semiconductor substrate 1. Further, a p ⁺ type region 3 having a higher concentration than that of the substrate 1 is formed for element isolation except for the portion hidden by the source / drain region 2 and the word line 8 formed on the substrate 1. The p ⁺ type region 3 separates elements in the channel width direction. Although not shown, it goes without saying that an interlayer insulating film is deposited on the entire surface of the device shown in FIG. 1 to insulate each element.

Next, in FIG. 7, the floating gate 6 made of the first polysilicon layer is formed in the element region of each memory cell with the insulating film 5 interposed therebetween. The floating gate 6 is provided apart from the insulating film 4, and an impurity diffusion layer 2'having the same conductivity type as the source / drain is provided in one of the separated regions. From this, the mask for determining the length of the floating gate 6 has a so-called self-aligned structure in which it can be placed at any position on the polysilicon layer. Moreover, since the length of the floating gate 6 is kept constant, variations in the characteristics of the memory cells are reduced, and stable memory cell characteristics can be obtained. Further, in a region where the floating gate 6 and the insulating film 4 are separated from each other,
A word line 8 which is a control gate is formed so as to cover both side surfaces of the floating gate 6. Therefore, the facing area between the control gate 8 and the floating gate 6 can be increased without increasing the area in the plane direction. Therefore, since the coupling between the floating gate 6 and the control gate 8 can be increased, the write amount can be increased and the cell current at the time of reading can be increased even in a memory cell having a small area, and the operation margin can be improved. Further, a word line 8 as a control gate is formed by the second polysilicon layer via the insulating film 7. The word line 8 also serves as the gate of the offset transistor having no floating gate 6 in the element region as described above.

In FIG. 8, the element isolation of the memory cell in the channel width direction is made by the p ⁺ type diffusion layer 3 having a higher concentration than the substrate 1 in the substrate 1. The source / drain region 2 is common. On the substrate 1, a floating gate 6 is formed via an insulating film 5, and a word line 8 as a control gate is further formed via an insulating film 7.

When writing data to this non-volatile semiconductor memory device, as in the first embodiment, a high voltage is applied to both the control gate 8 and the source / drain region 2 to generate hot electrons so that the memory cell floats. The electrons are accumulated in the gate 6. The accumulated electrons shift the potential of the floating gate 6 in the negative direction, raise the threshold value of the floating gate transistor having the floating gate 6, and at a given potential supplied to the control gate, the floating gate transistor is It will not turn on. This state is, for example, a state in which data “0” is stored.

Further, at the time of erasing, by applying a high potential to the source / drain region 2, the electrons accumulated in the floating gate 6 are utilized by utilizing the tunnel effect of the thin oxide film 5.
Emit out of. Further, the device can be erased by irradiating the device with ultraviolet rays to excite the electrons accumulated in the floating gate 6 to emit the electrons to the outside of the floating gate 6.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the second embodiment will be described with reference to FIGS. 9 and 10.

9 (a) to 9 (g) are sectional views taken along line C- of FIG.
A cross-sectional view taken along the line C ', FIGS. 10 (a) to 10 (g),
6 is a cross-sectional view taken along the line DD 'in FIG. 6 and is shown in the order of manufacturing steps.

First, in FIGS. 9A and 10A, p-type semiconductor substrate 1 is ion-implanted with a p-type impurity of the same conductivity type as substrate 1 such as B (boron) for threshold control. . Next, an oxide film 5 having a thickness of 100 Å, for example, is formed on the entire surface by a thermal oxidation method. Since this oxide film 5 is very thin,
Has a tunnel effect. Further, the first polysilicon layer 6 is deposited and formed on the entire surface by, eg, CVD method. Next, the first polysilicon layer 6 and the oxide film 5 are sequentially etched using a photoresist (not shown) having a predetermined shape as a mask. Next, by using this predetermined patterned portion as a mask, an n-type impurity of a conductivity type opposite to that of the source / drain region forming substrate 1, for example, As (arsenic) is ion-implanted and thermally diffused. ^{A +} type source / drain region 2 is formed.

9B and 10B, an oxide film 4 is deposited and formed on the entire surface by, eg, CVD method. Next, the resist 9 is applied to the entire surface. In FIGS. 9 (c) and 10 (c), the resist 9 and the CVD oxide film 4 are made to have the same height as the first polysilicon layer 6 by using the same resist 9 as the CVD oxide film 4. Etch to form. At this time, the CVD oxide film 4 is formed so as to be embedded between the polysilicon layer 6 and the polysilicon layer 6. Next, photoresist 10 is applied, and the channel length of the floating gate is determined by mask alignment. At this time, the mask is adjusted so that the photoresist 10 remains only on the upper portion of the polysilicon layer 6.

9 (d) and 10 (d), the insulating film 4 is formed by sequentially etching the polysilicon layer 6 and the oxide film 5 using the photoresist 10 as a mask.
Floating gates 6 formed further apart from each other and a thin oxide film 5 having a tunnel effect are formed below the floating gates 6. Next, a resist 11 is formed and covered on one of the separated regions. In the other separated region, an n-type impurity, which is an anti-conductive type anti-conductive type, such as As (arsenic), is ion-implanted and thermally diffused to contact the source / drain region 2. Region 2'is formed. The n-type region 2'prevents both sides of the floating gate 6 from becoming offset transistors.

Next, in FIGS. 9 (e) and 10 (e), an oxide film 7 having a thickness of about 500 Å is formed on the entire surface by, eg, thermal oxidation. The oxide film 7 may have a three-layer structure of an oxide film, a nitride film, and an oxide film.

In FIG. 9 (f) and FIG. 10 (f), the
The polysilicon layer 8 is deposited and formed by, for example, the CVD method.

In FIGS. 9 (g) and 10 (g), the second polysilicon layer 8, the oxide film 7, the first polysilicon layer 6, and the oxide film 5 are formed to a predetermined size by using a photoresist (not shown) as a mask. Etching is sequentially performed.

9 (h) to 10 (h), p-type impurities of the same conductivity type as the substrate 1, for example, B (boron) are ion-implanted by using the oxide film 4 and the word line 8 as a mask, and heat is applied. By diffusion, a p ⁺ type region for element isolation having a higher impurity concentration than the substrate 1 is formed. After that, an interlayer insulating film (not shown) is deposited on the entire surface, contact holes are formed at predetermined positions, and a wiring layer made of, for example, Al (aluminum) is formed on the entire surface and patterned into a predetermined shape. A non-volatile semiconductor memory device according to the second embodiment of the present invention is manufactured by depositing and forming a surface protective film on.

According to the electrically erasable nonvolatile semiconductor memory device manufactured by such a manufacturing method, the floating gate of the memory cell is in an over-erased state, and a current flows through the cell even if the control gate potential is the ground potential. The problem that the potential of the bit line changes to cause the device to malfunction is solved by providing an offset transistor having no floating gate. In the past, selective oxidation was performed by the LOCOS method, and element isolation of memory cells was performed by a thick oxide film. The point is that the oxide film formed in stripes in the direction orthogonal to the word line, the word line and this oxide film. In the board other than the intersection of
Element isolation is performed by increasing the concentration of impurities. When the element isolation of the memory cell is performed by such a method, the area of the memory cell region is increased by the photo-etching process mask for patterning the word line and the photo-etching process mask for patterning the oxide film in stripes. Can be determined. Therefore, it is not necessary to consider the dimensional error due to the bird's beak between the oxidation resistant film and the oxide film, which is a problem in the LOCOS method, and the fringe of the floating gate first polysilicon in the channel width direction is not necessary. The area of the region is miniaturized. Therefore, the memory of the memory cell can be erased electrically, and even if the floating gate of the memory cell is in the over-erased state, no current flows through the cell and the malfunction of the device does not occur. Further, in the second embodiment, since the floating gate 6 is formed apart from the insulating film 4, it is possible to form the floating gate with a constant length regardless of the mask misalignment. Further, since both side surfaces of the floating gate 6 are covered with the word line 8 which is a control gate, the coupling between the control gate 8 and the floating gate 6 can be increased. As a result, the write amount can be increased and the cell current at the time of reading can be increased, and the operation margin can be improved.

Therefore, by providing the floating gate separately from the insulating film for element isolation, by forming the control gate in this separated region so as to cover both side surfaces of the floating gate,
The area where the floating gate and the control gate face each other is increased, and as a result, it is possible to increase the coupling, increase the write amount, increase the read current, and improve the operation margin. Furthermore, since the length of the floating gate can be kept constant, variations in the characteristics of the memory cells are reduced, stable characteristics can be obtained, and the formation method is self-aligned.

In addition, in the method of erasing the memory of the nonvolatile semiconductor memory device according to the present invention, it is needless to say that not only the electrical memory erasing but also the memory erasing by ultraviolet rays can be performed.

As described above, according to the present invention, the offset
A memory cell with a transistor can be minutely formed,
A method for manufacturing a nonvolatile semiconductor memory device can be provided.

[Brief description of drawings]

FIG. 1 is a plan view of a nonvolatile semiconductor memory device according to the first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line A-- in FIG.
FIG. 3 is a cross-sectional view taken along the line A ′, FIG. 3 is a cross-sectional view taken along the line BB ′ in FIG. 1, and FIG. 4 is a cross-sectional view showing the manufacturing method of the nonvolatile semiconductor memory device in FIG. 1 is a cross-sectional view taken along the line AA 'in FIG. 1, and FIG. 5 is a cross-sectional view showing the manufacturing method of the nonvolatile semiconductor memory device in FIG. 1 in the order of manufacturing steps. 6 is a sectional view taken along the line -B ', FIG. 6 is a plan view of the nonvolatile semiconductor memory device according to the second embodiment of the present invention, and FIG. 7 is a sectional view C of FIG.
8 is a sectional view taken along the line -C ', and FIG. 8 is a sectional view taken along the line DD' in FIG.
9 is a cross-sectional view showing the method of manufacturing the nonvolatile semiconductor memory device of FIG. 6 in the order of manufacturing steps,
6 is a sectional view taken along the line CC 'of FIG. 6, and FIG. 10 is a sectional view showing the method of manufacturing the nonvolatile semiconductor memory device of FIG. 6 in the order of manufacturing steps. 11 is a cross-sectional view taken along line 11 of FIG.
FIG. 13 is a circuit diagram of a nonvolatile semiconductor memory device including the memory element of FIG. 11, FIG. 13 is a cross-sectional view of a conventional nonvolatile memory element including an offset transistor,
FIG. 14 is a circuit diagram of a nonvolatile semiconductor memory device including the memory element of FIG. 1 ... p-type semiconductor substrate, 2 ... n-type source / drain region, 2 '... n-type region, 3 ... p ⁺ -type region for element isolation, 4
... Insulating film for element isolation, 5 ... Insulating film having tunnel effect, 6 ... Floating gate made of first polysilicon layer,
7 ... Insulating film, 8 ... Control gate (word line), 9 ...
Resist, 10 …… Resist, 11 …… Resist, 101 ……
p-type semiconductor substrate, 102 ... Source / drain region, 103 ...
… Insulating film, 104… Floating gate, 105… Insulating film, 106…
Control gate, RD, row decoder, CD, column
Decoder, C11 to C13, C21 to C23, C31 to C33 ... Memory cells, BL1 to BL3 ... bit lines, WL1 to 3 ... word lines.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/792 (72) Inventor Masamichi Asano 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Pref. (72) Inventor Tadashi Miyagawa, No. 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock Company, Toshiba Corporation (72) Inventor Tadayuki Taura, No. 1 Komukai-Toshiba, Saiwai-ku, Kawasaki-shi, Kanagawa Stock company Toshiba Tamagawa Plant (56) Reference JP 62-163376 (JP, A) JP 62-115777 (JP, A) JP 64-18270 (JP, A) Special Table 1- 501746 (JP, A)

Claims (3)

[Claims] 1. A step of forming a thin first insulating film on a semiconductor substrate of a first conductivity type, and a first conductor film which will later become a floating gate is formed on the first insulating film. A step of patterning the first insulating film and the first conductor film in a striped pattern, and a second conductivity type impurity in the semiconductor substrate using the striped pattern as a mask. A step of introducing a semiconductor region of the second conductivity type having a stripe shape in the semiconductor substrate, and forming a separation area for separating memory cells later between the stripe-patterned portions. A step of burying with a second insulating film; a step of forming a mask layer on at least a portion of the first conductor film that will later become a floating gate; and a step of exposing the mask layer and the second insulating film. As a mask, A step of removing the stripe-patterned portion to obtain a portion which will later become an offset transistor portion of the memory cell, and a floating gate and a word line are formed on at least the exposed portion of the first conductor film. A step of forming a third insulating film which becomes an insulating layer for bonding, a step of forming a second conductor film which will later become a word line above the semiconductor substrate, and the second conductor Patterning the film, the third insulating film, the first conductor film and the first insulating film to obtain at least an offset transistor portion, a word line and a floating gate, the word line, and A second conductivity type impurity is introduced into the semiconductor substrate using the exposed portion of the second insulating film as a mask, and an isolation region for later separating the memory cells into the semiconductor substrate. Method of manufacturing a nonvolatile semiconductor memory device characterized by comprising the step of obtaining a high-concentration semiconductor region of the first conductivity type serving. 2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the mask layer is formed only on the first conductor film which becomes the floating gate. 3. The first mask layer serves as the floating gate.
Impurity of the second conductivity type in the semiconductor substrate through one of the parts formed on both sides of the floating gate, which will later become the offset transistor part, when formed only on the conductor film. 3. The non-volatile semiconductor memory device according to claim 2, further comprising the step of: introducing a second conductivity type semiconductor region into the semiconductor substrate, the second conductivity type semiconductor region being in contact with the second conductivity type semiconductor region. Manufacturing method.