JPH0759126A - Parallel time division multiplex memory switch circuit - Google Patents

Abstract

PURPOSE:To reduce the total bit number of a memory of the parallel time division multiplex memory switch circuit. CONSTITUTION:Input output paths are divided into m-groups each comprising n/m paths, where (n) is the number of the input output paths and (m) is the number of parallel circuits, each parallel conversion circuit provided to each group converts an input signal into a parallel signal in parallel by a multiple of (m) at a speed lower by a multiple of (m) comprising n-bit parallel and n/m word series in the unit of n-bits comprising n/m parallel/n-bit serial, m-sets of memories of n-bit parallel/n/m<2> words are provided to each of m-sets of memory switch circuits, signals of n/m sets of input paths at maximum connecting to n/m sets of output paths of the memory switch circuit are selected from m-groups of n-bit parallel/n/words serial signals subjected to parallel conversion precedingly in each word timing of 1-n/m and all written in addresses 1-n/m<2> of m-sets of memories, n/m-Sets of input paths connecting to n/m-sets of output paths of each memory switch circuit are selected in each word timing of 1-n/m corresponding to the order of output paths and low speed parallel output signals of n-bit parallel/n/m word serial are read from a corresponding address of m-sets of memories.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path switch circuit using a time division multiplex memory switch circuit in a PCM communication system, and particularly to reducing the number of memory pits of a parallel time division multiplex memory switch circuit installed in parallel for high speed operation. Memory switch circuit configuration.

[0002]

2. Description of the Related Art In the PCM communication system, as a connection switch circuit for freely connecting signals from a plurality of input paths to a plurality of output paths, the input path signals are time-division multiplexed in the order of the input paths and are arranged in the order of the input paths. A time division multiplex memory switch circuit is used which sequentially writes to a memory at a write address, reads from the memory at an output path order address, and converts the original path signal to output after time division separation conversion.

In the time-division multiplexing memory switch circuit, the memory write / read operation speed is the limiting factor of the maximum number of paths or the maximum input / output signal speed.

Conventionally, as one method for overcoming this limiting factor, a plurality of time division multiplexed memory switch circuits are arranged in parallel, one input signal is converted into a plurality of low speed parallel signals, and the parallel signals are respectively converted. A parallel time-division multiplex memory switch that supplies the parallel time-division multiplex memory switch circuit, operates each parallel time-division memory switch at a low speed, and serializes a plurality of time-division multiplex memory switch circuit outputs to obtain an output signal. Circuit is used.

FIG. 9 shows a configuration example of a conventional time division multiplexing memory switch which does not parallelize the number of input / output paths of 8, and FIGS. 10 and 11 show operation time charts thereof.

As an example of the path connection between input and output, output path 0 ← input path 5, output path 1 ← input path 0 shown in FIG.
Output path 2 ← input path 1, output path 3 ← input path 4, output path 4 ← input path 3, output path 5 ← input path 0, output path 6 ← input path 2, output path 7 ← input path 6, input path 7 shows the case without connection.

FIG. 12 shows an example of the structure of a conventional time-division multiplexed memory switch in which the number of input / output paths is 8 and the number of parallels is 2, and FIGS. 13 and 14 are operation time charts thereof. An example of the connection between the input and output paths is FIG. 5, which is the same as FIG.

In FIG. 9, 10 to 17 are shown in FIG.
a to 17a, the input terminals of the bit serial and 8-path parallel input signals from the eight input PCM signal paths, 201 is 1
8 bit serial / path parallel signals of 0a to 17a are time-division multiplexed structural unit: word timing 0 of frame
7 (= input signal bit timing) is shown in 2010a to 2017a in FIG. Eight 8-bit parallel
It is an 8-bit * 8-word serial-parallel conversion circuit that converts an 8-word serial signal.

Reference numeral 501 indicates signals 2010a-20 of paths 0-7 from the serial / parallel circuit 201 at word timings 0-7.
A write address generation circuit for sequentially generating write addresses 0 to 7 shown by 501a when 17a arrives;
Reference numeral 1 is an 8-bit * 8-word memory for sequentially writing the output signals 2010a to 2017a of the serial / parallel conversion circuit 201 to the write address (16) 501a indicated by the write address generation circuit 501 word by word. The read address 6 of the memory 301 in which the signal of the input path corresponding to the output path is written in 7
01a are sequentially generated for each word, and the output of the memory 301 is an 8-bit parallel / 8-word serial time-division signal output 301.
It is a read address generation circuit for obtaining 0a to 3017a.

Reference numeral 801 designates eight of these 3010a to 3017a, which are eight 8-bit parallel / 8-word serial 2, and signals 71a to 7a.
8a of 8a, 8p shown by 8 bit serial / path parallel signals
It is a parallel-serial conversion circuit of 8 bits * 8 words which is converted into output signals to the output terminals 70 to 77 of the CM signal path.

In this configuration, the memory 301 has the structure shown in FIG.
As shown in the word timing-write address-input path number comparison table of (A), the signals of the input paths 0 to 7 are sequentially written at addresses 0 to 7 at word timings 0 to 7.

Further, the reading of the memory 301 is shown in FIG.
As shown in the word timing-read address comparison table of (B), write addresses 5, 0, 1, 4, 3 of the input path numbers connected to the output paths in the order of output paths 0 to 7 at word timings 0 to 7. , 0, 2, 6 in this order.

In this configuration, one memory of 8-bit / 8-word configuration is used, and the total number of memo bits is 6.
It is 4 bits.

In FIG. 12, 10 to 17 are, as shown in FIG. 13, bit serial signals from eight input PCM signal paths which are the same as those in FIG. 9 shown by 10a to 13a and 14a to 17a.
Input terminals for path parallel input signals, 202 and 212 are 10a
~ 13a or 14a to 17a, four 8-bit serials 4
The path parallel signal is transmitted at word timings 0 to 3 (bit timing 0 for each parallel time division multiplexing structural unit (= frame)).
~ Half speed of ~ 7) 8 bits * 4 pass units in 2020a to 2027a or 2124a to 2127a in FIG.
Is an 8-bit * 4-word serial-parallel conversion circuit for converting into eight 8-bit parallel / 4-word parallel low-speed serial signals.

Reference numeral 502 denotes a signal 2 of paths 0-3 and 4-7 from the serial / parallel circuits 202 and 212 at word timings 0-3.
Write address generation circuits 302 and 312 which sequentially generate addresses 0 to 3 shown by 502a when 020a to 2027a and 2120a to 2127a arrive.
Output signal 2020 of serial-parallel conversion circuit 202 to address 2a
It is a memory of 8 bit * 4 word configuration in which a to 2027a are sequentially written.

Reference numerals 312 and 332 are 8-bit * 4 word memory 602 for sequentially writing the output signals 2120a to 2127a of the serial / parallel conversion circuit 212 to the write address 502a indicated by the write address generation circuit 502.
Is a memory read selection signal 6020a and a memory 302, 312 that selects the memory on the side where the signals of the corresponding input path are written from the memories 302, 312 in the order of output paths 0-3 at word timings 0-3. Read address 6021a is sequentially generated for each word,
Time-division multiplexed signal output 3 to the outputs of the memories 302 and 312
This is a read address generation circuit for obtaining 020a to 3027a and 3120a to 3127a.

Reference numeral 612 denotes a memory read selection signal 6120a for selecting the memory on the side where the signals of the corresponding input paths are written from the memories 322 and 332 in the order of the output paths 4 to 7 at the word timings 0 to 3 and The read addresses 6121a of the memories 322 and 332 are sequentially generated, and the time division multiplexed signal outputs 3220a to 3227a and 3320a to 3327 are output to the outputs of the memories 322 and 332.
It is a read address generation circuit for obtaining a.

Reference numerals 802 and 812 denote parallel low-speed time division multiplexed signal outputs 3020a to 3027a and 3120a to 312 from the memories 302 and 312 or the memories 322 and 332.
7a or 3220a-3227a, 3320a-33
27a to output terminals 70 to 73 or 3220a to 32
27a, 3320a to 3327a, output terminals 70 to
Output of 73 or 74 to 77 4 of 70a to 73a or 4 of 74a to 77a, 8 bit * 4 word converted to 8 bit serial / 4 path parallel signal to obtain output signal of 8 PCM signal paths Is a parallel-to-serial conversion circuit.

In this configuration, the memories 302, 312, 32
2, 332, as shown in the word timing-write address comparison table of FIG.
Then, the signals of the input paths 0 to 3, the input paths 4 to 7, the input paths 0 to 3, and the input paths 4 to 7 are sequentially written to the addresses 0 to 3. The same signals are written in the memory 302, the memory 322 and the memory 312, and the memory 332.

The reading of the memories 302 and 312 is shown in FIG.
As shown in the word timing-read address correspondence table of (B), input path numbers 5, 0, 1, and 4 are connected to the output paths in the order of output paths 0 to 3 at word timings 0 to 3.
In order. In FIG. 14B, the number in parentheses indicates the path number for reading / writing at that address.

The reading of the memories 322 and 332 is performed in the order of input path numbers 3, 0, 2 and 6 connected to each output path in the order of output paths 4 to 7 at word timings 0 to 3.

This configuration uses four memories each having an 8-bit / 4-word configuration, and the total number of memory bits is 1.
28 bits are required twice as much as 64 bits in FIG.

In this method, in general, when n time-division multiplexed memory switch circuits for n paths are arranged in parallel, m sub time-division multiplexed memory switch circuits installed in parallel each have a speed of 1 / m. Although it operates, the number of memory bits is required to be the same as the original number of memory bits before parallelization n ² bits, and m × n ² bits of memory are required m times as a whole.

[0024]

In the conventional parallel time division multiplex memory switch, the operation speed of each sub time division multiplex memory switch circuit installed in parallel decreases due to the parallel installation. The number of memory bits of the sub time division multiplex memory switch circuit was the same as that of the original time division multiplex memory switch.

Therefore, although the number of input paths and the number of output paths to which one sub-time-division multiplexing memory switch circuit arranged in parallel are substantially connected are each at most a fraction of the parallel number, each sub-time-division The number of memory bits of the multiplex memory switch circuit is the same as that of the original time division multiplex memory switch, and the total number of memory bits increases in proportion to the number of collocations.

An object of the present invention is to reduce the number of memory bits of each collocated sub-time-division multiplexing memory switch circuit to a fraction of the number of collocations so that the number of memory bits of a parallel time-division multiplexing memory switch circuit is reduced to the original value. It is an object of the present invention to provide a parallel time division multiplex memory switch circuit in which the number of memory bits does not increase by parallelizing the same time division multiplex memory switch.

[0027]

SUMMARY OF THE INVENTION A parallel time division multiplexed memory switch circuit in accordance with the present invention provides n out of n input paths.
The parallel / bit serial signal is divided into groups (m is an integer of 2 or more) for each n / m path in the order of paths, and every m group is divided into n / m parallel / n-bit serial signal units from the n / m path, m times parallel
A serial-parallel conversion circuit for converting an n-parallel / n / m word serial signal at m times slower speed, and m n of the serial-parallel conversion circuits of the m group
From parallel / n / m bit serial signal output, n / m of the m-th group
A maximum of n / m n parallel input signals connected to a plurality of output paths, a maximum of m for each word timing, a maximum of n / m between 1 to n / m word timings, and a maximum of n per circuit
/ M ² m parallel n / m: 1 selection circuits to be selected, and n parallel / n / m ² bit serial output signals of the selection circuits at any of addresses 1 to n / m ² M n-bit parallel / n / m ² word memories that are sequentially written so that they do not overlap, and a memory in which the signals of the corresponding input paths are written from the m memories in the order of output paths n / m To n / m ² words per memory at a maximum, a total of n / m words in n parallel / n / m word read address generating circuit for selectively reading serial signals, and n parallel / n / m from the m memories And a serial conversion circuit that converts a word serial parallel low-speed signal output into an n / m parallel / n-bit serial signal.

[0028]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1 shows a configuration example of a parallel time division multiplexing memory switch circuit to which the present invention is applied for the input / output path 8 and the parallel number 2, and FIGS. 2 to 4 show operation time charts thereof. The connection between the input and output paths is shown in the case of FIG. 5 as in FIGS. 9 and 12.

FIG. 6 shows a configuration example of a parallel time division multiplexing memory switch circuit to which the present invention is applied for the number of input / output paths n and the number of parallels m.

In FIG. 1, 10 to 17 are 10a in FIG.
13a and 14a to 17a, the input terminals of the bit serial / path parallel input signals from the same eight input PCM signal paths as in FIG. 9, 202 and 212 are four 8 bit serials of 10a to 13a and 14a to 17a.・ A four-path parallel signal is transmitted in parallel time-division multiplexing configuration unit: every frame,
8 bits * 4 paths in units of 2020a to 2027a in FIG.
And 2120a to 2127a, which is the same conventional 8-bit * 4-word serial-parallel conversion circuit for converting into eight 8-bit parallel / 4-word serial signals.

403 and 413 are 0 to 3 of one frame.
Signal 2020a to 2027a of paths 0 to 3 and 4 to 7 from the serial / parallel circuits 202 and 212 for each word timing of
Input signal path 0, path 1 and input signal path 4, 5 connected from 2120a to 2127a to output paths 0 to 3
Are input signals of the memory input selection signal 5030a of the write address generation circuit 503 for the path 0 at word timing 0, the path 1 at word timing 1, the path 4 at word timing 0, and the path 5 at word timing 1. In order of memory 303 and memory 313
Is a selection circuit selectively connected to.

Numeral 503 designates the signals of the input signal paths 0, 1 and 4, 5 from the selection circuits 403 and 413 at the word timings 0 and 1, for example, 0, 0 of the memories 303 and 313.
5031a, 5032a and 5 written to address 1
033a and 5034a are write address generation circuits that generate write addresses, write permission signals, and memory input selection signals of 5030a.

423 and 433 are 0 to 3 of one frame.
Signal 2020a to 2027a of paths 0 to 3 and 4 to 7 from the serial / parallel circuits 203 and 213 for each word timing of
Memory input selection signal 513 of write address generation circuit 513 for input signal path 0, path 6 and path 2 and path 3 connected from 2120a to 2127a to output paths 4 to 7.
0a, and a selection circuit that connects to the memory 303 and the memory 313 in the order of the signal of the word timing 0, the pass 0 at the word timing 2, the pass 6 at the word timing 2, the pass 2 at the word timing 2, and the pass 3 at the word timing 3, respectively. Is.

Reference numeral 513 represents the signals of the input signal paths 0, 6 and 2, 3 from the selection circuits 423 and 433 at the word timings 0, 2 and 2, 3 and the memories 303 and 3 respectively.
For example, 5131 shown in FIG.
a write address generating circuit for generating the write address and write enable signal shown at 5132a and 5133a and 5134a and the memory input selection signal at 5130a.

303 and 313 are output signals 4030a to 4037a and 4130a to 4137 of the selection circuits 403 and 413 to the write addresses 5031a and 5033a indicated by the write address generation circuit 503.
a is a write enable signal 5032 for each word timing.
It is a memory of 8-bit * 2 read configuration which is written when a and 5034a are "1".

323 and 333 are output signals 4230a to 4237a and 4330a to 4337 of the selection circuits 423 and 433 to the write addresses 5131a and 5133a indicated by the write address generation circuit 513.
a is a write enable signal 5132 for each word timing.
It is a memory of 8-bit * 2-word structure written when a and 5134a are "1".

Reference numeral 603 is word timing 0 of one frame.
A memory selection signal 6030a for selecting the memories 303 and 313 in which the signals of the corresponding input paths are written every 3 to 3 and a read address 6031a of the memory are sequentially generated, and the outputs of the memories 303 and 313 are time-division multiplexed. Signal output 3030a to 3037a, 3130a to 313
7a is a read address generation circuit for obtaining 7a.

Reference numeral 613 denotes a memory selection signal 6130a for selecting the memories 323 and 333 in which the signals of the input paths corresponding to the output paths 4 to 7 are written at each word timing of one frame: 0 to 3 and a read address of the memory. 61
31a are sequentially generated, and time-division multiplexed signal outputs 3230a to 3237a and 3330 are output to the outputs of the memories 323 and 333.
It is a read address generation circuit for obtaining a to 3337a.

Reference numerals 802 and 812 denote time division multiplexed signal outputs 30 of the memories 303 and 313 or the memories 323 and 333.
30a-3037a, 3130a-3137a or 3
230a to 3237a, 3330a to 3337a to output terminals 70 to 73 or 74 to 77, 70a to 70a of FIG.
74a or bit series shown in 74a to 77a of FIG.
13 is a conventional parallel-serial conversion circuit of 8 bits * 4 words which is the same as that of FIG. 12 and which obtains the output of a path parallel parallel sub time division multiplexing memory switch circuit.

An example of write addresses and input path numbers of the memories 303, 313, 323, 333 is shown in FIG.
The write address-input pass number comparison table is shown.

In this example, the signals of the input paths 0 and 1 and the input paths 4 and 5 are written at addresses 0 and 1 of the memories 303 and 313, respectively. The signals of the input paths 0 and 6 and the input paths 2 and 3 are written at addresses 0 and 1 of the memories 323 and 333, respectively. In this example, the signals of the input paths connected to the output paths of the sub time division multiplexing memory switch circuit are written in the order of the input paths in the left-justified order.

Correspondence between the write address input of the memory and the path number is not necessarily limited to writing from the smallest number of addresses in the order of the input path as shown in the example of FIG. 4A, and the memories 303 and 313. It suffices if the input paths 0, 1, 4, 5 are written in any of the addresses, and the input paths 0, 1, 4, 5 are written in any of the addresses in the memories 303, 313. It is a necessary condition that the signal of the input path connected to the output path of the sub time division multiplexing memory switch circuit is written in any address of the memory of the sub time division multiplexing memory switch circuit.

Write addresses 5030a and 5031
a, 5032a, 5033a, 5034a, 5130
a, 5131a, 5132a, 5133a, 5134a
Is the same as the method of generating the memory read address of the conventional time division multiplexing memory switch circuit, and the method of storing the address value according to the connection setting in the memory in advance and reading it at the word timing 0, 1, 2, 3. (Method A),
Alternatively, only the input path number position connected to the output for each sub time division multiplexing memory switch circuit is written in the memory by a flag, and the flag is read at the word timings 0, 1, 2, 3 and counted at the word timing. It can be obtained by the method (method B) or the like.

Input / output path number n = 1,024, parallelization number m
= 2, an example of the configuration of the write / read address generation circuit by the method A and the method B is shown in FIGS.
Shown in.

In method A (method of FIG. 7B), it is necessary to prepare an input path-write address comparison table in advance, but since the correspondence between word timing and input path number is fixed, When changing the connection of a partial path, it is not necessary to change the write address of the path for which the connection is not changed, and it is possible to change it by rewriting the write / read address of only the relevant connection change point.

In FIG. 7B, 90 is a 9-bit word counter, 91 is a 24-bit / 512-word memory, 92 is a connection setting data creating / writing circuit, 930.
˜933 are 8-bit counters. The number in () indicates the number of signals.

In method B (method 7 (A)), when the connection of some paths is changed, it may be necessary to change the write address even for the path for which the connection is not changed. It is necessary to switch the addresses all at once so as to avoid the data error of the unmodified path, but it is not necessary to prepare the input path-write address comparison table.

In FIG. 7A, the same parts as those in FIG. 7B are designated by the same reference numerals.

Read addresses 6030a and 6031
a, 6130a, and 6131a are similar to the method of generating the read address of the conventional time division multiplexing memory switch circuit, the read address value according to the connection setting is calculated in advance and written in the memory, and the word timing 0, It is given by the method of reading by 1, 2, and 3.

However, this read address value is written as the read address value of the input path number connected to the output path at the address corresponding to the output path number in the conventional examples of FIGS. In FIG. 1, only the input path signal connected to the output of the sub time division multiplexing memory switch circuit is written for each sub time division multiplexing memory switch circuit at the time of writing, and the write address of each input path signal is read out. Write it as an address value.

The reading of the memories 303 and 313 is shown in FIG.
As shown in the word timing-read address comparison table of (B), a memory in which input path numbers 5, 0, 1, and 4 connected to the output paths in the order of output paths 0 to 3 at word timings 0 to 3 are stored. And its address as (memory selection, address) in this order (1, 1), (0,
0), (0,1) and (1,0) are generated.

Here, X = 0 of (X, Y) is the memory 303.
, X = 1 indicates selection of the memory 313, and Y = 0, Y =
1 indicates the 0th address and the 1st address of the memory.

For reading the memories 323 and 333, the memory and its address in which the input path numbers 3, 0, 2 and 6 connected to the respective output paths in the order of the output paths 4 to 7 at the word timings 0 to 3 are stored ( (1, 1), (0, 0), (1, 0), (0,
1) occurs. Here, X = 0 of (X, Y) indicates selection of the memory 323, X = 1 indicates selection of the memory 333, and Y =
0 and Y = 1 respectively indicate address 0 and address 1 of the memory.

In this configuration, four memories of 8-bit / 2-word configuration are used, and the total number of memory bits is 64, which is half that of the configuration of FIG. 12, which is the same as the configuration of FIG.

In FIGS. 2 and 3, the number in {} indicates a signal in which an address is set but is not written or not read. In FIG. 4, () is an input path of a signal to be read / written. A number is shown, and {} indicates an input path number of a signal which is selected by the selection circuit but is not written.

FIGS. 6A and 6B show an example of the configuration of the parallel time division multiplexing memory switch circuit according to the present invention when the number of input / output paths is generally n and the number of parallel paths is m.

With respect to the number of input / output paths n and the number of parallel connections m, n is divided into m groups of n / m in the order of input paths.

For each m group, n / m parallel / n-bit serial n-bit parallel / n / m word serial m-times parallel / m-times low-speed parallel signals are converted.

For each of the m sub time division multiplexing memory switch circuits, m memories of n-bit parallel × n / m ² word structure are provided.

A maximum of n / m connected to m output memories of the sub time-division multiplex memory switch circuit is connected to the m memory of each of the m sub time-division multiplex memory switch circuits.
M groups of n bits in parallel
It is selected from the n / m word serial signal at every word timing of 1 to n / m, and all are written so as not to overlap the addresses 1 to n / m ^{2 of the} m memories.

For each of the m sub time-division multiplexing memory switch circuits, from the m memories, the input paths n / m connected to the output paths n / m of the sub time-division multiplexing memory switch circuits are output. A low speed parallel output signal of n-bit parallel / n / m word series is selected and read from the address corresponding to the written corresponding memory at each word timing of 1 to n / m corresponding to the output path order.

For each of the m sub time division multiplex memory switch circuits, n bits in parallel / n from the memory obtained in
/ M word serial low-speed parallel output signals are converted into m parallel n-bit serial output path signals.

In FIG. 6 (A), the parallel conversion circuit is configured such that n / m is parallel, n-bit serial signal is n, parallel is n.
/ M word serial to a low-speed parallel signal.
The switch consists of m parallel conversion circuits and m sets of n parallel
Select n / m signals for the output n / m path from the n / m word serial low-speed parallel signals and arrange them into n parallel / n / m word serial low-speed parallel signals that are word-serialized in the order of the output paths. It is to convert.

The serial conversion circuit converts a low-speed parallel signal of n parallel / n / m word serial into an output serial signal of n / m parallel / n-bit serial. The numbers in parentheses indicate the number of parallel signals.

In FIG. 6B, the selection circuit is an m: 1 signal selection circuit having an n-parallel configuration, and an output of this circuit is output from m groups of n parallel / n / m word serial signals by a selection signal of WA. The maximum n / m n parallel signals to be connected to each word are selected in a maximum of m for each word, and a maximum of n / m ² per memory are selected and distributed to the n memories.

The memory is an n-bit * n / m ² word memory. Since the WA generates a selection signal for the selection circuit, a write address that allocates n / m ² outputs from the selection circuit at each word timing so as not to overlap one of addresses 1 to n / m of each memory. To occur.

RA generates a read address for selecting the memory number in which the input path signal set by WA is written and its write address for every n / m from the word timing 1 corresponding to the output path number.

In the circuit configuration of FIG. 1, as in the conventional parallel time division multiplexing memory switch circuit shown in FIG. 12, the operation speed of the memory switch section is the conventional time division multiplexing memory switch shown in FIG. It is half of the circuit. The total memory bit number is half the total memory bit number of the conventional parallel time division multiplexing memory switch circuit shown in FIG. 12, and the total memory bit number of the conventional non-parallel time division multiplexing memory switch circuit shown in FIG. There are 64 bits equal to the number. That is, in the present invention, the operating speed can be halved without increasing the number of memory bits.

Generally, when m parallel circuits are used, the conventional parallel time division multiplexing memory switch circuit according to FIG. 12 has m times the number of memory bits, but in the configuration of FIG. The number of memory bits can be the same as the number of memory bits of the time division multiplexing memory switch circuit. The operation speed of each parallelized memory switch unit is a fraction.

The input signal selection circuit and the write address generation circuit newly required in FIGS. 1 and 6A and 6B are, for example, for the number of input / output paths n = 1 and the number of parallelizations m = 2. As shown in FIG. 8, the circuit scale and the number of memories are sufficiently small compared to the increase in the total number of memory bits shown in FIG.

Although the path connection between input and output is shown as an example, it is obvious that the configuration of the present invention can be generally applied to arbitrary connection setting between input and output.

[0073]

As described above, according to the present invention, since the number of memory bits can be reduced, there is an effect that the scale of hardware can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the blocks of FIG.

FIG. 3 is a time chart showing the operation of the blocks of FIG.

FIG. 4 is a diagram for explaining the operation of the blocks in FIG.

FIG. 5 is a diagram showing an example of connection between input / output paths.

FIG. 6 is a diagram showing another configuration of the exemplary embodiment of the present invention.

FIG. 7 is a diagram showing an example of a write / read address generation circuit.

FIG. 8 is a diagram showing comparison of memory bit numbers.

FIG. 9 is a diagram showing an example of a conventional time division multiplexing memory switch circuit.

FIG. 10 is an operation time chart of the block of FIG.

FIG. 11 is a diagram for explaining the operation of the blocks in FIG.

FIG. 12 is a diagram showing another example of a conventional time division multiplexing memory switch.

FIG. 13 is a time chart showing the operation of FIG.

FIG. 14 is a diagram for explaining the operation of FIG.

[Explanation of symbols]

 201 8-bit / 8-word serial / parallel conversion circuit 202,212 8-bit / 4-word serial / parallel conversion circuit 301 8-bit * 8 word configuration memory 302-332 8-bit * 4-word configuration memory 303-333 8-bit * 2 word Configuration memory 403 to 433 2: 1 signal selection circuit 501 to 533 Write address generation circuit 601 to 603 Read address generation circuit 90 Word timing generation circuit 91 Write / read address memory 92 Write / read address setting / writing circuit 930 to 933 Write Address counter

Claims (1)

[Claims] 1. An n parallel / bit serial signal from n input paths is divided into groups (m is an integer of 2 or more) for each n / m paths in the order of the paths, and each n groups are selected from the n / m paths. N / m parallel
A serial-parallel conversion circuit for converting an n-bit serial signal unit into an m-times parallel / m-times slower n-parallel / n / m-word serial signal,
A maximum of n / m n parallel input signals connected to the n / m output paths of the m-th group from the m n-parallel / n / m-bit serial signal outputs of the m-group serial-parallel conversion circuit, A maximum of m per 1 word timing, a maximum of n / m between 1 to n / m word timings, a maximum of n / m ² per circuit, and n n parallel m: 1 selection circuits, The n parallel / n / m ^2- bit serial output signal of the selection circuit is sent from address 1 to n /
m Write sequentially so that it does not overlap with any of the ² addresses m
N-bit parallel memory of n / m ² words, and the maximum n per memory from the memory in which the signal of the corresponding input path is written in the order of n / m output paths from the m memories.
/ M ² words each, total n / m words n parallel / n / m
A read address generation circuit for selectively reading out a word serial signal, and a parallel-serial conversion circuit for converting an n parallel / n / m word serial parallel low-speed signal output from the m memories to an n / m parallel / n-bit serial signal A parallel time-division multiplexing memory switch circuit having: