JPH0759055B2 - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- JPH0759055B2 JPH0759055B2 JP61252375A JP25237586A JPH0759055B2 JP H0759055 B2 JPH0759055 B2 JP H0759055B2 JP 61252375 A JP61252375 A JP 61252375A JP 25237586 A JP25237586 A JP 25237586A JP H0759055 B2 JPH0759055 B2 JP H0759055B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- signal charge
- solid
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は例えばビデオカメラ、電子スチルカメラに使用
して好適な電子シャッタ機構を有する固体撮像装置に関
する。The present invention relates to a solid-state image pickup device having an electronic shutter mechanism suitable for use in, for example, a video camera or an electronic still camera.
本発明は例えばビデオカメラ、電子スチルカメラに使用
して好適な電子シャッタ機構を有する固体撮像装置であ
って、第１の導電型の半導体基板の表面側に形成された
第２の導電型の領域と、この第２の導電型の領域の表面
側に形成された信号電荷蓄積領域とを有し、第１の導電
型の半導体基板に所定電圧を印加して信号電荷蓄積領域
に蓄積された信号電荷を第１の導電型の半導体基板に掃
き出させることにより露出時間の制御を行う様になされ
た固体撮像装置において、第１の導電型の半導体基板に
所定電圧を印加する期間を水平ブランキング期間内と
し、信号電荷蓄積領域に蓄積される信号を上記水平ブラ
ンキング期間内に上記第１の導電型の半導体基板に掃き
出させる様にしたことにより、電気的に露出時間の制御
を行い得る様にし、またこの場合においても、コントラ
ストの一様な再生画像を得ることができる様にしたもの
である。The present invention is a solid-state imaging device having an electronic shutter mechanism suitable for use in, for example, a video camera or an electronic still camera, and a second conductivity type region formed on the front surface side of a first conductivity type semiconductor substrate. And a signal charge accumulation region formed on the surface side of the second conductivity type region, and a signal accumulated in the signal charge accumulation region by applying a predetermined voltage to the first conductivity type semiconductor substrate. In a solid-state imaging device configured to control an exposure time by sweeping charges to a semiconductor substrate of a first conductivity type, horizontal blanking is performed during a period of applying a predetermined voltage to the semiconductor substrate of a first conductivity type. Within the period, the signal accumulated in the signal charge accumulating region is swept out to the semiconductor substrate of the first conductivity type within the horizontal blanking period, so that the exposure time can be electrically controlled. Like In the case of octopus also, in which the manner it is possible to obtain a uniform reproduced image contrast.
従来、メカニカルシャッタを用いず、電気的に露出時間
の制御を行い得る様になされた固体撮像装置として、Ｎ
型シリコン基板上にＰ型領域を形成すると共に、このＰ
型領域上に受光部、垂直レジスタ部、水平レジスタ部及
び出力部を設け、Ｎ型シリコン基板に印加する直流電圧
を可変する様にしたものが提案されている。即ち、この
固体撮像装置は、第４図Ａに示す読み出しパルスP1に引
き続き僅か遅れて第４図Ｂに示す様に１フィールド期間
の任意の期間t1の間、Ｎ型シリコン基板部分に直流電圧
30〔Ｖ〕を印加し、この期間t1の間、受光部の信号電荷
蓄積領域に生ずる信号電荷をすべてＮ型シリコン基板部
分に掃き出させ、１フィールド期間の残りの期間t2の
間、Ｎ型シリコン基板部分に直流電圧10〔Ｖ〕を印加
し、この期間t2の間に受光部の信号電荷蓄積領域に信号
電荷を蓄積し、この信号電荷を読み出しパルスP1に続く
読み出しパルスP2によって読み出そうとするものであ
り、斯る固体撮像装置によれば、Ｎ型シリコン基板部分
に30〔Ｖ〕の直流電圧を印加する期間t1を可変制御する
ことによって露出時間t2の制御を行うことが可能とな
る。Conventionally, as a solid-state imaging device that can electrically control the exposure time without using a mechanical shutter,
A P-type region is formed on the silicon substrate and the P-type region is formed.
It is proposed that a light receiving portion, a vertical register portion, a horizontal register portion, and an output portion are provided on the mold region so that the DC voltage applied to the N-type silicon substrate can be varied. That is, this solid-state image pickup device has a direct current applied to the N-type silicon substrate portion during an arbitrary period t 1 of one field period as shown in FIG. 4B after a slight delay from the read pulse P 1 shown in FIG. 4A. Voltage
30 [V] is applied, and during this period t 1 , all the signal charges generated in the signal charge accumulation region of the light receiving portion are swept out to the N-type silicon substrate portion, and during the remaining period t 2 of one field period, A direct current voltage of 10 [V] is applied to the N-type silicon substrate portion, signal charges are accumulated in the signal charge accumulation region of the light receiving portion during this period t 2 , and this signal charge is read out from the read pulse P 1 followed by the read pulse P 1. is intended to be read by 2, according to斯Ru solid-state imaging device, the exposure time t 2 by a period t 1 for applying a DC voltage of 30 [V] N-type silicon substrate portion is variably controlled It becomes possible to control.
しかしながら、斯る固体撮像装置においては、第５図に
示す様に、再生画面（１）上にコントラストの相違する
部分、即ち明るい部分（２）と暗い部分（３）とが生ず
るという不都合があった。ここに、この明るい部分
（２）はＮ型シリコン基板部分に30〔Ｖ〕を印加してい
る期間t1に出力部から読み出された信号部分に対応し、
暗い部分（３）はＮ型シリコン基板部分に10〔Ｖ〕を印
加している期間t2に出力部から読み出された信号部分に
対応しており、斯る再生画像におけるコントラストの相
違は、１フィールド期間中にＮ型シリコン基板の電圧が
高い期間t1と低い期間t2とがあるため、出力部のブッフ
アアンプ等が動作点を変動させる等の変調を受けるため
に生ずるものと考えられる。However, in such a solid-state imaging device, as shown in FIG. 5, there is a disadvantage that a portion having a different contrast, that is, a bright portion (2) and a dark portion (3) are generated on the reproduction screen (1). It was Here, this bright portion (2) corresponds to the signal portion read from the output portion during the period t 1 in which 30 [V] is being applied to the N-type silicon substrate portion,
The dark portion (3) corresponds to the signal portion read from the output portion during the period t 2 in which 10 [V] is applied to the N-type silicon substrate portion, and the difference in contrast in the reproduced image is Since there is a period t 1 in which the voltage of the N-type silicon substrate is high and a period t 2 in which the voltage of the N-type silicon substrate is low in one field period, it is considered that this occurs because the buffer amplifier or the like in the output section undergoes modulation such as changing the operating point.
本発明は、斯る点に鑑み、再生画像にコントラストの相
違を生じさせない様にした電子シャッタ機構を有する固
体撮像装置を提供することを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device having an electronic shutter mechanism that does not cause a difference in contrast between reproduced images.
本発明固体撮像装置は、例えば第１図〜第３図に示す様
に、第１の導電型の半導体基板（４）の表面側に形成さ
れた第２の導電型の領域（５）と、この第２の導電型の
領域（５）の表面側に形成された信号電荷蓄積領域
（６）とを有し、第１の導電型の半導体基板（４）に所
定電圧VHを印加して信号電荷蓄積領域（６）に蓄積され
た信号電荷を第１の導電型の半導体基板（４）に掃き出
させることによって露出時間t2の制御を行う様になされ
た固体撮像装置において、第１の導電型の半導体基板
（４）に所定電圧VHを印加する期間を水平ブランキング
期間内とし、信号電荷蓄積領域（６）に蓄積される信号
電荷を水平ブランキング期間内に第１の半導体基板
（４）に掃き出させる様にしたものである。The solid-state imaging device of the present invention includes, for example, as shown in FIGS. 1 to 3, a second conductivity type region (5) formed on the front surface side of a first conductivity type semiconductor substrate (4), A signal charge storage region (6) formed on the surface side of the second conductivity type region (5), and applying a predetermined voltage V H to the first conductivity type semiconductor substrate (4). In the solid-state imaging device configured to control the exposure time t 2 by sweeping out the signal charge accumulated in the signal charge accumulation region (6) to the semiconductor substrate (4) of the first conductivity type, The period during which the predetermined voltage V H is applied to the conductivity type semiconductor substrate (4) is within the horizontal blanking period, and the signal charges accumulated in the signal charge accumulation region (6) are within the horizontal blanking period. The substrate (4) is swept out.
斯る本発明に依れば、第１の導電型の半導体基板（４）
に所定電圧VHを印加する期間を水平ブランキング期間内
とし、信号電荷蓄積領域（６）に蓄積される信号電荷を
水平ブランキング期間内に第１の導電型の半導体基板
（４）に掃き出させる様になされているので、第１の導
電型の基板（４）に所定電圧VHを印加する水平ブランキ
ング期間の回数を変えることで露出時間の制御が行なえ
ると共に、出力部のバッフアアンプ等が第１の導電型の
基板（４）の電圧変化によって変調を受けたとしても、
再生画像は全くその影響を受けず、一様なコントラスト
となる。According to the present invention, the semiconductor substrate (4) of the first conductivity type is provided.
The period of applying the predetermined voltage V H to the horizontal blanking period is set to sweep the signal charges stored in the signal charge storage region (6) to the first conductivity type semiconductor substrate (4) within the horizontal blanking period. The exposure time can be controlled by changing the number of horizontal blanking periods in which the predetermined voltage V H is applied to the first conductivity type substrate (4), and the buffer amplifier of the output section can be controlled. Etc. are modulated by the voltage change of the first conductivity type substrate (4),
The reproduced image is not affected by it at all and has a uniform contrast.
以下、第１図〜第３図を参照して本発明固体撮像装置の
一実施例につき説明しよう。An embodiment of the solid-state image pickup device of the present invention will be described below with reference to FIGS.
この第１図において、（４）はＮ型シリコン基板を示
し、本例においては、このＮ型シリコン基板（４）上に
受光部（７）、垂直レジスタ部（８）、水平レジスタ部
（図示せず）及び出力部（図示せず）を設け、所インタ
ーライン転送方式のCCD形撮像装置として構成する、 この場合、Ｎ型シリコン基板（４）の表面側にＰ型領域
（５）を形成すると共に、更にこのＰ型領域（５）の表
面側にN-型領域（９）を形成する。そして、受光部
（７）は、このN-型領域（９）表面領域に浅いP++型領
域（10）を形成すると共にこのP++型領域（10）の下方
に信号電荷蓄積領域を構成するN+型領域（６）を形成す
ることによって構成する。また、この場合、P++型領域
（10）及びN+型領域（６）に隣接してチャンネルストッ
パ部を構成するP+型領域（11）を形成すると共に、P++
型領域（10）上にSiO2による絶縁層（12）を形成する。In FIG. 1, (4) indicates an N-type silicon substrate, and in this example, a light receiving part (7), a vertical register part (8), and a horizontal register part (FIG. (Not shown) and an output section (not shown) are provided to form an interline transfer type CCD image pickup device. In this case, a P type region (5) is formed on the surface side of the N type silicon substrate (4). At the same time, an N − type region (9) is formed on the surface side of the P type region (5). Then, the light receiving part (7) forms a shallow P ++ type region (10) in the surface region of the N − type region (9) and a signal charge accumulation region below the P ++ type region (10). It is formed by forming the N + type region (6) to be formed. In this case, to form a P ++ type region (10) P + -type regions forming the channel stopper portion adjacent to and N + -type region (6) (11), P ++
An insulating layer (12) made of SiO 2 is formed on the mold region (10).
また垂直レジスタ部（８）は、チャンネル領域を構成す
るＰ型領域（13）を介して信号電荷転送領域を構成する
N+型領域（14）を形成すると共に、このN+型領域（14）
上にSiO2によりなる絶縁層（12）及びSi3N4よりなる絶
縁層（15）を介してポリシリコンよりなる転送電極（1
6）を形成することによって構成する。この場合、信号
電荷転送領域を構成するN+型領域（14）の下方にスミア
を防止するためのＰ型領域（17）を形成すると共に、転
送電極（16）の上方に絶縁層（12）を介して遮光用のア
ルミニウム層（18）を設ける。尚、この第１図には１個
の転送電極（16）のみを示しているが、本例において
は、従来周知の様に４相駆動方式によりこの垂直レジス
タ部（８）を駆動し得る様に転送電極を配置する。また
水平レジスタ部及び出力部については図示せずも、従来
周知の様に構成する。Further, the vertical register section (8) constitutes a signal charge transfer area via a P-type area (13) constituting a channel area.
To form the N + -type region (14), the N + -type region (14)
A transfer electrode (1) made of polysilicon is formed on the insulating layer (12) made of SiO 2 and an insulating layer (15) made of Si 3 N 4 on the upper side.
6) is formed. In this case, a P-type region (17) for preventing smear is formed below the N + -type region (14) forming the signal charge transfer region, and an insulating layer (12) is formed above the transfer electrode (16). A light-shielding aluminum layer (18) is provided through. Although only one transfer electrode (16) is shown in FIG. 1, in this example, the vertical register section (8) can be driven by a four-phase driving method as well known in the art. The transfer electrode is arranged at. Although not shown, the horizontal register section and the output section are configured as well known in the art.
また本例においては、直流電源（19）及び（20）の夫々
の負電圧端子とＰ型領域（５）とを共通接続して接地す
ると共に、直流電源（19）及び（20）の夫々の正電圧端
子をスイッチ回路（21）の一方及び他方の固定接点（21
A）及び（21B）に夫々接続し、このスイッチ回路（21）
の可動接点（21C）をＮ型シリコン基板（４）に接続す
る。この場合、直流電源（19）の出力電圧VLは第２図に
実線Ｘで示す様にＰ型領域（５）のポテンシャルが表面
のP++型領域（10）のポテンシャルよりも稍低くなり、
信号電荷蓄積領域（６）において信号電荷を蓄積できる
と共に有効なブルーミング抑制を行うことができる電
圧、例えば10Vとし、また直流電源（20）の出力電圧VH
は第２図に破線Ｙで示す様にＰ型領域（５）のポテンシ
ャルが信号電荷蓄積領域（６）のポテンシャルよりも低
くなり、信号電荷蓄積領域（６）に蓄積された信号電荷
をＮ型シリコン基板（４）に掃き出すことができる電
圧、例えば30Vとする。またスイッチ回路（21）は制御
信号入力端子（22）を介して供給される制御信号によっ
てスイッチング制御できる様にし、本例においては、第
３図Ａ及び第３図Ｂに示す様に前フィールド期間に信号
電荷蓄積領域（６）に蓄積された信号電荷を読み出しパ
ルスP1で垂直レジスタ部（８）に読み出した後、63.5μ
sec毎に設定される水平ブランキング期間を連続して任
意の個数選択し、この選択した水平ブランキング期間の
間にＮ型シリコン基板（４）に電圧VH、例えば30〔Ｖ〕
を印加し、信号電荷蓄積領域（６）に蓄積された信号電
荷をＮ型シリコン基板（４）に掃き出す様にする。換言
すれば、読み出しパルスP1による読み出しの後、露出を
開始する直前まで、水平ブランキング期間毎にＮ型シリ
コン基板（４）に電圧30Vを印加し、信号電荷蓄積領域
（６）に蓄積される信号電荷を掃き出し、露出時間t2に
おいては、Ｎ型シリコン基板（４）に印加する電圧を10
Vとして信号電荷を蓄積する様にする。尚、第２図Ｃは
水平クロック信号、第２図Ｄは水平ブランキング信号、
第２図Ｅは水平ブランキング期間におけるＮ型シリコン
基板（４）に印加する電圧の様子を示すものである。Further, in this example, the negative voltage terminals of the DC power supplies (19) and (20) are commonly connected to the P-type region (5) to be grounded, and the DC power supplies (19) and (20) are connected to each other. Connect the positive voltage terminal to one and the other fixed contacts (21) of the switch circuit (21).
This switch circuit (21) is connected to A) and (21B) respectively.
The movable contact (21C) is connected to the N-type silicon substrate (4). In this case, the output voltage V L of the DC power source (19) is lower in the potential of the P type region (5) than the potential of the surface P + + type region (10) as shown by the solid line X in FIG. ,
A voltage capable of accumulating signal charges in the signal charge accumulating region (6) and effectively suppressing blooming, for example, 10 V, and the output voltage V H of the DC power supply (20)
The potential of the P-type region (5) becomes lower than the potential of the signal charge storage region (6) as indicated by the broken line Y in FIG. 2, and the signal charge stored in the signal charge storage region (6) is N-type. The voltage that can be swept onto the silicon substrate (4), for example, 30V. Further, the switch circuit (21) is made to be able to perform switching control by a control signal supplied through the control signal input terminal (22). In this example, as shown in FIGS. After reading the signal charge accumulated in the signal charge accumulation region (6) into the vertical register section (8) with a read pulse P 1 ,
An arbitrary number of horizontal blanking periods set for each sec are continuously selected, and a voltage V H , for example, 30 [V], is applied to the N-type silicon substrate (4) during the selected horizontal blanking period.
Is applied to sweep out the signal charges accumulated in the signal charge accumulation region (6) to the N-type silicon substrate (4). In other words, after reading by the read pulse P 1 , until the exposure is started, the voltage 30V is applied to the N-type silicon substrate (4) every horizontal blanking period, and the voltage is accumulated in the signal charge accumulation region (6). Sweeping out the signal charge that is generated, and applying the voltage of 10 to the N-type silicon substrate (4) at the exposure time t 2 .
The signal charge is stored as V. 2C is a horizontal clock signal, FIG. 2D is a horizontal blanking signal,
FIG. 2E shows the state of the voltage applied to the N-type silicon substrate (4) during the horizontal blanking period.
この様に構成された本例の固体撮像装置においては、第
２図Ｂに示す様に信号電荷蓄積領域（６）に蓄積された
信号電荷を掃き出す水平ブランキング期間の回数を変化
させることで、露出時間t2を例えば1/60〜1/10000の間
で自由に可変させることができる。In the solid-state imaging device of this example configured as described above, by changing the number of horizontal blanking periods for sweeping out the signal charge accumulated in the signal charge accumulation region (6) as shown in FIG. 2B, The exposure time t 2 can be freely changed, for example, between 1/60 and 1/10000.
この様に本例の固体撮像装置においては、Ｎ型シリコン
基板（４）に印加する電圧を可変することによって露出
制御を行っているが、Ｎ型シリコン基板（４）に電圧
VH、例えば30Vを印加する期間を水平ブランキング期間
中に行う様になされているので、Ｎ型シリコン基板に印
加される電圧が可変されることによって出力部のバッフ
アアンプ等が変調を受けたとしても、再生画像には何等
影響を与えず、コントラストの一様な再生画像を得るこ
とができるという利益がある。As described above, in the solid-state imaging device of this example, the exposure control is performed by changing the voltage applied to the N-type silicon substrate (4).
Since the period of applying V H , for example, 30 V is performed during the horizontal blanking period, it is assumed that the buffer amplifier or the like in the output section is modulated by changing the voltage applied to the N-type silicon substrate. However, there is an advantage that a reproduced image having a uniform contrast can be obtained without affecting the reproduced image.
尚、上述実施例においては、露出を開始する直前まで、
水平ブランキング期間毎に信号電荷を掃き出す様にした
場合について述べたが、固体撮像素子の特性によって
は、露出を開始する直前の水平ブランキング期間中に１
回だけ掃き出す様にし、或いは露出を開始するまでの水
平プランキング期間のうちの数回のみを選択して掃き出
す様にすることもできる。即ち、この掃き出しの回数は
固体撮像素子の特性に合わせて適宜に設定することがで
きる。In the above embodiment, until just before the start of exposure,
The case where the signal charge is swept out every horizontal blanking period has been described. However, depending on the characteristics of the solid-state image sensor, the signal charge may be set to 1 during the horizontal blanking period immediately before the start of exposure.
It is also possible to sweep out only once or to select and sweep out only several times in the horizontal blanking period until the exposure is started. That is, the number of times of this sweeping can be appropriately set according to the characteristics of the solid-state image sensor.
また本発明は、上述実施例に限らず、本発明の要旨を逸
脱することなく、その他、種々の構成が取り得ることは
勿論である。Further, the present invention is not limited to the above-described embodiments, and needless to say, various other configurations can be adopted without departing from the gist of the present invention.
本発明に依れば、水平ブランキング期間内に所定電圧VH
が第１の導電型の半導体基板（４）に印加される様にな
されているので、電気的な露出時間制御を行うことによ
って、出力部のバッフアアンプ等が変調を受けたとして
も、再生画像には何等影響を与えず、コントラストの一
様な再生画像を得ることができるという利益がある。According to the present invention, within the horizontal blanking period, the predetermined voltage V H
Is applied to the semiconductor substrate (4) of the first conductivity type. Therefore, even if the buffer amplifier in the output section is modulated by controlling the electrical exposure time, the reproduced image is reproduced. Has an advantage that a reproduced image with uniform contrast can be obtained without any influence.
第１図は本発明固体撮像装置の一実施例を示す構成図、
第２図は第１図例における信号電荷蓄積領域を含む厚さ
方向におけるポテンシャルを示す線図、第３図は第１図
例の説明に供する線図、第４図及び第５図は夫々従来の
固体撮像装置の説明に供する線図である。 （４）はＮ型シリコン基板、（５）はＰ型領域、（６）
は信号電荷蓄積領域、（７）は受光部、（８）は垂直レ
ジスタ部、（14）は信号電荷転送領域、（19）及び（2
0）は夫々直流電源である。FIG. 1 is a block diagram showing an embodiment of the solid-state imaging device of the present invention,
FIG. 2 is a diagram showing the potential in the thickness direction including the signal charge storage region in the example of FIG. 1, FIG. 3 is a diagram used for explaining the example of FIG. 1, and FIGS. 3 is a diagram for explaining the solid-state imaging device of FIG. (4) is an N-type silicon substrate, (5) is a P-type region, (6)
Is a signal charge storage region, (7) is a light receiving part, (8) is a vertical register part, (14) is a signal charge transfer region, (19) and (2).
0) are DC power sources, respectively.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 智行 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 (72)発明者 浜崎 正治 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 (56)参考文献 特開 昭58−125961（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoyuki Suzuki 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation (72) Shoji Hamasaki 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) References JP-A-58-125961 (JP, A)
Claims (1)
された第２の導電型の領域と、該第２の導電型の領域の
表面側に形成された信号電荷蓄積領域とを有し、上記第
１の導電型の半導体基板に所定電圧を印加して上記信号
電荷蓄積領域に蓄積された信号電荷を上記第１の導電型
の半導体基板に掃き出させることにより露出時間の制御
を行う様になされた固体撮像装置において、 上記第１の導電型の半導体基板に上記所定電圧を印加す
る期間を水平ブランキング期間内とし、上記信号電荷蓄
積領域に蓄積される上記信号電荷を上記水平ブランキン
グ期間内に上記第１の導電型の半導体基板に掃き出させ
る様にしたことを特徴とする固体撮像装置。1. A second conductivity type region formed on the surface side of a first conductivity type semiconductor substrate, and a signal charge storage region formed on the surface side of the second conductivity type region. The exposure time is controlled by applying a predetermined voltage to the first conductivity type semiconductor substrate and sweeping out the signal charges accumulated in the signal charge accumulation region to the first conductivity type semiconductor substrate. In the solid-state imaging device configured to perform the above, the period for applying the predetermined voltage to the first conductive type semiconductor substrate is within a horizontal blanking period, and the signal charges accumulated in the signal charge accumulation region are A solid-state imaging device characterized in that the first conductive type semiconductor substrate is swept out within a horizontal blanking period.
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61252375A JPH0759055B2 (en) | 1986-10-23 | 1986-10-23 | Solid-state imaging device |
| US07/110,844 US4875100A (en) | 1986-10-23 | 1987-10-21 | Electronic shutter for a CCD image sensor |
| EP87309365A EP0265271B1 (en) | 1986-10-23 | 1987-10-22 | Electronic shutter for an electronic camera and method of utilizing a CCD image sensor as electronic shutter for such a camera |
| DE3752305T DE3752305T2 (en) | 1986-10-23 | 1987-10-22 | Electronic shutter for electronic camera |
| SG1996008391A SG74557A1 (en) | 1986-10-23 | 1987-10-22 | Solid state imager devices |
| DE3751775T DE3751775T2 (en) | 1986-10-23 | 1987-10-22 | Electronic shutter for an electronic camera and method for using a CCD image sensor as an electronic shutter for such a camera |
| EP95202218A EP0683603B1 (en) | 1986-10-23 | 1987-10-22 | Electronic shutter for electronic camera |
| HK98107004A HK1007833A1 (en) | 1986-10-23 | 1998-06-26 | Electronic shutter for an electronic camera and method of utilizing a ccd image sensor as electronic shutter for such a camera |
| HK98114853A HK1013568A1 (en) | 1986-10-23 | 1998-12-22 | Electronic shutter for electronic camera |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61252375A JPH0759055B2 (en) | 1986-10-23 | 1986-10-23 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63105579A JPS63105579A (en) | 1988-05-10 |
| JPH0759055B2 true JPH0759055B2 (en) | 1995-06-21 |
Family
ID=17236432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61252375A Expired - Lifetime JPH0759055B2 (en) | 1986-10-23 | 1986-10-23 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0759055B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2920924B2 (en) * | 1989-01-12 | 1999-07-19 | ソニー株式会社 | CCD camera |
| JPH04237271A (en) * | 1991-01-21 | 1992-08-25 | Fuji Photo Film Co Ltd | Image pickup device |
| JPH04360478A (en) * | 1991-06-07 | 1992-12-14 | Matsushita Electric Ind Co Ltd | Solid-state image pickup element |
| JP3015246B2 (en) * | 1993-10-08 | 2000-03-06 | シャープ株式会社 | Solid-state imaging device |
| JPH0965217A (en) * | 1995-08-22 | 1997-03-07 | Nec Corp | Solid-state image pickup device and its drive method |
| JP3598648B2 (en) * | 1996-04-02 | 2004-12-08 | ソニー株式会社 | Charge transfer device and method of driving charge transfer device |
| JP2007006261A (en) * | 2005-06-24 | 2007-01-11 | Fujifilm Holdings Corp | Driving method for solid-state imaging element and solid-state imaging apparatus |
-
1986
- 1986-10-23 JP JP61252375A patent/JPH0759055B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63105579A (en) | 1988-05-10 |
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