JP2970119B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a video camera,
The present invention relates to a solid-state imaging device having an electronic shutter function suitable for use in an electronic still camera and a driving method thereof .

[0002]

2. Description of the Related Art Conventionally, without using a mechanical shutter,
As a solid-state imaging device having a so-called electronic shutter function for electrically controlling the exposure time, for example, a P-type region is formed on an N-type silicon substrate, and a light-receiving unit, a vertical register unit, and a horizontal There has been proposed a device in which a register unit and an output unit are provided and a DC voltage applied to an N-type silicon substrate is made variable.

That is, in this solid-state imaging device, for example, a DC voltage of 30 V is applied to the N-type silicon substrate for an arbitrary period t ₁ of one field period with a slight delay following the read pulse P ₁ shown in FIG. During this period t ₁ , all the signal charges generated in the signal charge storage region of the light receiving section are swept out to the N-type silicon substrate side, and, for the remaining period t ₂ of one field period, the N-type silicon substrate a DC voltage of 10V was applied, a signal charge accumulated in the signal charge accumulation region of the light receiving section during the period t _2, a read pulse P ₁ the signal charges
The read pulse P ₂ followed, which reads, according to the solid-state imaging device, by variably controlling the period t ₁ for applying a DC voltage 30V in N-type silicon substrate, and controls the exposure time t ₂ It becomes possible.

However, in the solid-state imaging device, as shown in FIG. 6, there is an inconvenience that a portion having a different contrast, that is, a bright portion 31a and a dark portion 31b are formed on the reproduction screen 31.

[0005] Here, the bright portion 31a corresponds to a signal portion which is read from the output unit during the period t ₁ that by applying a DC voltage 30V in N-type silicon substrate, a dark portion 3
1b corresponds to signal portions read out from the output unit during the period t ₂ which applies a DC voltage of 10V to the N-type silicon substrate, the difference in contrast in the reproduction image, 1
Since during field period the voltage of the N-type silicon substrate is a high period t ₁ and a low period t _2, the buffer amplifier and the output section is considered to occur in order to receive a modulation such varying the operating point.

On the other hand, in order to solve the above problem, the present applicant sets a period in which a predetermined potential (a so-called shutter pulse) is applied to an N-type silicon substrate within a horizontal blanking period,
A solid-state imaging device has been proposed in which signal charges stored in a signal charge storage region are swept out to an N-type silicon substrate within a horizontal blanking period.

According to this solid-state imaging device, the exposure time, that is, the shutter speed can be controlled by changing the position of the final shutter pulse applied to the N-type silicon substrate with respect to the position of the read pulse. Further, even if the buffer amplifier or the like of the output section is modulated by the voltage change of the N-type silicon substrate, the reproduced image is not affected at all.
Uniform contrast can be obtained.

[0008]

However, when a shutter pulse is applied during the horizontal blanking period as described above, only a discontinuous variable shutter can be realized as a result, and as the shutter speed increases, the shutter speed increases. There is an inconvenience that the change rate of the shutter speed increases rapidly.

This has a drawback that when the electronic shutter function is used as a substitute for the conventional auto iris (mechanical light amount adjustment), it is not possible to select an optimum exposure amount, particularly at the time of a high-speed shutter. That is, in the case of controlling the electronic iris, the program AE, and the like, when the shutter speed is high, it is impossible in principle to finely adjust the light receiving amount of the CCD image sensor by controlling the shutter speed.

Therefore, recently, a solid-state imaging device has been proposed in which a shutter pulse is applied at an arbitrary timing during a vertical blanking period, and the electric charge is swept away by an electronic shutter so that the amount of received light can be freely changed. Have been.

FIG. 7 shows timings of various signals of the solid-state imaging device. In this figure, HD indicates a horizontal synchronizing signal, and B1, B2 and B3 indicate horizontal blanking periods. V ₁ , V ₂ , V ₃ and V ₄ indicate vertical transfer pulses, and P indicates a read pulse in the vertical transfer pulses. Ps indicates a shutter pulse applied to the N-type silicon substrate to operate the electronic shutter function.

The vertical transfer pulses V _{1 to} V ₄ constitute four-phase pulses having different phases, and the signal charges transferred to the vertical register are applied one row at a time by the application of the vertical transfer pulses V _{1 to} V _4. Transfer to the horizontal register side. This vertical transfer is performed during each horizontal blanking period. In this case, since the vertical blanking period is in progress, this vertical transfer is in the idle feeding state.

In this solid-state imaging device, a horizontal blanking period B during a vertical blanking period (VBLK) is used.
The shutter pulse Ps rises at an arbitrary timing between 2 and the horizontal blanking period B3. With the rise of the shutter pulse Ps, the signal charges accumulated in the signal charge accumulation region of the light receiving section are swept away to the N-type silicon substrate side. Therefore, the shutter pulse Ps
From the falling edge to the rising edge of the next readout pulse P is the exposure time L, and the signal charges accumulated during this exposure time L are read out to the vertical register by application of the readout pulse P.

Therefore, the shutter pulse Ps can rise at an arbitrary timing without being influenced by the horizontal synchronizing signal HD, so that the light receiving amount of the CCD image sensor can be finely adjusted by controlling the shutter speed. it can.

However, in this solid-state imaging device, the shutter pulse Ps is independently raised at an arbitrary timing during the vertical blanking period (VBLK).
There is a possibility that the surface potential of the N-type silicon substrate is not stabilized, and the operation characteristics become unstable.

[0016] That is, the output after the shutter pulse Ps, the substrate potential Vsub is fixed to a predetermined potential, a state where the vertical transfer pulses V ₁ ~V ₄ to the vertical transfer electrode is applied.
The depth of the potential well of each light receiving portion of the image region in which a large number of light receiving portions are arranged in a matrix is usually defined by a channel stopper region (ground potential is applied). In the central portion of the region, the potential of the channel stopper region varies depending on the potential applied to the vertical transfer gate electrode (hereinafter, simply referred to as a transfer electrode). The depth, that is, the potential of the substrate surface is also determined by the potential applied to the transfer electrode.

In such a state, when the vertical transfer pulses V _{1 to} V ₄ are applied during the exposure period L after the output of the shutter pulse Ps, the potential on the substrate surface fluctuates (stabilizes) and, for example, There is a problem that the amount of signal charges accumulated in the light receiving unit varies even when the amount of light is incident.

SUMMARY OF THE INVENTION The present invention has been made in view of such problems, and an object of the present invention is to make it possible to finely adjust a light receiving amount by controlling a shutter speed and to stabilize operation characteristics. An object of the present invention is to provide a solid-state imaging device capable of performing optimal control in additional functions such as an electronic iris and a program AE, and a driving method thereof .

[0019]

SUMMARY OF THE INVENTION The present invention relates to a first conductive type.
Second conductivity type region formed on the surface side of semiconductor substrate 1
(Well region 5) and the surface side of the second conductivity type region 5
And a signal charge storage region 8 formed therein.
Apply a predetermined potential (shutter pulse Ps) to the plate 1
The signal charge Q stored in the signal charge storage region 8 is
The exposure time L is controlled by sweeping out to the conductive substrate 1.
In a solid-state imaging device designed to control
Within the ranking period (VBLK), the shutter pulse
Ps (and Psτ) is converted to a vertical transfer pulse V₁~ V_Four(as well as
Vτ₁~ Vτ_Four) Is applied to the semiconductor substrate 1 in synchronization with
To achieve.The present invention also provides a semiconductor substrate 1 having a predetermined potential
By applying the jitter pulse Ps), the semiconductor substrate
The signal charge stored in the signal charge storage region 8 formed on the surface side of the plate 1
The signal charge Q is swept out to the semiconductor substrate 1 and
A predetermined potential (shutter pulse Ps) is applied to the semiconductor substrate 1
By changing the timing of applying
In the driving method of the solid-state imaging device for controlling the interval L,
During the direct blanking period (VBLK), the shutter
The vertical transfer pulse V ₁ ~ V
_Four (And Vτ ₁ ~ Vτ _Four On the semiconductor substrate 1 in synchronization with
Add.

[0020]

SUMMARY OF] According to the invention described above is applied to the semiconductor substrate 1 in synchronization with the shutter pulse Ps (and Pstau) vertical transfer pulses V ₁ ~V ₄ for performing an electronic shutter function (and Vτ ₁ ~Vτ ₄₎ Therefore, normally, by applying the vertical transfer pulses V _{1 to} V ₄ (and Vτ _{1 to} Vτ ₄ ),
In the central part of the image area, the potential of the substrate surface fluctuates (stabilizes).
Is applied in synchronism with the vertical transfer pulses V _{1 to} V ₄ (and Vτ _{1 to} Vτ ₄ ), so that the potential on the substrate surface becomes
It is stabilized without depending on the vertical transfer pulses V _{1 to} V ₄ (and Vτ _{1 to} Vτ ₄ ). Therefore, in the exposure time L after the output of the shutter pulse Ps (and Psτ),
It is possible to prevent a change in the signal charge amount caused by a change in the potential of the substrate surface, and to stabilize the operation characteristics.

Also, a vertical blanking period (VBLK)
Since the shutter pulse Ps (and Psτ) is applied during this operation, the shutter pulse Ps (and Psτ) can be started at an arbitrary timing without being affected by the horizontal synchronization signal HD. Light reception amount adjustment can be performed.

[0022] Thus, the solid-state imaging device 及 according to the present invention
According to this method , the light receiving amount can be finely adjusted by controlling the shutter speed, the operating characteristics can be stabilized, and optimal control can be performed in additional functions such as an electronic iris and a program AE. Can be.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram illustrating a CCD solid-state imaging device according to the present embodiment.

In this CCD solid-state imaging device, a light receiving section 2, a vertical register section 3, a channel stopper section 4, a horizontal register section (not shown) and an output section (not shown) are provided on an N-type silicon substrate 1. Then, it is configured as a so-called interline transfer type CCD solid-state imaging device.

That is, a P-type well region 5 is formed on the surface of the N-type silicon substrate 1, and an N ^- type well region 6 is further formed on the surface of the well region 5. The light receiving section 2 has a shallow P
^{A ++-} type positive charge storage region 7 is formed, and an N ⁺ -type signal charge storage region 8 is formed below the positive charge storage region 7. In addition, the channel stopper 4
Is composed of a P ⁺ type channel stopper region 9 formed adjacent to the positive charge storage region 7 and the signal charge storage region 8. Reference numeral 10 denotes an insulating layer made of SiO ₂ .

The vertical register section 3 includes a signal charge transfer area,
That is, N which constitutes the vertical register 11 ⁺Form mold area
At the same time, SiO_TwoConsisting of insulation
Layer 10 and Si_ThreeN_FourThrough the insulating layer 12
By forming the transfer electrode 13 made of crystalline silicon,
It is configured. In this case, below the vertical register 11
Then, a P-type region 14 for preventing smear is formed.

A read gate section 15 for reading out the signal charges of the light receiving section 2 to the vertical register section 3 is provided between the light receiving section 2 and the vertical register section 3. This read gate unit 15 is provided with a P-type region 1 forming a channel region.
6 is formed by forming a gate electrode 17 via insulating layers 10 and 12. In this example, the gate electrode 17 is formed of polycrystalline silicon in common with the transfer electrode 13.

An Al film 18 for shielding light is formed on the read gate section 14, the vertical register section 3, and the channel stopper section 4 excluding the light receiving section 2 via an insulating layer 10. still,
Although only one transfer electrode is shown in FIG. 1, in this example, the transfer electrodes 13 are arranged so as to drive the vertical register unit 3 by a four-phase driving method as is well known. Also,
The horizontal register unit and the output unit are not shown,
The configuration is conventionally known.

In this embodiment, for example, a pulse generating circuit 21 with a built-in ROM for supplying a reference clock CLK and outputting a desired pulse signal is incorporated, and one output terminal φp and the N-type silicon substrate 1 are connected. One path is connected via a pulse delay circuit 22, a switching circuit 23 and a drive circuit 24, and the other path is connected via a switching circuit 23 and a drive circuit 24.

Further, a series of four output terminals φ1 to φ4 and 4
The transfer electrode 13 arranged corresponding to the phase driving method is connected via a pulse delay circuit 22, a switching circuit 23, and a drive circuit 25 on one path, and is connected to the switching circuit 23 and the drive circuit 25 on the other path. Drive circuit 25
Connect through.

That is, a shutter pulse Ps shown in FIG. 3 is output from the output terminal φp of the pulse generation circuit 21, and this shutter pulse Ps is supplied to the N
The substrate potential Vsub becomes high (V _H ) by being supplied to the silicon substrate 1.

Here, when the substrate potential Vsub is at a low level (V
_L ) is a P-type well region 5 as shown by a solid line in FIG.
Is lower than the potential of the signal charge storage region 8, so that the signal charge Q can be stored in the signal charge storage region 8 and the blooming can be effectively suppressed. The substrate potential Vsub At a high level (V _H ), the potential of the well region 5 becomes deeper than the potential of the signal charge storage region 8 as shown by the broken line in FIG. Is a voltage level that can be swept out to the N-type silicon substrate 1 side.

On the other hand, from the four output terminals φ1 to φ4,
The four-phase vertical transfer pulse V shown in FIG. ₁~ V_FourIs output
And these vertical transfer pulses V₁~ V_FourIs the drive circuit 2 respectively
5 to the corresponding transfer electrode 13. these
Four-phase vertical transfer pulse V₁~ V _FourBy receiving
The signal charge Q transferred from the section 2 is stored in the horizontal register section for each row.
Transfer to

The shutter pulse Ps and the vertical transfer pulses V _{1 to} V ₄ read data from the ROM in the pulse generation circuit 21 based on the input of the reference clock CLK and the horizontal synchronizing signal HD, decode the data, and output the decoded data. Is done.

Next, the signal processing operation of the CCD solid-state imaging device according to the present embodiment during the vertical blanking period (VBLK) will be described with reference to FIG. In FIG. 3, HD is a horizontal synchronizing signal, and periods B1, B2, and B3 each indicate a horizontal blanking period. V ₁ , V ₂ , V ₃ and V
Reference numeral ₄ denotes a four-phase drive vertical transfer pulse, and Vsub denotes a substrate potential. P in the read period R indicates a read pulse.

In the CCD solid-state imaging device of this embodiment, during normal operation, during each of the horizontal blanking periods B1 and B2 in the vertical blanking period (VBLK), the four-phase vertical transfer pulses V _{1 to} V ₄ are switched. By the selective switching operation of the circuit 23, the idle feed is performed by directly supplying the transfer electrode 13 without passing through the pulse delay circuit 22.

The horizontal blanking periods B1,
When a vertical transfer pulse (particularly, the fourth vertical transfer pulse V ₄ ) is applied during B2, the shutter pulse Ps (for example, 3
0V) is supplied directly to the substrate 1 without passing through the pulse delay circuit 22 in synchronization with the selective switching operation of the switching circuit 23 to raise the substrate potential Vsub. By applying the shutter pulse Ps, the signal charges Q accumulated in the light receiving unit 2 are swept away to the substrate 1 side.

At this time, the horizontal blanking periods B1 and B2 are counted by, for example, a programmable counter in the switching circuit 23. For example, the horizontal blanking period B3 immediately before the readout period R is set as the final horizontal blanking period, and this final horizontal blanking period is set. When the numerical value indicating the arrival of the horizontal blanking period B2 immediately before the ranking period B3 is counted, the switching operation of the switching circuit 23 switches the signal input path to the pulse delay circuit 22 side.

In the pulse delay circuit 22, the shutter pulses Ps and 4 input during the horizontal blanking period B2
The phase vertical transfer pulses V _{1 to} V ₄ are output with a predetermined delay. The delay time τ is calculated based on the input of data D relating to the shutter speed from the electronic iris or the program AE26.

After the horizontal blanking period B2, the input path of each signal is switched to the pulse delay circuit 22 side by the switching circuit 23. Therefore, the shutter pulse is again output after a predetermined time τ has elapsed regardless of the presence or absence of the horizontal blanking period. Ps and four-phase vertical transfer pulses V _{1 to} V ₄ are supplied to the substrate 1 and the transfer electrode 13, respectively. In FIG 1 and FIG 3, it noted these shutter pulse and vertical drive pulse respectively as Psτ and Vτ ₁ ~Vτ _4.

Since the shutter pulse Psτ is output immediately before the readout period R, it is the final shutter pulse. The exposure time L until the next readout period R is determined by the output timing of the shutter pulse Psτ. That is, the exposure time L corresponding to the electronic iris and the shutter speed set by the program AE26 is determined.

At this time, the vertical transfer pulses Vτ _{1 to} Vτ ₄
Usually causes a fluctuation (destabilization) of the substrate surface potential in the central part of the image area.
Shutter pulse P for sweeping away signal charge Q in light receiving section 2
Since sτ is applied in synchronization with the vertical transfer pulses Vτ _{1 to} Vτ ₄ , the substrate surface potential is stabilized without depending on the vertical transfer pulses Vτ _{1 to} Vτ ₄ .

The vertical blanking period (VBLK)
During this time, the shutter pulse Ps is supplied in each of the horizontal blanking periods B1 and B2 before the final shutter pulse Psτ is supplied, and the signal charge Q is swept away every horizontal blanking period B1 and B2. Therefore, it is possible to reliably prevent the signal charges Q from being left unsweeped when the final shutter pulse Psτ is applied.

The input signal from the switching circuit 23
Of the horizontal synchronization signal HD after the switching of the road
Rise, that is, at the completion of the final horizontal blanking period B3
Then, the input path of each signal is switched back to the pulse generation circuit 21 side.
Replace it. At this time, during the final horizontal blanking period B3
Has a shutter pulse Ps and a four-phase vertical transfer pulse V
₁~ V_FourIs not supplied to the substrate 1 and the transfer electrode 13. Obedience
Therefore, during the exposure period L up to the read period R,
There is no change in position and remains stabilized.

As described above, according to the present example, the shutter pulse Ps (and Psτ) for performing the electronic shutter function is synchronized with the vertical transfer pulses V _{1 to} V ₄ (and Vτ _{1 to} Vτ ₄ ) and the N-type silicon Since the voltage is applied to the substrate 1, the potential on the substrate surface is reduced by the vertical transfer pulses V _{1 to} V ₄ (and Vτ).
_{1 to} Vτ ₄ ) and is independent of
In the exposure period L after the output of the shutter pulse Psτ, the fluctuation of the signal charge amount caused by the fluctuation of the potential of the substrate surface can be prevented, and the operation characteristics can be stabilized.

The vertical blanking period (VBLK)
Since the shutter pulse Ps (and Psτ) is applied during this operation, the shutter pulse Ps (and Psτ) can be started at an arbitrary timing without being affected by the horizontal synchronization signal HD. Light reception amount adjustment can be performed.

As described above, according to the CCD solid-state imaging device according to the present embodiment, it is possible to finely adjust the amount of received light by controlling the shutter speed, to stabilize the operation characteristics, and to improve the electronic iris and the like. Optimal control can be performed for additional functions such as the program AE.

[0048] In the above embodiment, an example that does not output the vertical transfer pulses V ₁ ~V ₄ final horizontal blanking period B3, the other, as shown in the timing chart of FIG. 4, the final horizontal blanking period B3 Vertical transfer pulse V
It may be caused to output ₁ ~V _4.

In this case, the configurations of the switching circuit 23 and the pulse delay circuit 22 are simplified, but the potential on the substrate surface may fluctuate due to the vertical transfer pulses V _{1 to} V ₄ in the final horizontal blanking period B3. However, unlike the conventional case, in the preceding stage, the final shutter pulse Psτ and the vertical transfer pulses Vτ _{1 to} Vτ ₄ are output in synchronization, thereby stabilizing the substrate surface potential. variations in the substrate surface potential even if output vertical transfer pulses V ₁ ~V ₄ in a horizontal blanking period B3 becomes small.

In the above embodiment, an example in which the present invention is applied to a CCD solid-state imaging device of an interline transfer system has been described.
The present invention can also be applied to a CCD solid-state imaging device of a frame interline transfer system. In this case, high-speed transfer is performed with a two-phase vertical transfer pulse waveform during the vertical blanking period, and a shutter pulse synchronized with the vertical transfer pulse may be set at an arbitrary timing in the vertical blanking period. Also in this method, the circuit can be realized without much difficulty.

[0051]

As described above, the solid-state imaging device according to the present invention and its driving
According to the method, it is possible to finely adjust the amount of received light by controlling the shutter speed, to stabilize the operation characteristics, and to perform optimal control in additional functions such as the electronic iris and the program AE. .

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a CCD solid-state imaging device according to the present embodiment.

FIG. 2 is a potential diagram showing an electronic shutter operation of the CCD solid-state imaging device according to the embodiment.

FIG. 3 is a timing chart showing signal processing of the CCD solid-state imaging device according to the embodiment.

FIG. 4 is a timing chart showing another signal processing of the CCD solid-state imaging device according to the embodiment.

FIG. 5 is a timing chart showing signal processing of a CCD solid-state imaging device according to a conventional example.

FIG. 6 is an explanatory diagram showing disadvantages of a CCD solid-state imaging device according to a conventional example.

FIG. 7 is a timing chart showing signal processing of a CCD solid-state imaging device according to another conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N-type silicon substrate 2 Light-receiving part 3 Vertical register part 4 Channel stopper part 5 P-type well area 6 N-type well area 7 Positive charge accumulation area 8 Signal charge accumulation area 9 Channel stopper area 10, 12 Insulating layer 11 Vertical register 13 transfer electrodes 14 P-type region 15 readout gate unit 18 Al film 21 pulse generating circuit 22 pulse delay circuit 23 switching circuits 24 and 25 drive circuit 26 electronic iris or program AE CLK reference clock HD horizontal synchronizing signal V ₁ ~V ₄ and Vτ _{1 to} Vτ ₄ Vertical transfer pulse Ps and Psτ Shutter pulse

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-1-46379 (JP, A) JP-A-62-21377 (JP, A) JP-A-58-125961 (JP, A) JP-A-58-259 125964 (JP, A) JP-A-63-105579 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04N 5/30-5/335

Claims (2)

(57) [Claims] A first conductive type region formed on a surface side of a first conductive type semiconductor substrate; and a signal charge storage region formed on a surface side of the second conductive type region. In a solid-state imaging device adapted to control an exposure time by applying a predetermined potential to the semiconductor substrate and sweeping out signal charges accumulated in the signal charge accumulation region to the semiconductor substrate, A solid-state imaging device, wherein the predetermined potential is applied to the semiconductor substrate in synchronization with a vertical transfer pulse during a ranking period. 2. Applying a predetermined potential to a semiconductor substrate
As a result, the signal charge formed on the surface side of the semiconductor substrate is stored.
Sweeps out signal charges accumulated in the product area to the semiconductor substrate
To apply the predetermined potential to the semiconductor substrate.
Variable exposure to control exposure time
In the method for driving a solid-state imaging device, the predetermined potential is vertically transferred within a vertical blanking period.
Applying to the semiconductor substrate in synchronization with the pulse
Driving method of the solid-state imaging device.