JPH0759024A - Multi-screen television receiver - Google Patents

Abstract

PURPOSE:To simplify the configuration of a receiver by using control of a vertical line thinning filter circuit in common for control of a write/read address of a slave screen memory. CONSTITUTION:A selector 3 selects a base band signal of a High Vision broadcast from a tuner 2 as a master screen video signal and gives the signal to a video decoder 7, a selector 4 selects a base band video signal of an NTSC broadcast as a slave screen video signal and the signal is given to a video decoder 9, in which the signal is converted into a component signal corresponding to the slave screen video signal. The signal is A/D-converted at an A/D converter circuit 10 and the converted signal is given to a vertical line thinning filter circuit 12, and the obtained slave screen video signal is written at a predetermined address of a slave picture memory 19 in response to the count of horizontal vertical address counters. The read slave screen video signal is converted by a D/A converter 30 and the converted signal is given to a switch 8, the switching operation of the switch is controlled based on a switching signal generated by a frame signal generating circuit and the slave screen video image is displayed together with the master screen video image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-screen television receiver capable of inserting a reduced sub-screen into a main screen and viewing the video of the main screen and the video of the sub-screen at the same time.

[0002]

2. Description of the Related Art In recent years, it has been
Due to the spread of new equipment such as V-equipment, teletext, and new media, television receivers are required to have higher image quality and higher functionality.

As a function developed as the above-described high-performance, a picture-in-picture function (hereinafter referred to as PinP) that allows a reduced child screen to be inserted into a television screen (parent screen) and two screens can be viewed at the same time Function), and a multi-screen television receiver equipped with this PinP function is provided.

This multi-screen television receiver will be described with reference to the drawings. FIG. 6 is a block diagram showing a main part of a conventional multi-screen television receiver.

As shown in FIG. 6, a multi-screen television receiver equipped with a PinP function is a tuner for selectively receiving a predetermined broadcast wave from a plurality of broadcast waves received by an antenna 1. 2 is provided.

The baseband video signal corresponding to the broadcast wave selected by the tuner 2 is given to each selector 3, 4. The baseband video signal from the tuner 2 and the baseband video signal from the terminal 5 are input to the selector 3, and the selector 3 selects one of the two input baseband video signals as a main screen image. Select as a signal.

Similarly, the base band video signal from the tuner 2 and the base band video signal from the terminal 5 are input to the selector 4, and the selector 4 receives the input 2 signal.
One baseband video signal is selected from the one baseband video signal as the sub-screen video signal. The tuning operation of the tuner 2 and the selection operations of the selectors 3 and 4 are controlled by the tuning microcomputer 6.

The parent screen video signal selected by the selector 3 is given to the video decoder 7, and the video decoder 7 receives the parent screen video signal from the selector 3 as R, G, B or Y, R-.
It is converted into each component signal of Y and BY. The component signal from the decoder 7 is given to the switch 8 and the synchronization processing circuit 24.

On the other hand, the sub-screen video signal selected by the selector 4 is given to the video decoder 9, and the video decoder 9 outputs the sub-screen video signal from the selector 4 to R, G, B or Y, RY ,. Convert to each component signal of BY. The component signal from the video decoder 9 is A / D
It is given to the converter 10 and the synchronization processing circuit 11.

The A / D converter 10 converts the component signal from the video decoder 9 into a digital signal, and this digital signal is given to the vertical line thinning filter circuit 12. The vertical line thinning filter circuit 12 is a circuit for drawing the number of lines in the vertical direction for a predetermined number of minutes, and this circuit includes multipliers 13 and 14, adders 15 and 16,
It has a line memory 17 and a switch 18. The signal from the vertical line thinning filter circuit 12 is given to the child screen memory 19, and the child screen memory 19 stores and holds the signal given thereto.

A coefficient table R is provided in each of the multipliers 13 and 14.
The coefficients K1 and K2 written in the OM 33 are given respectively. As shown in Table 1, the coefficient table ROM 33 stores the coefficients K1 and K2 for the multipliers 13 and 14 as well as the control data for controlling the operation of the switch 18 and the filter output (output of the vertical line thinning circuit 12). The ROM read counter 34 has information regarding the validity.
It is written in association with the count value of.

[0012]

[Table 1] The coefficient K1 written in the coefficient table ROM 33,
The ROM read counter 34 reads K2, control data, and information concerning the validity of the filter output. RO
The count value of the M read counter 34 is set so as to circulate along a closed loop from 0 to 4.

The synchronization processing circuit 11 generates a clock signal CLK, a horizontal synchronization signal H, and a vertical synchronization signal V, which are synchronized with the component signal corresponding to the sub-picture video signal from the video decoder 9, based on the component signal. The clock signal CLK and the horizontal synchronizing signal H are given to the horizontal control circuit 20. The horizontal control circuit 20 uses the clock signal CL
A horizontal write period signal indicating a horizontal write valid period is generated based on K and the horizontal synchronizing signal H.

This horizontal writing period signal is applied to the horizontal address counter 21. The horizontal address counter 21
A count-up operation is performed during a period in which the horizontal write period signal is input, and the count value is output to the sub-screen memory 19 as a horizontal write address.

The clock signal and the vertical synchronization signal V from the synchronization processing circuit 11 are applied to the vertical control circuit 22, and the vertical control circuit 22 performs vertical writing indicating a vertical writing effective period based on the clock signal CLK and the vertical synchronization signal V. Generate a period signal. When the vertical writing period signal is generated, the count value of the ROM read counter 34 is set to 1
A signal is generated that indicates incrementing.

The vertical write period signal is applied to the vertical address counter 23. The vertical address counter 23 counts up during the period in which the vertical write period signal is input, and outputs the count value to the sub-screen memory 19 as a vertical write address.

Similar to the synchronization processing circuit 11, the synchronization processing circuit 24 is based on the parent screen video signal from the video decoder 7 and is synchronized with the clock signal CLK and the horizontal synchronization signal H.
The vertical synchronizing signal V is generated. The clock signal CLK and the horizontal synchronizing signal H are given to the horizontal control circuit 25. The horizontal control circuit 25 generates a horizontal display period signal indicating a horizontal display effective period based on the clock signal CLK and the horizontal synchronizing signal H.

This horizontal display period signal is given to the horizontal address counter 26. The horizontal address counter 26
A count-up operation is performed during the period in which the horizontal display period signal is input, and the count value is output to the sub-screen memory 19 as a horizontal read address.

The clock signal and the vertical synchronization signal V from the synchronization processing circuit 24 are given to the vertical control circuit 27, and the vertical control circuit 27 uses the clock signal CLK and the vertical synchronization signal V to display a vertical display period signal indicating a vertical display effective period. To generate.

The vertical display period signal is given to the vertical address counter 28. The vertical address counter 28 performs a count-up operation during the period in which the vertical display period signal is input, and outputs the count value to the sub-screen memory 19 as a horizontal read address.

Clock signal CL from the synchronization processing circuit 24
K, the horizontal synchronizing signal H and the vertical synchronizing signal V are given to the frame signal generating circuit 29. The frame signal generating circuit 29 generates a switching signal for switching the switch 8 based on the clock signal CLK, the horizontal synchronizing signal H and the vertical synchronizing signal V.

The switch 8 has a sub-picture video signal read from the sub-picture memory 19 through the D / A converter 30 together with the component signal (main-picture video signal) from the video decoder 7 and a framed signal generation circuit. And the framing signal from 31 is provided. The framed signal from the framed signal generation circuit 31 is a signal for defining the child screen display frame.

The switching operation of the switch 8 is performed by the frame signal generation circuit 2
This is performed based on a switching signal from the control unit 9 and, in accordance with this switching, a child screen process of inserting the image of the child screen into the parent screen is executed.

Next, the horizontal control circuit 20 for designating the write address of the child screen video signal in the child screen memory.
The vertical control circuit 22 will be described with reference to the drawings. 7 is a block diagram showing a horizontal control circuit used in the multi-screen television receiver of FIG. 6 for designating a write address of a sub-screen video signal in a sub-screen memory, and FIG. 8 is a block diagram of FIG. FIG. 3 is a block diagram showing a vertical control circuit used for a screen television receiver for designating a write address of small screen image information in a small screen memory.

As shown in FIG. 7, the horizontal control circuit 20 has a counter 102 provided with a terminal 101 for taking in a clock signal CLK and a horizontal synchronizing signal H.
Equipped with. The counter 102 is reset by the horizontal synchronizing signal H and performs a count-up operation based on the clock signal CLK. The count value of the counter 102 is the comparator 10
3 and 104, the comparator 103 outputs the counter 102.
And the value indicating the pixel position P1 in the horizontal effective period held in the register 105 are compared. When the count value of the counter 102 and the value indicating the pixel position P1 in the horizontal effective period match, the signal from the comparator 103 is input to the set terminal S of the flip-flop 107.

On the other hand, the comparator 104 includes the counter 10
The count value of 2 is compared with the value stored in the register 106 and indicating the pixel position P4 during the horizontal effective period. When the count value of the counter 102 and the value indicating the pixel position P4 in the horizontal effective period match, the signal from the comparator 104 is input to the reset terminal R of the flip-flop 107.

The flip-flop 107 has a set terminal S.
To the horizontal address counter 21 ( (Shown in FIG. 6).

As shown in FIG. 8, the vertical control circuit 22 has a counter 112 provided with a terminal 111 for receiving the clock signal CLK and the vertical synchronizing signal V.
Equipped with. The counter 112 is reset by the vertical synchronization signal V and performs a count-up operation with the clock signal CLK as a reference. The count value of the counter 112 is the comparator 11
3, 114, the comparator 113 is provided with a counter 112.
And the value indicating the pixel position Q1 in the vertical effective pixel period held in the register 115 are compared. When the count value of the counter 112 and the value indicating the pixel position Q1 in the vertical effective pixel period match, the signal from the comparator 113 is input to the set terminal S of the flip-flop 117.

On the other hand, the comparator 114 is the counter 11
The count value of 2 is compared with the value held in the register 116 and indicating the pixel position Q4 in the vertical effective pixel period. When the count value of the counter 112 and the value indicating the pixel position Q4 in the vertical effective pixel period match, the signal from the comparator 114 is input to the reset terminal R of the flip-flop 117.

The flip-flop 117 has a set terminal S.
To the ROM read counter via a terminal 118, which is a vertical write period signal indicating a vertical effective write period which is a period from the signal input from the comparator 113 to the reset terminal R to the signal input from the comparator 114 to the reset terminal R. 6) and the AND circuit 119. AND circuit 119
From the coefficient table ROM (shown in FIG. 6) to the terminal 1 along with the vertical write period signal from the flip-flop 117.
The thinning signal input via 20 is input. When the thinning signal instructs writing, the vertical writing period signal is output via the terminal 121 to the vertical address counter 23 (shown in FIG. 6).

Next, the horizontal control circuit 25 and the vertical control circuit 27 for designating the read address of the child screen information of the child screen memory will be described with reference to the drawings. 9 is a block diagram showing a horizontal control circuit used for the multi-screen television receiver of FIG. 6 for designating a read-out address of a sub-screen video signal in a sub-screen memory, and FIG. 10 is a multi-screen of FIG. FIG. 11 is a block diagram showing a vertical control circuit used for a television receiver for designating a read address of a small screen video signal in a small screen memory.

As shown in FIG. 9, the horizontal control circuit 25 has a counter 123 provided with a terminal 122 for receiving the clock signal CLK and the horizontal synchronizing signal H.
Equipped with. The counter 123 is reset by the horizontal synchronizing signal H and performs a count-up operation based on the clock signal CLK. The count value of the counter 123 is the comparator 12
4, 125, and the comparator 124 is provided with a counter 123.
And the value indicating the start pixel position of the horizontal effective display period held in the register 126 are compared. When the count value of the counter 122 and the value indicating the starting pixel position of the horizontal effective display period match, the signal from the comparator 124 is input to the set terminal S of the flip-flop 128.

On the other hand, the comparator 125 is the counter 12
The count value of 3 is compared with the value indicating the end pixel position of the horizontal effective display period held in the register 127. When the count value of the counter 123 and the value indicating the end pixel position of the horizontal effective display period match, the signal from the comparator 125 is input to the reset terminal R of the flip-flop 128.

The flip-flop 128 has a set terminal S
To the horizontal address counter 26 (shown in FIG. 6) via the terminal 129. Output).

As shown in FIG. 10, the vertical control circuit 27 has a counter 13 provided with a terminal 131 for taking in the clock signal CLK and the vertical synchronizing signal V.
2 is provided. The counter 132 is reset by the vertical synchronizing signal V and performs a count-up operation with the clock signal CLK as a reference. The count value of the counter 132 is the comparator 13
3, the comparator 133 is provided with a counter 132.
And the value indicating the start line position of the designated display period held in the register 135 are compared. When the count value of the counter 132 and the value indicating the start line position of the designated display period match, the signal from the comparator 133 is input to the set terminal S of the flip-flop 137.

On the other hand, the comparator 134 is the counter 13
The count value of 2 is compared with the value stored in the register 136 and indicating the end line position of the designated display period. When the count value of the counter 132 and the value indicating the end line position match, the signal from the comparator 134 is input to the reset terminal R of the flip-flop 137.

The flip-flop 137 has a set terminal S.
A vertical display period signal indicating a designated display period, which is a period from the signal input from the comparator 133 to the reset terminal R to the signal input from the comparator 134 to the reset terminal R via the terminal 138 to the vertical address counter 128 (see FIG. 6). Output).

Next, the frame signal generating circuit 29 will be described with reference to the drawings. FIG. 11 is a block diagram showing a frame signal generation circuit used in the multi-screen television receiver of FIG.

As shown in FIG. 11, the frame signal generating circuit 29 has a terminal 141 for receiving the clock signal CLK, the horizontal synchronizing signal H and the vertical synchronizing signal V from the synchronizing processing circuit 24 (shown in FIG. 6). The counter 142 and the counter 162 provided are provided. The counter 142 is reset by the horizontal synchronizing signal H and performs a count-up operation based on the clock signal CLK. The count value of the counter 142 is given to the comparators 143, 144, 145 and 146, and the comparator 143 compares the count value of the counter 142 with the value indicating the horizontal pixel position P1 held in the register 147. When the count value of the counter 142 and the value indicating the horizontal pixel position P1 match, the signal from the comparator 143 is input to the set terminal S of the flip-flop 151.

On the other hand, the comparator 144 is the counter 14
The count value of 2 is compared with the value indicating the horizontal pixel position P4 held in the register 148. When the count value of the counter 142 and the value indicating the horizontal pixel position P4 match, the signal from the comparator 144 outputs the signal from the flip-flop 151.
Is input to the reset terminal R of.

The flip-flop 151 has a set terminal S.
A signal indicating the period from the signal input from the comparator 143 to the reset terminal R to the signal input from the comparator 144 to the reset terminal R is output.

The comparator 145 detects the count value of the counter 142 and the horizontal pixel position P2 held in the register 149.
Is compared with the value indicating. When the count value of the counter 142 and the value indicating the horizontal pixel position P2 match, the comparator 14
The signal from 5 is the set terminal S of the flip-flop 152.
Entered in.

On the other hand, the comparator 146 is the counter 14
The count value of 2 is compared with the value indicating the horizontal pixel position P3 held in the register 150. When the count value of the counter 152 and the value indicating the horizontal pixel position P3 match, the signal from the comparator 146 outputs the signal.
Is input to the reset terminal R of.

The flip-flop 152 has a set terminal S.
A signal indicating the period from the signal input from the comparator 149 to the reset terminal R to the signal input from the comparator 150 to the reset terminal R is output.

The counter 162 is reset by the vertical synchronizing signal V and performs a count-up operation with the clock signal CLK as a reference. The count value of the counter 162 is the comparator 16
3, 164, 165, 166, and a comparator 163.
Compares the count value of the counter 162 with the value indicating the vertical pixel position Q1 held in the register 167. When the count value of the counter 162 and the value indicating the vertical pixel position Q1 match, the signal from the comparator 163 is input to the set terminal S of the flip-flop 171.

On the other hand, the comparator 164 is the counter 16
The count value of 2 is compared with the value indicating the vertical pixel position Q4 held in the register 168. When the count value of the counter 162 and the value indicating the vertical pixel position Q4 match, the signal from the comparator 164 outputs the signal from the flip-flop 171.
Is input to the reset terminal R of.

The flip-flop 171 has a set terminal S.
A signal indicating the period from the signal input from the comparator 163 to the reset terminal R to the signal input from the comparator 164 to the reset terminal R is output.

The comparator 165 detects the count value of the counter 162 and the vertical pixel position Q2 held in the register 169.
Is compared with the value indicating. When the count value of the counter 162 and the value indicating the vertical pixel position Q2 match, the comparator 16
The signal from 5 is the set terminal S of the flip-flop 172.
Entered in.

On the other hand, the comparator 166 is the counter 16
The count value of 2 is compared with the value indicating the vertical pixel position Q3 held in the register 170. When the count value of the counter 162 and the value indicating the vertical pixel position Q3 match, the signal from the comparator 166 outputs the signal from the flip-flop 172.
Is input to the reset terminal R of.

The flip-flop 172 has a set terminal S.
A signal indicating the period from the signal input from the comparator 169 to the reset terminal R to the signal input from the comparator 170 to the reset terminal R is output.

The signal from the flip-flop 151 and the signal from the flip-flop 171 are given to the AND circuit 173, and the AND circuit 173 has the flip-flop 151.
And the signal from the flip-flop 171 are ANDed and the signal indicating the result is ANDed.
It outputs to the switch 8 (shown in FIG. 6) via 74 and the terminal 175. The signal given to the switch 8 through the terminal 175 is a signal for indicating a rectangular area defined by the points P1, P4, Q1 and Q4.

The signal from flip-flop 152 and the signal from flip-flop 172 are applied to AND circuit 176, and AND circuit 176 causes flip-flop 152 to operate.
AND the signal from the flip-flop 172, and the signal showing the result is ANDed.
Output to 76.

The signal from the AND circuit 176 is inverted by the inverter 177, and the inverted signal is supplied to the AND circuit 174. AND circuit 174 is A
The logical product of the signal from the ND circuit 173 and the signal from the inverter 177 is calculated, and a signal indicating the result is output to the switch 8 via the terminal 178. This terminal 178
Signals given to the switch 8 via P2, P3, Q
This signal is used to indicate the rectangular area defined by the points 2 and Q3. The signal from the terminal 178 and the signal from the terminal 175 are combined with each other and then given to the switch 8 as a switching signal.

Next, the operation of the multi-screen television receiver will be described with reference to the drawings. 12 is a diagram for explaining the thinning-out process for the sub-screen image, FIG. 13 is a diagram for explaining the operation of the horizontal counter and the vertical counter, and FIG. 14 is a diagram for explaining the operation of the frame signal generating circuit. .

An example of inserting the NTSC broadcast sub-screen video into the main screen on which the high-definition broadcast video is displayed will be described.

The selector 3 selects the baseband video signal of the high-definition broadcast from the tuner 2 as the parent screen video signal, and the selected parent screen video signal is given to the video decoder 7. The video decoder 7 converts the parent screen video signal into a corresponding component signal.

On the other hand, the selector 4 selects the NTSC broadcast baseband video signal input via the terminal 5 as the sub-screen video signal. The selected sub-screen video signal is given to the video decoder 9, and the video decoder 9 converts the sub-screen video signal into a corresponding component signal.

The component signal corresponding to the sub-picture video signal is A / D converted by the A / D converter 10 and then given to the vertical line thinning filter circuit 12. The vertical line thinning filter circuit 12 performs processing for thinning a predetermined number of lines. For example, when inserting a 1/3 size child screen to the parent screen, the number of HDTV lines is 11
The number of vertical lines of NTSC is 5 while it is 25
Since there are 25 lines, 525 (112 lines)
5/3) Thinning is done to make a line.

The thinning process is performed by approximating the thinning rate to 3/4. That is, as shown in FIG. 12, three lines are generated from four lines, and each line is weighted in this generation. The coefficients K1 and K2 are used for this weighting.

The sub-picture video signal generated by the thinning-out process is written to a predetermined address of the sub-picture memory 19 according to the count value from the horizontal address counter 21 and the count value from the vertical address counter 23.
In this writing process, as shown in FIG. 13A, the vertical control circuit 22 continues the count-up operation for one vertical period, and the count value (the straight line 18 shown in the figure is increased.
1) indicates the values of the pixels Q1 to Q4 in the vertical effective period,
A vertical writing period signal is output. Each time this vertical write period signal is output, the vertical address counter 23 performs a count-up operation to generate a vertical write address (a straight line 182 shown in the drawing). On the other hand, in the horizontal control circuit 20, as shown in FIG. 13B, the count-up operation is continued for one horizontal period, and the count value (the straight line 183 in the figure) indicates the horizontal effective period pixel P1.
To P4, the horizontal writing period signal is output. Each time the horizontal write period signal is output, the horizontal address counter 21 performs a count-up operation to generate a horizontal write address (a straight line 184 shown in the drawing).

The sub-picture video signal written in the sub-picture memory 19 is read according to the count value from the horizontal address counter 26 and the count value from the vertical address counter 28.

In this read process, as shown in FIG. 13C, the vertical control circuit 27 continues the count-up operation for one vertical period, and the count value (the straight line 185 in the figure) indicates the designated display period. , The vertical display period signal is output. Each time this vertical display period signal is output, the vertical address counter 28 performs a count-up operation to generate a vertical read address (a straight line 186 shown in the figure). On the other hand, as shown in the horizontal control circuit 25 in FIG. 13D, when the count-up operation is continued for one horizontal period and the count value (the straight line 187 in the figure) indicates the designated display period, A horizontal writing period signal is output. Each time the horizontal write period signal is output, the horizontal address counter 26 is incremented to generate a horizontal read address (a straight line 188 shown in the figure).

The read sub-picture video signal is D / A converted by the D / A converter 30 and then applied to the switch 8. The switching operation of the switch 8 is controlled based on the switching signal generated by the frame signal generation circuit 29. In this switching signal generation processing, as shown in FIG. 14, P1, P4, Q1,
A signal for indicating a rectangular area defined by each point of Q4 and a signal for indicating a rectangular area defined by each point of P2, P3, Q2, Q3 are generated, and a composite signal of these is switched. It is given to the switch 8 as a signal.

The switch 8 sequentially selects the main screen video signal, the sub screen video signal and the framed signal based on the switching signal from the frame signal generation circuit 29, and the selected signal is the terminal 35.
To a CRT (not shown). On the CRT, a parent screen image corresponding to the parent screen image signal and a child screen image corresponding to the child screen image signal are displayed.

However, in the above multi-screen television,
Multiplier 1 in vertical line thinning filter circuit 12
Since the control for the coefficients 3 and 14 and the control for the switch 18 and the control for the writing and reading addresses of the small screen memory 19 are individually performed, the configuration becomes complicated.

[0066]

As described above, in the above-mentioned multi-screen television, the control of the coefficients of the multipliers 13 and 14 and the control of the switch 18 in the vertical line thinning filter circuit 12 and the sub-screen memory 19 are performed. Since the write and read addresses are controlled individually, the configuration becomes complicated.

The present invention provides a multi-screen television receiver which can control the vertical line thinning filter circuit and the write / read address of the sub-screen memory in common and can simplify the configuration. The purpose is to do.

[0068]

According to the present invention, a first video capturing means captures a first video signal as a parent screen video signal, and a second video capturing means captures a second video signal.
Vertical line thinning processing is performed on the second video signal to generate a sub-screen video signal from the second video signal,
The sub-screen video signal obtained by the vertical line thinning-out process is written in the storage means based on the horizontal write address and the vertical write address, and the sub-screen video signal is read out from the storage means in the horizontal direction and the vertical direction. A multi-screen television receiver for reading out based on an address and synthesizing the read-out sub-screen video signal with the first video signal to insert the sub-screen video signal into a main screen. A first program in which an execution procedure for vertical line thinning processing is described, a second program in which an execution procedure for generating the vertical direction write address is described, and the vertical direction read address are generated. And a third program that describes an execution procedure for Control for the vertical line thinning processing according to a procedure, control for the vertical write address generation according to the procedure described in the second program, and vertical read according to the procedure described in the third program. Control means for executing control for address generation is provided.

[0069]

[Operation] In the multi-screen television receiver of the present invention, a first program in which an execution procedure for the vertical line thinning processing is described and an execution procedure for generating the vertical write address are described. A second program and a third program in which an execution procedure for generating the vertical read address is described.
The control for the vertical line thinning process according to the procedure described in the first program, the control for the vertical write address generation according to the procedure described in the second program, and the third program Control means are provided for performing control over the vertical read address generation in accordance with the described procedure.

Control for the vertical line thinning process,
The control for the generation of the vertical write address and the control for the generation of the vertical read address are performed by software. The control means can operate with a clock signal at a clock rate of the image at most, and the operation of the control means does not require a semiconductor process having a very high processing speed. Therefore, the control for the vertical line thinning filter circuit and the control for the write / read address of the child screen memory can be commonly performed, and the configuration can be simplified.

[0071]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the main part of the multi-screen television receiver of the present invention. As shown in FIG. 1, a multi-screen television receiver equipped with a PinP function includes a tuner 2 for selectively receiving a predetermined broadcast wave from a plurality of broadcast waves received by an antenna 1. .

The baseband video signal corresponding to the broadcast wave selected by the tuner 2 is given to each selector 3, 4. The baseband video signal from the tuner 2 and the baseband video signal from the terminal 5 are input to the selector 3, and the selector 3 selects one of the two input baseband video signals as a main screen image. Select as a signal.

Similarly, the baseband video signal from the terminal 5 is input to the selector 4 together with the baseband video signal from the tuner 2, and the selector 4 receives the input 2
One of the baseband video signals is selected from the two baseband video signals as the sub-picture video signal. The tuning operation of the tuner 2 and the selection operations of the selectors 3 and 4 are controlled by the tuning microcomputer 6.

The parent screen video signal selected by the selector 3 is given to the video decoder 7, and the video decoder 7 sends the parent screen video signal from the selector 3 to R, G, B or Y, R-.
It is converted into each component signal of Y and BY. The component signal from the video decoder 7 is given to the switch 8 and the synchronization processing circuit 24.

On the other hand, the sub-picture video signal selected by the selector 4 is given to the video decoder 9, and the video decoder 9 outputs the baseband video signal from the selector 4 to R,
G, B or Y, RY, BY component signals are converted. The component signal from the video decoder 9 is given to the A / D converter 10 and the synchronization processing circuit 11.

The A / D converter 10 converts the component signal from the video decoder 9 into a digital signal, and this digital signal is given to the vertical line thinning filter circuit 12. The vertical line thinning filter circuit 12 is a circuit for drawing the number of lines in the vertical direction for a predetermined number of minutes, and this circuit includes multipliers 13 and 14, adders 15 and 16,
It is composed of a line memory 17 and a switch 18.
The signal from the vertical line thinning filter circuit 12 is given to the child screen memory 19. The child screen memory 19 stores and holds the signal given thereto.

The synchronization processing circuit 11 generates a clock signal CLK, a horizontal synchronization signal H, and a vertical synchronization signal V which are synchronized with the sub-screen video signal from the video decoder 9 based on the sub-screen video signal.
The clock signal CLK and the horizontal synchronizing signal H are given to the horizontal control circuit 20. Horizontal control circuit 2
0 generates a horizontal write period signal indicating a horizontal write valid period based on the clock signal CLK and the horizontal synchronizing signal H.

This horizontal write period signal is applied to horizontal address counter 21. The horizontal address counter 21
A count-up operation is performed during a period in which the horizontal write period signal is input, and the count value is output to the sub-screen memory 19 as a horizontal write address.

Like the synchronization processing circuit 11, the synchronization processing circuit 24 generates a clock signal CLK, a horizontal synchronization signal H, and a vertical synchronization signal V which are synchronized with the parent screen video signal signal from the video decoder 7 based on the same. The clock signal CLK and the horizontal synchronizing signal H are given to the horizontal control circuit 25. The horizontal control circuit 25 uses the clock signal CL
A horizontal display period signal indicating a horizontal display effective period is generated based on K and the horizontal synchronizing signal H.

This horizontal display period signal is given to the horizontal address counter 26. The horizontal address counter 26
A count-up operation is performed during the period in which the horizontal display period signal is input, and the count value is output to the sub-screen memory 19 as a horizontal read address.

The control unit 41 controls the clock signal and vertical synchronization signal V from the synchronization processing circuit 11 and the clock signal and vertical synchronization signal V from the synchronization processing circuit 24.
Given to.

The control unit 41 includes a coefficient setting control program for setting the coefficients K1 and K2 to be given to the multipliers 13 and 14, and a vertical write period signal for generating a vertical write period signal indicating a vertical write valid period. Write period signal generation program and write address setting control for setting a vertical write address for writing the sub-screen video signal from the vertical line thinning filter circuit 12 to the sub-screen memory 19 based on the vertical write period signal A program, a vertical display period signal generation program for generating a vertical display period signal indicating a vertical display effective period, and a vertical read address for reading a small screen video signal from the small screen memory 19 based on the vertical display period signal. And a read address setting control program for setting.

The control unit 41 controls the coefficient setting control for setting the coefficients K1 and K2 based on the coefficient setting control program and the vertical writing period signal generation control for generating the vertical writing period signal based on the vertical writing period signal generation program. And a write address setting control for setting a vertical write address of the small screen video signal to the small screen memory 19 based on the write address setting control program, and a vertical display period signal is generated based on the vertical display period signal generation program. The vertical display period signal generation control and the read address setting control for setting the vertical read address of the small screen image signal from the small screen memory 19 are executed based on the read address setting control.

Clock signal CL from the synchronization processing circuit 24
K, the horizontal synchronizing signal H and the vertical synchronizing signal V are given to the frame signal generating circuit 42. The frame signal generation circuit 42 generates a switching signal for switching the switch 8 based on the clock signal CLK, the horizontal synchronizing signal H, and the vertical synchronizing signal V.

The switch 8 has a component signal corresponding to the master screen video signal from the video decoder 7 and a slave screen video signal read from the slave screen memory 19 through the D / A converter 30 and a slave screen video signal. And a framing signal for framing. The framed signal is generated by the framed signal generation circuit 31.

The switching operation of the switch 8 is performed by the frame signal generation circuit 4
It is performed based on the switching signal from 2.

Next, the structure of the control unit 41 will be described with reference to the drawings. FIG. 2 is a block diagram showing a control unit used in the television receiver of FIG.

As shown in FIG. 2, the control unit 41 includes a data RAM 201, an instruction RAM 202, an instruction decoder 203, a program counter 204, an index register 205, an arithmetic register 206 and an arithmetic circuit 2.
07, output ports 208, 209, 210, 211, 2
12, 213, input ports 214, 215, switch 2
16 and bus lines connecting them.

The input port 214 is a port for taking in the clock signal CLK and the vertical synchronizing signal V from the synchronous processing circuit 11 (shown in FIG. 1), and the input port 215.
Is a port for taking in the clock signal CLK and the vertical synchronizing signal V from the synchronization processing circuit 24 (shown in FIG. 1).

The output port 208 is a port for outputting the coefficient K1 to the multiplier 13 (shown in FIG. 1),
The output port 209 is a port for outputting the coefficient K2 to the multiplier 14 (shown in FIG. 1).
Reference numeral 10 is a port for outputting a control signal for controlling the switching operation of the switch 18.

On the other hand, the output port 211 is a port for outputting a write address in the vertical direction to the child screen memory 19 (shown in FIG. 1), and the output port 212 is a vertical read in the child screen memory 19. It is a port for outputting an address. The output port 213 is the frame signal generation circuit 2
9 (shown in FIG. 1) is a port for outputting the clock signal CLK, the horizontal synchronizing signal H, and the vertical synchronizing signal V.

The command RAM 202 stores coded execution instructions corresponding to the above-mentioned programs, and the execution instructions are read based on the read address generated by the program counter 204. The read execution instruction is given to the instruction decoder 203, and the instruction decoder 203
Decodes the execution instruction from the instruction RAM 202, and based on the result of the decoding, each register 205, 206, each output, input port 208, 209, 210, 211, 212, 21.
3, 214, 215, switch 216 and data RA
M201 is controlled.

As shown in Table 2, the data RAM 201 stores data relating to control executed by the control unit.

[0095]

[Table 2] Next, the configuration of the frame signal generation circuit 42 will be described with reference to the drawings. FIG. 3 is a block diagram showing a frame signal generating circuit used in the multi-screen television receiver of FIG.

The frame signal generation circuit 42, as shown in FIG. 3, receives the clock signal CL from the control unit 41.
It has a counter 222 provided with a terminal 221 for taking in K, the horizontal synchronizing signal H, and the vertical synchronizing signal V. The counter 222 is reset by the horizontal synchronizing signal H and performs a count-up operation with the clock signal CLK as a reference. The count value of the counter 222 is the comparators 223, 2
24, 225, 226, the comparator 223 compares the count value of the counter 222 with the value indicating the horizontal pixel position P1 held in the register 227. When the count value of the counter 222 and the value indicating the horizontal pixel position P1 match, the signal from the comparator 223 is input to the set terminal S of the flip-flop 231.

On the other hand, the comparator 224 has the counter 22
The count value of 2 is compared with the value indicating the horizontal pixel position P4 held in the register 228. When the count value of the counter 222 and the value indicating the horizontal pixel position P4 match, the signal from the comparator 224 outputs the signal from the flip-flop 231.
Is input to the reset terminal R of.

The flip-flop 231 has a set terminal S
A signal indicating the period from the signal input from the comparator 223 to the reset terminal R to the signal input from the comparator 224 to the reset terminal R is output.

The comparator 225 determines the count value of the counter 222 and the horizontal pixel position P2 held in the register 229.
Is compared with the value indicating. When the count value of the counter 222 and the value indicating the horizontal pixel position P2 match, the comparator 22
The signal from 5 is the set terminal S of the flip-flop 232.
Entered in.

On the other hand, the comparator 226 has the counter 22
The count value of 2 is compared with the value indicating the horizontal pixel position P3 held in the register 230. When the count value of the counter 222 and the value indicating the horizontal pixel position P3 match, the signal from the comparator 226 causes the flip-flop 232.
Is input to the reset terminal R of.

The flip-flop 232 has a set terminal S
A signal indicating the period from the signal input from the comparator 225 to the reset terminal R to the signal input from the comparator 226 to the reset terminal R is output.

The signal from flip-flop 231 is applied to terminal 233 and AND circuit 234.

On the other hand, the signal from the flip-flop 232 is given to the inverter 235 and the inverter 23
Reference numeral 5 inverts the signal from the flip-flop 232 and outputs the inverted signal. The signal from the inverter 235 is given to the AND circuit 234. AND circuit 2
34 performs a logical product of the signal from the flip-flop 231 and the signal from the inverter 235, and outputs a signal indicating the result as a switching signal to the switch 8 (shown in FIG. 1) via the terminal 236.

Next, the operation of the multi-screen television receiver will be described.

The selector 3 selects the baseband video signal of the high-definition broadcast from the tuner 2 as the parent screen video signal, and the selected parent screen video signal is given to the video decoder 7. The video decoder 7 converts the parent screen video signal into a corresponding component signal.

On the other hand, the selector 4 selects the NTSC broadcast baseband video signal input through the terminal 5 as the sub-screen video signal. The selected sub-screen video signal is given to the video decoder 9, and the video decoder 9 converts the sub-screen video signal into a corresponding component signal.
The component signal corresponding to the sub-screen video signal is A / D
After being A / D converted by the converter 10, it is applied to the vertical line thinning filter circuit 12. The vertical line thinning filter circuit 12 performs processing for thinning a predetermined number of lines. For example, when inserting a 1/3 size child screen to the parent screen, the number of high definition lines is 1125, whereas the number of vertical lines of NTSC is 525, so 525 lines are 375. Thinning is performed to make (1125/3) lines. Ie 4
Three lines are generated from each line, and weighting is performed on each line for this generation. The coefficients K1 and K2 stored in the data RAM 201 of the control unit 41 are used for this weighting.

The sub-picture video signal generated by the thinning-out process is written in a predetermined address of the sub-picture memory 19 according to the count value from the horizontal address counter 21 and the count value of the control unit 41.

The sub-picture video signal written in the sub-picture memory 19 is read according to the count value from the horizontal address counter 26 and the count value from the control unit 41, and the read sub-picture video signal is D / It is given to the switch 8 after being D / A converted by the A converter 30.

The switch 8 sequentially switches the parent screen image signal, the child screen image signal and the framed signal from the framed signal generation circuit 31 based on the switching signal from the frame signal generation circuit 42, and the selected signal is the terminal 35. To a CRT (not shown). On the CRT, a parent screen image corresponding to the parent screen image signal and a child screen image corresponding to the child screen image signal are displayed.

Next, the vertical control processing of the control unit 41 will be described with reference to the drawings. Figure 4
1 is a flow chart for explaining the operation of the control unit used in the multi-screen television receiver of FIG. 1, and FIG. 5 shows the sub-screen processing in the control unit used in the multi-screen television receiver of FIG. It is a flow chart for explaining.

The control unit 41 executes each control each time the horizontal synchronization signal H from the synchronization processing circuit 11 and the horizontal synchronization signal from the synchronization processing circuit 24 are input.

First, the presence or absence of the input of the horizontal synchronizing signal H of the sub-picture video signal is detected as shown in FIG. 4 (step 301). When the horizontal synchronizing signal H of the small screen image signal is input, the small screen process 302 is executed (step 3).
02).

On the other hand, when the horizontal synchronizing signal H of the sub-screen video signal is not input, it is detected whether or not the horizontal synchronizing signal H is input to the main-screen video signal (step 303).

If the horizontal synchronizing signal H of the parent screen video signal is not input, the process from step 302 is repeated. When the horizontal synchronizing signal H of the parent screen image signal is input, the presence or absence of the vertical synchronizing signal V of the parent screen image signal is detected (step 304).

When the vertical synchronizing signal V of the parent screen video signal is input, the parent screen line number of the parent screen video signal is "0".
Is set, that is, the data described in the address 9 of the data RAM 201 is set to "0" (step 305).

Then, the vertical read address described at address 16 of the data RAM 201 is set to "0" (step 306).

When the vertical synchronizing signal V of the parent screen video signal is not input, 1 is added to the parent screen line number (step 307).

After adding 1 to the parent screen line number, it is determined whether or not the following expression (1) is satisfied (step 308).

Read start line <parent screen line number <read end line (1) When the parent screen line number does not satisfy the above equation (1),
The data "0,0,0,0" is output to the frame signal generation circuit 42 via the output port 213 (step 30).
9). For example, as shown in FIG. 14, when the parent screen line number is not between Q1 and Q4, the frame signal generation circuit 42 generates a switching signal for selecting only the parent screen video signal, and this switching signal is It is given to the switch 8.

When the parent screen line number satisfies the above expression (1), 1 is added to the vertical read address described in the address 16 of the data RAM 201, and the added data is added between P1 and P4. Is output to the frame signal generation circuit 42 via the output port 213 (step 310).

Next, it is determined whether the following expression (2) or expression (3) is satisfied (step 311).

Frame top line <parent screen line number <frame inner top line (2) Frame inner bottom line <parent screen line number <frame bottom line ... (3) The parent screen line number is the above formula (2). And when either of the expressions (3) is satisfied, "P1, P4, P4, P4
Is output to the frame signal generation circuit 42 via the output port 213 (step 312). The frame signal generation circuit 42 generates a switching signal for selecting the frame cutting signal, and this switching signal is given to the switch 8.

When the parent screen line number does not satisfy both of the above equations (2) and (3), "P1, P2, P3
, P4 "data is output to the frame signal generation circuit 42 through the output port 213 (step 313). The frame signal generation circuit 42 generates a switching signal for selecting the child video signal, and this switching signal is given to the switch 8.

Next, the child screen processing (step 302) will be described with reference to FIG.

When the horizontal synchronizing signal H of the sub-picture video signal is input, the sub-picture processing is performed as shown in FIG. 5 (step 302). First, the presence / absence of input of the vertical synchronizing signal V of the sub-picture video signal is detected (step 401).

When the vertical synchronizing signal V of the sub-picture video signal is input, the sub-screen line number described in the address 8 of the data RAM 201 is set to "0" (step 4).
02).

Then, the coefficient table pointer described in the address 5 of the data RAM 201 is set to "0" (step 403), and the vertical write address is described in the address 17 of the data RAM 201 to "0". (Step 404).

When the vertical synchronizing signal V of the sub-picture video signal is not input, 1 is added to the sub-picture line number (step 405).

After adding 1 to the sub-screen line number, it is judged whether or not the following expression (4) is satisfied (step 406).

Write start line <parent screen line number <write end line (4) When the child screen line number does not satisfy the above equation (4),
The step returns to step 301.

When the child screen line number satisfies the above equation (4), the coefficient table indicated by the coefficient table pointer is read out, and the corresponding coefficients K1, K2 and the control signal for the switch 18 are output ports 208, 20.
9 and 210 respectively (step 40
7).

Next, when "VALID" is obtained from the read coefficient table, 1 is added to the vertical write address, and the added vertical write address is output to the child screen memory 19 via the output port 211. (Step 408).

After the vertical write address is output to the child screen memory 19, 1 is added to the coefficient table pointer (step 409), and when the coefficient table pointer reaches "5", the coefficient table pointer is set to "0". The setting process is performed (step 410).

The above coefficient setting control, vertical write period signal generation control, vertical write address setting control, vertical display period signal generation control, and vertical read address setting control are within one horizontal period. If each program has a capacity of 100 steps, the processing speed will be about 1.57 MHz (= 15.7 KHz × 100).

Therefore, the coefficient setting control, the vertical write period signal generation control, the vertical write address setting control, the vertical display period signal generation control, and the vertical read address setting control described above can be performed at high speed. It can be executed without using a processor having a processing speed, and the configuration can be simplified.

Further, the specification of the entire system can be easily changed by changing the contents of the program.

[0137]

As described above, according to the multi-screen television receiver of the present invention, the control for the vertical line thinning filter circuit and the control for the writing and reading addresses of the sub-screen memory are commonly performed. Therefore, the configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of a multi-screen television receiver of the present invention.

FIG. 2 is a block diagram showing a control unit used in the multi-screen television receiver shown in FIG.

FIG. 3 is a block diagram showing a frame signal generation circuit used in the multi-screen television receiver shown in FIG.

4 is a flow chart for explaining the operation of a control unit used in the multi-screen television receiver of FIG.

5 is a flowchart for explaining child screen processing in a control unit used in the multi-screen television receiver of FIG.

FIG. 6 is a block diagram showing a main part of a conventional multi-screen television receiver.

7 is a block diagram showing a horizontal control circuit used for the multi-screen television receiver of FIG. 6 for designating a write address of a sub-screen video signal in a sub-screen memory.

8 is a block diagram showing a vertical control circuit used for the multi-screen television receiver of FIG. 6 for designating a write address of a sub-screen video signal in a sub-screen memory.

9 is a block diagram showing a horizontal control circuit used for the multi-screen television receiver of FIG. 6 for designating a read-out address of a small-screen video signal in a small-screen memory.

10 is a block diagram showing a vertical control circuit used for the multi-screen television receiver of FIG. 6 for designating a read address of a small screen video signal in a small screen memory.

11 is a block diagram showing a frame signal generation circuit used in the multi-screen television receiver shown in FIG.

[Fig. 12] Fig. 12 is a diagram for explaining a thinning-out process for a small screen image.

FIG. 13 is a diagram for explaining operations of a horizontal counter and a vertical counter.

FIG. 14 is a diagram for explaining the operation of the frame signal generation circuit.

[Explanation of symbols]

3, 4 ... Selector, 12 ... Vertical line thinning filter circuit, 19 ... Sub-screen memory, 41 ... Control unit, 42 ... Frame signal generating circuit, 201 ... Data RAM, 2
07 ... Operation circuit.

Claims (1)

[Claims] 1. A first video capturing means captures a first video signal as a parent screen video signal, a second video capturing means captures a second video signal, and the second video signal is a child. Vertical line thinning processing for generating a screen video signal is performed on the second video signal, and a sub-screen video signal obtained by the vertical line thinning processing is stored based on a horizontal write address and a vertical write address. Means to read the child screen video signal from the storage means based on a horizontal read address and a vertical read address, and synthesize the read child screen video signal with the first video signal A multi-screen television receiver for inserting the sub-screen video signal into the first screen, wherein the execution procedure for the vertical line thinning-out process is described. A program, a second program in which an execution procedure for generating the vertical write address is described, and a third program in which an execution procedure for generating the vertical read address is described. Control for the vertical line thinning process according to the procedure described in the first program, control for the vertical write address generation according to the procedure described in the second program, and the third 5. A multi-screen television receiver, comprising control means for executing the control for the vertical read address generation according to the procedure described in the program.