JPH0758900B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device that operates an output circuit that drives an external output terminal stably and at high speed.

[Conventional technology]

Conventionally, this type of semiconductor device is a core entity used together with this semiconductor device. Although the microprocessor has the same number of outputs as the number of data, at present, 8-bit and 16-bit output semiconductor devices are being developed because 8-bit and 16-bit microprocessors are generally used. Further, as a future trend, more and more bits are being promoted. Here, an example of an 8-bit output semiconductor device will be described with reference to FIG.

First, the output 1 bit will be described. The output circuit unit for driving the output electrode O ₀ connected to the external terminal is a P-channel type insulated gate field effect transistor (hereinafter referred to as IGFET) P ₀ and an N-channel type IGFET N. ₀ and the terminals of P ₀ and N ₀ are connected as follows. IGFET P ₀
Is the source connected to the first power supply Vcc supplied to Vco supplied by aluminum wiring, the gate is connected to the first data signal B, the drain is connected to the output electrode O ₀ , and IGCET N ₀ is the source connected to the second power supply.
Connect Vs to the power supply Vso supplied by aluminum wiring,
The gate is connected to the second data signal A and the drain is connected to the output electrode O ₀ . Here, Rc and Rs are wiring resistances of Vcc and Vs, respectively. The semiconductor device has 8 such output electrodes (O _{0 to} O ₇ ).
It is composed of individual pieces.

Next, the circuit operation will be described. The time (speed) for charging / discharging the voltage of this electrode O ₀ is set by g _{m of} P ₀ and N ₀ and O ₀
The amount of charge stored in the
In order to realize high speed operation, g _m of P ₀ and N ₀ must be increased. However, if gm is increased, the charging / discharging flow becomes larger, and the total current, which is the sum of all output bits, becomes
1, Inflow and outflow to the second power source. As a result, the potentials of the first and second power supplies Vso and Vco wired on the semiconductor substrate with an aluminum material or the like largely change (vibrate) due to the wiring resistances Rc and Rs and the inductance of the external terminal (and the lead electrode). As a result of the fluctuations in Vso and Vco in this way, a logic circuit such as an input circuit using Vso and Vco as a power source malfunctions, and speeding up is hindered.

Next, a specific operation will be described with reference to the timing chart of FIG. First, output data D from "Low" to "High"
Then, the first and second data signals B, A go from “Low” to “Hig” via 2NOR: N1, inverter: N3,2NAND: N ₂ and inverter N4.
It changes to h ". Here ob is set to" High "and ▲ ▼ is set to" Low. "When the data signal B becomes" High ", IGFET P
₀ is "off", and data signal A becomes "High", so IGF
ET N ₀ turns “on”. Output electrode O when N ₀ turns on
₀ discharges from 5 ^V to 0 ^V, and this discharge time t is expressed as follows.

To decrease t, I ₀ must be increased, that is, gm of N ₀ must be increased. 8-bit output semiconductor device Then, Is becomes large and the peak becomes about 200 ^mA . If Rs = 5Ω, Vso instantly rises from 0 ^V to 1 ^V.
If the input voltage Vi _N of the input circuit that shares this Vso is 2.5 ^V and Vj must be set to “Low”, when Vso rises to 1 ^V , the potential difference between the gate and source of IGFET Nj becomes small, and gm decreases Vj rises from instant 0 ^V to 3 ^V, malfunction against the expected value 0 ^V. This malfunction prevents high-speed operation. The current value must be reduced in order to prevent malfunction, but this makes it impossible to achieve high speed. As described above, it has been difficult to develop a conventional semiconductor device that realizes high-speed operation.

[Problems to be solved by the invention]

In the above-described conventional semiconductor device, the output circuit unit must be speeded up in order to realize high speed operation of the device, but as a measure, the N of the final stage (connected to the output external terminal) is used.
There is a method of increasing the g _m of the channel and P-channel IGFET to increase the charging / discharging current, but on the other hand, the current flowing during charging / discharging causes the power supply or ground on the aluminum wiring to fluctuate. The power supply or the ground of the logic circuits such as the input circuit and the sense amplifier circuit that are present also fluctuate in the same manner, causing a malfunction. As described above, there is a drawback that speeding up cannot be easily realized.

Furthermore, as a recent trend, semiconductor devices have been promoted to have multi-bits in the number of outputs along with the multi-bits of microprocessors, 4 → 8 → 16 → 32 bits. The fluctuation of the power supply ground potential becomes even larger. As described above, in order to realize high speed, it is necessary to increase g _m of the final stage transistor, but it is difficult to perform optimal design because it causes noise to the reference voltage of the aluminum wiring, and high speed is required. There is a drawback that a stable semiconductor device cannot be realized.

An object of the present invention is to eliminate the drawbacks of the conventional semiconductor device and to provide a high-speed and stable semiconductor device.

In contrast to the conventional semiconductor device described above, the present invention provides a comparator for detecting a voltage at an external terminal and an output signal from the comparator.
A circuit for holding the high-level voltage smaller than the power supply voltage is provided, and the difference is that the amount of charge charged to the external terminal is minimized.

[Means for solving problems]

In the semiconductor device of the present invention, the source of the first conductivity type first insulated gate field effect transistor provided on the semiconductor substrate is the first power source, the gate is the first data signal, and the drain is the external terminal. Connect to the output electrode that is electrically connected,
For driving an external terminal, the source of the second insulated gate field effect transistor of the opposite conductivity type to the first conductivity type is connected to the second power supply, the gate is connected to the second data signal, and the drain is connected to the output electrode. In a semiconductor device including the output transistor section, a comparator that receives the voltage of the output electrode and compares it with a reference voltage, and a voltage of the output electrode when the first insulated gate field effect transistor is "on" When the voltage becomes higher than the voltage, the first insulated gate field effect transistor is set to “off” by the output of the comparator, and when the voltage of the output electrode becomes lower than the reference voltage, the first insulated gate field effect transistor is set to “on”. A first logic circuit for controlling a first data signal, and a third insulated gate field effect transistor having the first power source as a source and commonly connecting a drain and a gate. A transistor, a fourth insulated gate field transistor having a gate connected to the third data signal, a drain connected to the output electrode, and a source connected to the drain of the third insulated gate field transistor; When the voltage of the output electrode becomes higher than the reference voltage when the insulated gate field effect transistor of "4" is turned on, the fourth insulated gate field effect transistor is turned "on" by the output of the comparator, and the voltage of the output electrode is changed to the reference voltage. A second one controlling the third data signal which, when lower, sets the fourth insulated gate field effect transistor to "off".
And a logic circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, one embodiment of the present invention is a P-channel type first IGFET P ₁₀
The source of which is connected to the first power source Vco (+5 ^V ), the gate of which is connected to the first data signal B1 and the drain of which is connected to the output electrode O ₀ , and the second conductivity type N ^- channel type second IGFET. A semiconductor device having an output transistor section for driving an external terminal, in which the source of N ₁₀ is connected to the second power supply Vso (0 ^V ), the gate is connected to the second data signal A1, and the drain is connected to the output electrode O _0. At the output electrode O ₀ voltage, the reference voltage Vref (+3 ^V )
A comparator composed of IGFETs P ₁₃ , P ₁₄ , N ₁₁ , N ₁₂ N _{13 to} be compared with and a logic circuit NO ₇ NO ₆ , NO ₂ and its inverter for controlling the data signal B 1 by the output Vcom of the comparator. a circuit portion constituted by NO _4, the power Vco as a source, and the IGFET P ₁₁ commonly connecting the drain and the gate, a source connected to the drain and the gate of P _11, a third data for controlling the gate by Vcom Connect to signal B2 and drain to output electrode O ₀
And IGFET P ₁₂ connected to.
Here, the logic circuits NO ₇ , NO ₆ , NO ₃ , NO ₄ are inverter circuits, and the logic circuit NO ₂ is a 3-input NOR circuit. The data signal B2 is
Generated by logic circuits NO ₇ , NO ₁ , NO ₃ that input Vcom, ob, ▲ ▼ deactivate the output circuit and data signal O ₀
Is a control signal that makes the signal floating. In a normal operating state, it is ob ... "High" ▲ ▼ ... "Low".

Next, the operation of each circuit section will be described with reference to the timing chart of FIG. In FIG. 2, first, when the output data D is changed from "Low" to "High" in this embodiment, the data signal B1 holds "High" and the data signal B2 is "Low".
Changes from "High", and the data signal A1 also changes from "Low" to "High". Data signals B1 and B2 are both "High"
Therefore, IGFETs P ₁₀ and P ₁₂ are "off", and data signal A1 is "H".
IGFET N ₁₀ is "on" because it is "igh" and the O ₀ potential is discharged from IGFET N ₁₀ from 3.2 ^V to 0 ^{V. In} the process, when O ₀ becomes 3.0 ^V or less, Vcom is compared. "High" by the container
Changes to "Low".

Next, when the output data D is changed from "High" to "Low", the data signal A1 changes from "High" to "Low" and the IGFET N ₁₀ is changed to "of".
"becomes, B1 is" f "is IGFET P ₁₀ changes from" High "to" Low "becomes. At this time IGFET P ₁₂ is Vcom is" on "for a""data signal B2 at the" Low High off ". Output electrode O ₀
Is charged via IGFET P ₁₀ and rises from 0 ^V to 3 ^V. 3
^When it rises to ^V , the comparator output Vcom changes from 0 ^V to 5 ^V , and Bcom
1 changes from “Low” to “High” B2 changes from “High” to “Low”, IGFET P ₁₀ turns “off”, and IGFET P ₁₂ turns “on”. The output electrode O ₀ rises to (Vcc− | V _TP |) due to the effect of IGFET P ₁₁ , and if V _TP = −1.8 ^V , then O ₀ rises to 3.2 ^V and stabilizes.

Thus, using the comparator, the “High” level of the outgoing electrode O ₀
By controlling to 3.2 ^V , it became possible to minimize the amount of charge stored in O ₀ . Specifically C _L = 100
^In the case of ^PF , the conventional charge Q is 500 ^P coulomb (5 ^V × 10
^However , in the present invention, 320 ^P coulomb (3.2 ^V × 100 ^PF ) is sufficient, and the charge amount can be reduced to 64%. Therefore, if the g _m of IGFET N ₁₀ is the same, the discharge speed can be increased to about 64%, and if the discharge speed is the same, the discharge current can be suppressed to 64%.

In this way, using the comparator, the output terminal voltage "Hig
By providing a circuit that keeps the h "level to the minimum necessary, the speed can be increased, the discharge current can be reduced, the risk of noise generation can be reduced, and the speed can be stably increased.

FIG. 3 shows another embodiment of the present invention. In FIG.
The other embodiment of the present invention has the same circuit configuration as that of the above-mentioned embodiment, but in particular, by adding the P-channel IGFET P ₁₁ a, the output “High” voltage of the output electrode O ₀ becomes Vcc−2V. _TP 2.5 ^V
Therefore, there is an advantage that the speed can be further reduced. At this time, V _REF = 2.4 ^V.

〔The invention's effect〕

As described above, according to the present invention, the "Hi
The provision of the circuit for lowering the gh "voltage has the effect of realizing a high-speed operation semiconductor device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a timing chart used for explaining the circuit operation of the embodiment, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a circuit diagram showing the conventional semiconductor device, and FIG. 5 is a timing chart showing the conventional semiconductor device. P _{10 to} P ₁₄ , P ₁₁ a ... P-channel type insulated gate field effect transistor, N _{10 to} N ₁₃ ... N-channel type insulated gate field effect transistor, NO _{1 to} NO ₂ 3 input NO
R circuit, NO ₃ ~ NO ₅ ,, NO ₆ ,, NO ₇ ... Inverter circuit, NA ₁ ...
… NAND circuit.

Claims (1)

[Claims] 1. A first conductivity type first provided on a semiconductor substrate.
The source of the insulated gate field effect transistor is connected to the first power source, the gate is connected to the first data signal, and the drain is connected to the output electrode electrically connected to the external terminal, and the conductivity is opposite to that of the first conductivity type. Type second insulated gate field effect transistor having a source connected to a second power supply, a gate connected to a second data signal, and a drain connected to the output electrode, the semiconductor having an output transistor portion for driving an external terminal. In the device, a comparator that receives the voltage of the output electrode and compares it with a reference voltage, and a comparator that outputs a voltage of the output electrode higher than the reference voltage when the first insulated gate field effect transistor is "on" The output turns off the first insulated gate field effect transistor, and when the voltage of the output electrode becomes lower than the reference voltage, the first insulated gate field effect transistor turns off. a first logic circuit for controlling a first data signal set to "on", a third insulated gate field effect transistor having the first power source as a source and commonly connecting a drain and a gate, and a third data A fourth insulated gate field transistor having a signal connected to the gate, a drain connected to the output electrode and a source connected to the drain of the third insulated gate field transistor;
When the voltage of the output electrode becomes higher than the reference voltage when the insulated gate field effect transistor is turned on, the fourth insulated gate field effect transistor is turned on by the output of the comparator, and the voltage of the output electrode becomes the reference voltage. A semiconductor device comprising: a second logic circuit for controlling the third data signal for setting the fourth insulated gate field effect transistor to "off" when it becomes lower.