JPH0758757B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0758757B2 JPH0758757B2 JP1296909A JP29690989A JPH0758757B2 JP H0758757 B2 JPH0758757 B2 JP H0758757B2 JP 1296909 A JP1296909 A JP 1296909A JP 29690989 A JP29690989 A JP 29690989A JP H0758757 B2 JPH0758757 B2 JP H0758757B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- conductive path
- voltage
- power
- drive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は混成集積回路に関し、特にパワーMOSFETを備え
た混成集積回路に関する。The present invention relates to a hybrid integrated circuit, and more particularly to a hybrid integrated circuit including a power MOSFET.
（ロ）従来の技術 近年、省エネルギ、快適性の面より、誘導モータの可変
速下が強く要望されており、その手段として、インバー
タ装置の小型化、低価格化に非常な期待が寄せられてい
る。(B) Conventional technology In recent years, from the viewpoint of energy saving and comfort, there is a strong demand for variable speed induction motors, and as a means therefor, great expectations are placed on downsizing and cost reduction of inverter devices. ing.
以下に従来のインバータ装置の使用例を第４図，第５図
に示し説明する。An example of use of the conventional inverter device will be described below with reference to FIGS. 4 and 5.
第４図は、インバータ装置の基本構成図、第５図は、イ
ンバータ装置の駆動回路である。FIG. 4 is a basic configuration diagram of the inverter device, and FIG. 5 is a drive circuit of the inverter device.
第４図で、（11）はAC電源、（21）はAC電源の整流回
路、（31），（41），（51）は夫々前記整流回路（21）
と接続するＵ相,V相,W相の各相駆動回路である。そし
て、各相駆動回路（31），（41），（51）は、第１ベー
ス部（61）、第１パワートランジスタ（71）、第２ベー
ス部（81）、第２パワートランジスタ（91）により構成
される。（101）は周波数を設定する周波数設定部、（1
11）は前記周波数設定部（101）の信号を受け、各相の
第1,第２ベース部（61），（81）へ信号を出力する制御
回路部、（121）は各相駆動回路（31），（41），（5
1）に接続するモータである。第５図は、第４図中の駆
動回路（31），（41），（51）の具体例を示し、第４図
と同じ部分には同じ番号をつけ、重複する説明は省略す
る。（131）は第１ベース部（61）と第２ベース部（8
1）内の動力源の直流電源部、（141）は第１パワートラ
ンジスタ（71）をON−OFFする第１ベースドライブ部、
（151）は第２パワートランジスタ（91）をON−OFFする
第２ベースドライブ部、（161），（171）は第1,第２ベ
ースドライブ部（141），（151）への信号入力端子であ
る。In FIG. 4, (11) is an AC power source, (21) is an AC power source rectifier circuit, and (31), (41), and (51) are the rectifier circuits (21), respectively.
It is a U-phase, V-phase, and W-phase drive circuit connected to each. Each phase drive circuit (31), (41), (51) includes a first base portion (61), a first power transistor (71), a second base portion (81), and a second power transistor (91). It is composed of (101) is the frequency setting section for setting the frequency, (1
11) is a control circuit section that receives the signal from the frequency setting section (101) and outputs the signal to the first and second base sections (61) and (81) of each phase, and (121) is the phase drive circuit ( 31), (41), (5
It is a motor connected to 1). FIG. 5 shows a specific example of the drive circuits (31), (41) and (51) in FIG. 4, the same parts as in FIG. (131) is the first base portion (61) and the second base portion (8
1) DC power source part of power source, (141) first base drive part for turning on / off the first power transistor (71),
(151) is a second base drive section for turning on / off the second power transistor (91), and (161) and (171) are signal input terminals to the first and second base drive sections (141) and (151). Is.
以上の構成によれば、第４図，第５図より周波数設定部
（101）で周波数を設定すれば、制御回路部（111）は、
前記設定信号に基づき、電気角で120°の位相間隔で、
U,V,Wの各相駆動回路（31），（41），（51）の第1,第
２ベース部（61），（81）へ夫々のパワートランジスタ
（71），（91）を交互にON−OFFする信号を出力する。
即ち第1,第２ベース部（61），（81）では、第1,第２ベ
ースドライブ部（141），（151）の信号入力端子（16
1），（171）で信号を受け、各々の直流電源部（131）
によりパワートランジスタ（71），（91）を交互にON−
OFFし、整流回路（21）により供給される直流電圧を等
価的に３相交流に変換し、モータ（121）の運転を行
う。According to the above configuration, if the frequency is set by the frequency setting unit (101) from FIGS. 4 and 5, the control circuit unit (111) becomes
Based on the setting signal, at a phase interval of 120 ° in electrical angle,
The power transistors (71) and (91) are alternately arranged to the first and second base parts (61) and (81) of the U, V and W phase drive circuits (31), (41) and (51). The signal that turns on and off is output to.
That is, in the first and second base parts (61) and (81), the signal input terminals (16) of the first and second base drive parts (141) and (151) are connected.
1), (171) receives the signal, each DC power supply unit (131)
Turns on the power transistors (71) and (91) alternately-
The power is turned off, the DC voltage supplied by the rectifier circuit (21) is equivalently converted into a three-phase AC, and the motor (121) is operated.
以上に詳述したパワートランジスタを用いたインバータ
回路は主に低速用のモータを駆動する場合に用いられ
る。高速用を必要とする場合にはパワーMOSFETを用いた
インバータ回路が一般的に使用される。The inverter circuit using the power transistor described in detail above is mainly used for driving a low speed motor. When high speed operation is required, an inverter circuit using a power MOSFET is generally used.
第６図はパワーMOSFETを用いた場合の基本構成図であ
る。パワーMOSFETを用いたとしても基本的動作は上述し
たパワートランジスタ用のインバータ回路と略同一のた
め省略する。FIG. 6 is a basic configuration diagram when a power MOSFET is used. Even if the power MOSFET is used, the basic operation is substantially the same as that of the above-described inverter circuit for the power transistor, and therefore the description thereof will be omitted.
上述したインバータ回路を混成集積回路に集積化する場
合、従来例では二枚の絶縁性金属基板を用いて対応して
いた。即ち、一方の基板にパワートランジスタあるいは
パワーMOSFET等を有したパワー用回路を形成し、他方の
基板に駆動回路および保護回路等の小信号用回路を形成
して夫々の回路を二枚の基板上に配置して集積化を行っ
ていた（第７図参照）。In the case of integrating the above-described inverter circuit into a hybrid integrated circuit, two insulating metal substrates are used in the conventional example. That is, a power circuit having a power transistor or a power MOSFET is formed on one substrate, and a small signal circuit such as a drive circuit and a protection circuit is formed on the other substrate, and each circuit is formed on two substrates. It was placed in the area for integration (see FIG. 7).
（ハ）発明が解決しようとする課題 同一基板表面上にパワー用回路および小信号用回路を形
成すると以下に示す如き問題があった。(C) Problems to be Solved by the Invention When the power circuit and the small signal circuit are formed on the same substrate surface, there are the following problems.
第８図は小信号用回路のパワー素子（MOSFET）を駆動さ
せる１つの駆動回路を示したパターン図である。かかる
従来の駆動回路は複数のディスクリート部品あるいは半
導体チップを接続して構成されるのが一般的である。イ
ンバータ回路において、述べるまでもないが第８図に示
したパターンが６個配置されている。FIG. 8 is a pattern diagram showing one driving circuit for driving the power element (MOSFET) of the small signal circuit. Such a conventional drive circuit is generally constructed by connecting a plurality of discrete components or semiconductor chips. Needless to say, six patterns shown in FIG. 8 are arranged in the inverter circuit.
駆動回路を形成するパターン配線下の構造は金属基板、
絶縁層、導体となっているために寄生容量が発生する。
この寄生容量は駆動回路部分のパターン配線が長くなる
とその容量が大きくなり、例えば、インバータ回路下側
アームのパワーMOSFETを駆動させると一対のもう一方の
上側アームのパワーMOSFETが寄生容量によって誤動作す
る。その結果、短絡電流が流れパワーMOSFETが破壊する
という不具合がある。The structure under the pattern wiring that forms the drive circuit is a metal substrate,
Since it is an insulating layer and a conductor, parasitic capacitance occurs.
This parasitic capacitance increases as the pattern wiring of the drive circuit portion becomes longer. For example, when the power MOSFET of the lower arm of the inverter circuit is driven, the power MOSFET of the other upper arm of the pair malfunctions due to the parasitic capacitance. As a result, there is a problem that a short-circuit current flows and the power MOSFET is destroyed.
（ニ）課題を解決するための手段 本発明は上述した課題に鑑みて為されたものであり、電
圧駆動型素子に出力信号を供給する駆動回路は１つの半
導体チップ上に集積化され、その半導体チップと導電路
を接続したことを特徴としている。(D) Means for Solving the Problems The present invention has been made in view of the above problems, and a drive circuit that supplies an output signal to a voltage-driven element is integrated on one semiconductor chip, The feature is that the semiconductor chip and the conductive path are connected.
（ホ）作用 この様に本発明に依れば電圧駆動型素子をスイッチング
させる複数の回路素子より構成された駆動回路を１つの
半導体チップ上に集積化することにより、駆動回路内で
のパターン引き回し線を著しく少なくすることができ
る。その結果、パターン配線下の寄生容量を著しく減少
させることができる。(E) Action As described above, according to the present invention, by integrating the drive circuit composed of a plurality of circuit elements for switching the voltage drive type element on one semiconductor chip, the pattern routing in the drive circuit is achieved. The lines can be significantly reduced. As a result, the parasitic capacitance under the pattern wiring can be significantly reduced.
また、駆動回路を半導体チップ上に集積化することで従
来と比べ駆動回路部分の面積が著しく小さくなり混成集
積回路の小型化が行える。Further, by integrating the drive circuit on the semiconductor chip, the area of the drive circuit portion is remarkably reduced as compared with the prior art, and the hybrid integrated circuit can be downsized.
（ヘ）実施例 以下に第１図および第２図に示した図面に基づいて本発
明を詳細に説明する。(F) Embodiments The present invention will be described in detail below with reference to the drawings shown in FIGS. 1 and 2.
第１図は本発明を示す混成集積回路の平面図であり、第
２図は第１図のＩ−Ｉ断面図である。1 is a plan view of a hybrid integrated circuit showing the present invention, and FIG. 2 is a sectional view taken along the line I--I of FIG.
第１図および第２図の如く、本発明の混成集積回路
（１）は金属基板（２）と、基板（２）上に絶縁体
（６）を介して形成された導電路（３）と、導電路
（３）の所定位置に実装された電圧駆動型素子（４）お
よび素子（４）をスイッチングさせる駆動回路（５）と
から構成される。As shown in FIGS. 1 and 2, the hybrid integrated circuit (1) of the present invention comprises a metal substrate (2) and a conductive path (3) formed on the substrate (2) via an insulator (6). , A voltage drive type element (4) mounted at a predetermined position of the conductive path (3) and a drive circuit (5) for switching the element (4).
金属基板（２）は鉄、銅、あるいはアルミニウム等の金
属を用いることができるが本実施例ではアルミニウム基
板を用いるものとする。本実施例で用いるアルミニウム
基板表面には陽極酸化技術によって酸化アルミニウム膜
が形成され絶縁処理が行われる。The metal substrate (2) can be made of a metal such as iron, copper, or aluminum, but in this embodiment, an aluminum substrate is used. An aluminum oxide film is formed on the surface of the aluminum substrate used in this embodiment by an anodic oxidation technique, and insulation treatment is performed.
その基板（２）の一主面上には絶縁体（６）を介して所
望形状の導電路（３）が形成される。A conductive path (3) having a desired shape is formed on one main surface of the substrate (2) through an insulator (6).
絶縁層（６）はエポキシあるいはポリイミド樹脂等の樹
脂薄層あるいはセラミック等の板材が用いられる。本実
施例ではエポキシ樹脂薄層を用いるものとしその薄層に
は銅箔が貼着されている。銅箔を所定のパターンにエッ
チングすることにより所望形状の導電路（３）が形成さ
れる。導電路（３）は印刷によって形成できることはい
うまでもない。As the insulating layer (6), a resin thin layer such as epoxy or polyimide resin or a plate material such as ceramic is used. In this embodiment, an epoxy resin thin layer is used, and a copper foil is attached to the thin layer. By etching the copper foil into a predetermined pattern, the conductive path (3) having a desired shape is formed. It goes without saying that the conductive path (3) can be formed by printing.
導電路（３）はパワー部分に用いられるもの（3a）と小
信号部分に用いられる（3b）とが同一基板（２）上に形
成されることになる。更に述べると、パワー系の導電路
（3a）は基板（２）の略中間で区画される領域に形成さ
れ、基板（２）の一側辺にはパワー用の複数の固着パッ
ドが形成される。小信号系の導電路（3b）はパワー系の
導電路（3a）と２分する様に形成されその延在する先端
部には小信号用の複数の固着パッドが形成される。すな
わち、パワー用および小信号用の固着パッドはそれぞれ
基板（２）の相対向する側辺周端部に形成されることに
なり、上記したように小信号用回路とパワー用回路とは
基板（２）の略中間領域で区画されることになる。The conductive path (3) used for the power portion (3a) and the small signal portion (3b) are formed on the same substrate (2). More specifically, the power system conductive path (3a) is formed in a region defined approximately in the middle of the substrate (2), and a plurality of fixing pads for power are formed on one side of the substrate (2). . The small signal system conductive path (3b) is formed so as to be divided into two parts with the power system conductive path (3a), and a plurality of fixed pads for small signals are formed at the extending tip portion thereof. That is, the fixing pads for power and small signals are respectively formed at the peripheral side edge portions of the substrate (2) which face each other, and as described above, the small signal circuit and the power circuit are formed on the substrate ( It will be partitioned in the substantially intermediate region of 2).
パワー系の導電路（3a）上の所定位置には複数の電圧駆
動型素子（４）が半田によって固着されている。電圧駆
動型素子（４）としては、例えばパワーMOSFET、IGBT、
BiMOS等の素子を用いることができるが本実施例ではパ
ワーMOSFETを用いるものとする（以下電圧駆動型素子
（４）をパワーMOSFETという）。各パワーMOSFET（４）
はブリッジ接続なる様に配置される。A plurality of voltage-driven elements (4) are fixed by soldering to predetermined positions on the power system conductive path (3a). As the voltage drive type element (4), for example, power MOSFET, IGBT,
A device such as a BiMOS can be used, but a power MOSFET is used in this embodiment (hereinafter, the voltage drive device (4) is referred to as a power MOSFET). Each power MOSFET (4)
Are arranged in a bridge connection.
小信号系の導電路（3b）上の所定位置には各パワーMOSF
ET（４）をスイッチングさせる駆動回路（５）およびコ
ンデンサー、チップ抵抗等のチップ部品が固着されてい
る。Each power MOSF is located at a specified position on the small signal system conductive path (3b).
A drive circuit (5) for switching the ET (4) and chip parts such as a capacitor and a chip resistor are fixed.
本発明の特徴とするところはパワーMOSFET（４）をスイ
ッチングさせる駆動回路（５）にある。即ち、従来構造
の駆動回路はトランジスタ、チップ抵抗、チップコンデ
ンサー等の複数の回路素子を用いて所望の導電路の引き
回し線によって接続することによって形成されていた。
しかし、本発明の駆動回路（５）は従来の駆動回路を構
成する回路が半導体チップ上に集積化されている。The feature of the present invention resides in the drive circuit (5) for switching the power MOSFET (4). That is, a drive circuit having a conventional structure has been formed by connecting a plurality of circuit elements such as a transistor, a chip resistor, and a chip capacitor by a wiring line of a desired conductive path.
However, in the drive circuit (5) of the present invention, the circuits forming the conventional drive circuit are integrated on the semiconductor chip.
第３図は半導体チップ上に形成された駆動回路（５）を
示すブロック図である。第３図の如く、所定の入力信号
に基づいて出力回路を駆動させる前段回路と、パワーMO
SFET（４）をスイッチングさせる出力回路と、前段回路
および出力回路に所定の安定した電流を供給する定電流
回路と、パワーMOSFET（４）の飽和電圧が過電流によっ
て上昇したときの異常電圧を検出する電圧検出回路とか
ら構成されている。FIG. 3 is a block diagram showing a drive circuit (5) formed on a semiconductor chip. As shown in FIG. 3, a front-end circuit that drives an output circuit based on a predetermined input signal, and a power MO
An output circuit that switches the SFET (4), a constant current circuit that supplies a predetermined stable current to the preceding circuit and the output circuit, and an abnormal voltage when the saturation voltage of the power MOSFET (4) rises due to overcurrent And a voltage detection circuit that operates.
駆動回路（５）はブリッジ接続された各パワーMOSFET
（４）と隣接して配置され夫々の導電路（３）にボンデ
ィングして接続され所定の出力を有したインバータ用の
混成集積回路を実現することができる。上述した実施例
では、インバータ回路を用いて説明したが、本発明はイ
ンバータ回路に限定れるものではなく、アクティブ・フ
ィルタ回路等パワーMOSFET等の電圧駆動型のスイッチン
グ素子を用いるハイブリッドICに応用できることは説明
するまでもない。The drive circuit (5) is each power MOSFET connected in bridge
It is possible to realize a hybrid integrated circuit for an inverter, which is arranged adjacent to (4) and is bonded and connected to each conductive path (3) and has a predetermined output. In the embodiments described above, the explanation was given using the inverter circuit, but the present invention is not limited to the inverter circuit, and it can be applied to a hybrid IC using a voltage drive type switching element such as a power MOSFET such as an active filter circuit. Needless to say.
斯る本発明に依れば、各パワーMOSFET（４）を駆動させ
る駆動回路（５）を半導体チップ上に集積化することに
より、従来の駆動回路は複数の引き回し線のパターンを
必要としていたのを不要とすることができる。この結
果、従来では引き回し線のパターン部分で寄生容量が発
生していたが、本発明では駆動回路（５）自体がチップ
化されているために寄生容量を著しく低減することがで
きる。According to the present invention, by integrating the drive circuit (5) for driving each power MOSFET (4) on the semiconductor chip, the conventional drive circuit requires a plurality of routing line patterns. Can be eliminated. As a result, conventionally, parasitic capacitance is generated in the pattern portion of the routing line, but in the present invention, since the drive circuit (5) itself is made into a chip, the parasitic capacitance can be significantly reduced.
また、駆動回路（５）がチップ上に集積化されているた
めに駆動回路（５）の面積は従来構造と比べ著しく小さ
くなるために混成集積回路の小型化が行える。さらに、
小信号用の固着パッドとパワー用の固着パッドとが基板
（２）の相対向する側辺に設けられているため基板
（２）上の有効面を最大限利用することができる。Further, since the drive circuit (5) is integrated on the chip, the area of the drive circuit (5) is significantly smaller than that of the conventional structure, so that the hybrid integrated circuit can be downsized. further,
Since the small signal sticking pad and the power sticking pad are provided on opposite sides of the substrate (2), the effective surface of the substrate (2) can be utilized to the maximum extent.
（ト）発明の効果 以上に詳述した様に本発明に依れば、各パワーMOSFET
（４）を駆動させる駆動回路（５）を半導体チップ上に
集積化することにより、従来の駆動回路では複数の引き
回し線のパターンを必要としていたのを本発明では不要
とすることができる。この結果、従来では引き回し線の
パターン部分で寄生容量が発生していたが、本発明では
駆動回路（５）自体がチップ化されているために寄生容
量を著しく低減することが可能となり、パワーMOSFET
（４）のスイッチング時のノイズによる容量変化による
電位変化を最小限に抑えることができ他のパワーMOSFET
の異常動作を防止することが可能となる。(G) Effect of the Invention As described in detail above, according to the present invention, each power MOSFET
By integrating the drive circuit (5) for driving (4) on the semiconductor chip, it is possible to eliminate the need for a plurality of routing patterns in the conventional drive circuit in the present invention. As a result, in the past, the parasitic capacitance was generated in the pattern portion of the routing line, but in the present invention, since the drive circuit (5) itself is made into a chip, it is possible to significantly reduce the parasitic capacitance and the power MOSFET.
(4) It is possible to minimize potential changes due to capacitance changes due to noise during switching, and other power MOSFETs
It is possible to prevent the abnormal operation of.
また、本発明では駆動回路（５）が半導体チップ上に集
積化されているために、従来より駆動回路自体の面積が
著しく小さくなるために混成集積回路の小型化に大きく
寄与できる利点を有する。さらに本発明では、小信号用
の固着パッドとパワー用の固着パッドとが基板の相対向
する側辺に設けられているために基板上の実装有効面積
を拡大することができる。その結果、小型の基板であっ
ても最大限の高密度実装が可能となる。Further, in the present invention, since the drive circuit (5) is integrated on the semiconductor chip, the area of the drive circuit itself is remarkably smaller than that of the conventional one, which has an advantage that it can greatly contribute to the miniaturization of the hybrid integrated circuit. Further, according to the present invention, since the small signal fixing pad and the power fixing pad are provided on the opposite sides of the substrate, the mounting effective area on the substrate can be increased. As a result, the maximum high-density mounting is possible even with a small board.
第１図は本発明の混成集積回路を示す平面図、第２図は
第１図のＩ−Ｉ断面図、第３図は駆動回路を示すブロッ
ク図、第４図はインバータ装置を示す基本構成図、第５
図は同インバータ装置の駆動回路図、第６図はMOSFETを
用いた場合のインバータ装置を示す基本構成図、第７図
は従来の混成集積回路を示す断面図および第８図は従来
の駆動回路を示す平面図である。 （１）……混成集積回路、（２）……金属基板、（３）
……導電路、（４）……パワーMOSFET、（５）……駆動
回路、（６）……絶縁体。1 is a plan view showing a hybrid integrated circuit of the present invention, FIG. 2 is a sectional view taken along the line I--I of FIG. 1, FIG. 3 is a block diagram showing a drive circuit, and FIG. 4 is a basic configuration showing an inverter device. Figure, fifth
FIG. 6 is a drive circuit diagram of the same inverter device, FIG. 6 is a basic configuration diagram showing an inverter device using a MOSFET, FIG. 7 is a sectional view showing a conventional hybrid integrated circuit, and FIG. 8 is a conventional drive circuit. FIG. (1) ... hybrid integrated circuit, (2) ... metal substrate, (3)
...... Conductive path, (4) …… Power MOSFET, (5) …… Drive circuit, (6) …… Insulator.
Claims (2)
導電路と、 前記導電路上の所定位置に接続された複数の回路素子
と、 所定の出力信号に基づいてスイッチングする電圧駆動型
素子とを備えた混成集積回路において、 前記電圧駆動型素子に前記出力信号を供給する駆動回路
は１つの半導体チップ上に集積化され、前記導電路と接
続されたことを特徴とする混成集積回路。1. A metal substrate, a conductive path of a desired shape formed on the metal substrate via an insulating layer, a plurality of circuit elements connected to predetermined positions on the conductive path, and a predetermined output signal. In a hybrid integrated circuit including a voltage-driven element that switches based on the driving circuit, the drive circuit that supplies the output signal to the voltage-driven element is integrated on one semiconductor chip and connected to the conductive path. A hybrid integrated circuit characterized by.
導電路と、 前記導電路上の所定位置に接続された複数の回路素子お
よび所定の出力信号に基づいてスイッチングする電圧駆
動型素子とを備えた混成集積回路において、 前記電圧駆動型素子に出力信号を供給する駆動回路は入
力信号に基づいて所定の出力信号を出力する前段回路と
前記出力信号に基づいて前記電圧駆動型素子をスイッチ
ングさせる出力回路と前記前段回路および出力回路に安
定した電流を供給する定電圧回路を有し、且つ、１つの
半導体チップ上に集積化され前記導電路と接続されたこ
とを特徴とする混成集積回路。2. A metal substrate, a conductive path of a desired shape formed on the metal substrate via an insulating layer, a plurality of circuit elements connected to predetermined positions on the conductive path, and a predetermined output signal. In a hybrid integrated circuit including a voltage-driven element that switches according to an input signal, a drive circuit that supplies an output signal to the voltage-driven element is based on the output signal and a pre-stage circuit that outputs a predetermined output signal based on the input signal. And an output circuit for switching the voltage-driven element and a constant voltage circuit for supplying a stable current to the pre-stage circuit and the output circuit, and integrated on one semiconductor chip and connected to the conductive path. A hybrid integrated circuit characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296909A JPH0758757B2 (en) | 1989-11-15 | 1989-11-15 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296909A JPH0758757B2 (en) | 1989-11-15 | 1989-11-15 | Hybrid integrated circuit |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8125807A Division JP2614599B2 (en) | 1996-05-21 | 1996-05-21 | Hybrid integrated circuit |
| JP8125806A Division JP2902993B2 (en) | 1996-05-21 | 1996-05-21 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03156964A JPH03156964A (en) | 1991-07-04 |
| JPH0758757B2 true JPH0758757B2 (en) | 1995-06-21 |
Family
ID=17839736
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1296909A Expired - Fee Related JPH0758757B2 (en) | 1989-11-15 | 1989-11-15 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758757B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2584128Y2 (en) * | 1993-04-09 | 1998-10-30 | 東洋電機製造株式会社 | Printed wiring board of inverter device for large current |
| JP4634962B2 (en) * | 2006-04-28 | 2011-02-16 | パナソニック株式会社 | Semiconductor device |
| KR101109359B1 (en) * | 2010-06-14 | 2012-01-31 | 삼성전기주식회사 | Heat-radiating substrate and manufacturing method thereof |
| JP6577146B1 (en) * | 2018-01-26 | 2019-09-18 | 新電元工業株式会社 | Electronic module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0817581B2 (en) * | 1988-04-15 | 1996-02-21 | 三洋電機株式会社 | Power inverter drive circuit and hybrid integrated circuit in which it is integrated |
-
1989
- 1989-11-15 JP JP1296909A patent/JPH0758757B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03156964A (en) | 1991-07-04 |
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