JPH0758728B2 - Pattern length measurement method in semiconductor device manufacturing - Google Patents

Pattern length measurement method in semiconductor device manufacturing

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Publication number
JPH0758728B2
JPH0758728B2 JP63194471A JP19447188A JPH0758728B2 JP H0758728 B2 JPH0758728 B2 JP H0758728B2 JP 63194471 A JP63194471 A JP 63194471A JP 19447188 A JP19447188 A JP 19447188A JP H0758728 B2 JPH0758728 B2 JP H0758728B2
Authority
JP
Japan
Prior art keywords
metal pattern
insulating film
pattern body
metal
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63194471A
Other languages
Japanese (ja)
Other versions
JPH0244748A (en
Inventor
祐子 関野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP63194471A priority Critical patent/JPH0758728B2/en
Publication of JPH0244748A publication Critical patent/JPH0244748A/en
Publication of JPH0758728B2 publication Critical patent/JPH0758728B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は半導体素子の製造におけるパターン測長方法
に係り、特に絶縁膜下に形成された金属パターン体の測
長方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern length measuring method in manufacturing a semiconductor device, and more particularly to a length measuring method of a metal pattern body formed under an insulating film.

(従来の技術) 従来、半導体素子の製造における金属パターン体の測長
には、光学顕微鏡もしくは走査電子顕微鏡が用いられて
きた。
(Prior Art) Conventionally, an optical microscope or a scanning electron microscope has been used for measuring the length of a metal pattern body in the manufacture of a semiconductor element.

光学顕微鏡においては、数μm以下のSiO2またはSiN絶
縁膜を透過して金属パターン体を観察することが可能で
あった。そのため、測長すべき金属パターン体を形成し
た後、集積回路(IC)作成終了までの任意の工程におい
て、パターン長を測定してきた。顕微鏡の倍率は主に約
2000倍にしてきた。
In the optical microscope, it was possible to observe the metal pattern through the SiO 2 or SiN insulating film of several μm or less. Therefore, the pattern length has been measured in an arbitrary process after forming the metal pattern body to be measured and ending the production of the integrated circuit (IC). The magnification of the microscope is mainly about
2000 times.

これに対して、走査電子顕微鏡においては、絶縁膜を透
過して金属パターン体を観察することが困難であった。
そのため、通常は、金属パターン体を形成した直後に、
第2図に示すように基板1および金属パターン体2が露
出した状態で測長してきた。また、金属パターン体上に
絶縁膜を形成した後の場合は、該絶縁膜の所定領域を除
去して金属パターン体を露出させて測長してきた。いず
れも顕微鏡の倍率は数1000倍から20000倍にしてきた。
On the other hand, in the scanning electron microscope, it was difficult to observe the metal pattern through the insulating film.
Therefore, usually, immediately after forming the metal pattern body,
As shown in FIG. 2, the length was measured with the substrate 1 and the metal pattern body 2 exposed. In addition, after forming an insulating film on the metal pattern body, a predetermined region of the insulating film is removed to expose the metal pattern body for length measurement. In both cases, the microscope magnification has been increased from several thousand times to 20,000 times.

(発明が解決しようとする課題) しかるに、前者の光学顕微鏡観察では、高倍率像を得る
ことが困難であり、測長の精度が低いという問題点があ
った。
(Problems to be Solved by the Invention) However, in the former optical microscope observation, it was difficult to obtain a high-magnification image, and there was a problem that the accuracy of length measurement was low.

これに対して、後者の走査電子顕微鏡観察では高倍率像
は得られるが、絶縁膜形成前の観察法においては、測定
雰囲気中のゴミ、支持台の汚れによる基板の素子形成領
域部の汚染によりICの性能または歩留りを低下させる問
題点があった。これに対して、絶縁膜形成後、該絶縁膜
の所定領域を除去して行う走査電子顕微鏡観察法におい
ては、基板の汚染による問題は生じないものの、測定金
属パターン体上の所定領域の絶縁膜を除去する必要があ
り、その際同時に測定すべき金属パターン体もエッチン
グされるので、金属パターン体の消失もしくは解像度の
低下という問題点があった。また、絶縁膜の除去に、該
絶縁膜のみを選択的に除去するエッチング法を用いるこ
ともできるが、この選択エッチングにはウェットエッチ
ングが用いられ、エッチング液の浸透が生じるため、IC
の配線不良を発生させることがあった。
On the other hand, although a high-magnification image can be obtained by the latter scanning electron microscope observation, in the observation method before forming the insulating film, dust in the measurement atmosphere and contamination of the element formation region of the substrate due to contamination of the support stand There is a problem that the performance or yield of IC is reduced. On the other hand, in the scanning electron microscope observation method in which a predetermined region of the insulating film is removed after forming the insulating film, the problem due to contamination of the substrate does not occur, but the insulating film in the predetermined region on the measurement metal pattern body However, since the metal pattern body to be measured is also etched at the same time, there is a problem that the metal pattern body disappears or the resolution decreases. Further, an etching method for selectively removing only the insulating film can be used for removing the insulating film, but wet etching is used for this selective etching, which causes penetration of an etching solution.
Sometimes caused a wiring failure.

この発明は、以上述べた低精度、基板の汚染、測定金属
パターン体の消失または解像度低下および配線不良の問
題点を除去し、IC作成に悪影響を与えずに金属パターン
体の測長を高精度にしかも簡便に行う方法を提供するこ
とを目的とする。
The present invention eliminates the problems of low accuracy, substrate contamination, disappearance of measurement metal pattern body or resolution degradation and wiring failure described above, and highly accurate measurement of metal pattern body without adversely affecting IC fabrication. Moreover, it is an object of the present invention to provide a method that is simple and easy.

(課題を解決するための手段) この発明では、基板上に第1の金属からなる金属パター
ン体を形成した後、絶縁膜とのエッチングの選択比の大
きい第2の金属からなる保護膜で前記金属パターン体を
被覆し、その上を含む前記基板上の全面に絶縁膜を形成
した後、該絶縁膜を前記保護膜上を含む所定領域で選択
的に除去し、該保護膜を露出させ、その後、露出した保
護膜を通して前記金属パターン体の測長を行う。
(Means for Solving the Problems) In the present invention, after forming a metal pattern body made of a first metal on a substrate, a protective film made of a second metal having a large etching selectivity with respect to an insulating film is used. After covering the metal pattern body and forming an insulating film on the entire surface of the substrate including the metal pattern body, the insulating film is selectively removed in a predetermined region including the protective film to expose the protective film, Then, the length of the metal pattern body is measured through the exposed protective film.

(作用) 上記の方法においては、基板上を絶縁膜で覆った上で金
属パターン体の測長を行っているので、基板は汚染され
ない。また、金属パターン体上の絶縁膜を除去した上で
測長を行っているので、走査電子顕微鏡を用いての測定
が可能となる。この時、金属パターン体は保護膜で覆わ
れているが、該保護膜は金属であり、保護膜を通しての
金属パターン体の測長が可能となる。また、保護膜は絶
縁膜とのエッチングの選択比の大きい金属から形成され
ており、このような保護膜で金属パターン体が覆われて
いると、絶縁膜の除去時、例え絶縁膜のエッチング法と
して、金属パターン体もエッチングする可能性のあるエ
ッチング法を用いても、金属パターン体がエッチングさ
れることはない。そのエッチング法としては反応性イオ
ンエッチング法などのドライエッチング法があり、ウェ
ットエッチングの場合と違ってエッチング液の浸透は生
じない。
(Operation) In the above method, since the length of the metal pattern body is measured after the substrate is covered with the insulating film, the substrate is not contaminated. Further, since the length measurement is performed after removing the insulating film on the metal pattern body, the measurement can be performed using a scanning electron microscope. At this time, the metal pattern body is covered with the protective film, but since the protective film is made of metal, the length of the metal pattern body can be measured through the protective film. Further, the protective film is formed of a metal having a large etching selection ratio with respect to the insulating film. When the metal pattern body is covered with such a protective film, when the insulating film is removed, for example, an insulating film etching method is used. As a result, even if an etching method that may also etch the metal pattern body is used, the metal pattern body is not etched. As the etching method, there is a dry etching method such as a reactive ion etching method, and unlike the case of wet etching, penetration of an etching solution does not occur.

(実施例) 以下この発明の一実施例を第1図を参照して説明する。
一実施例は、電界効果トランジスタの作成時、該トラン
ジスタのゲート電極と同一パターンの測長用金属パター
ン体を形成して、この金属パターン体から、電界効果ト
ランジスタのゲート電極の形成具合を観察する場合であ
る。第1図(a)〜(d)の各々においては、左側に断
面図、右側に平面図を示す。平面図は、断面図の右半分
の測長用金属パターン体部分のみの平面図である。
(Embodiment) An embodiment of the present invention will be described below with reference to FIG.
In one embodiment, when a field effect transistor is formed, a length-measuring metal pattern body having the same pattern as that of the gate electrode of the transistor is formed, and the formation of the gate electrode of the field effect transistor is observed from the metal pattern body. This is the case. In each of FIGS. 1A to 1D, a cross-sectional view is shown on the left side and a plan view is shown on the right side. The plan view is a plan view of only the metal pattern body portion for length measurement in the right half of the sectional view.

まず第1図(a)に示すように、半導体基板11上にタン
グステン(W)系金属を用いて電界効果トランジスタの
ゲート電極12を形成し、同時に同一金属により前記ゲー
ト電極12と同一パターンに測長用金属パターン体13を前
記基板11上に形成する。
First, as shown in FIG. 1A, a gate electrode 12 of a field effect transistor is formed on a semiconductor substrate 11 by using a tungsten (W) -based metal, and at the same time, the same metal and the same pattern as the gate electrode 12 are measured. A long metal pattern body 13 is formed on the substrate 11.

次に、第1図(b)に示すように電界効果トランジスタ
のソース・ドレイン領域14を基板11内に形成した後、そ
の上にAuGe/Ni/Auの金属を用いてオーミック電極15を形
成するが、この時同時に、測長用金属パターン体13側に
おいては、同金属からなる保護膜16を形成して、この保
護膜16で前記測長用金属パターン体13を覆うようにす
る。
Next, as shown in FIG. 1 (b), after forming the source / drain regions 14 of the field effect transistor in the substrate 11, an ohmic electrode 15 is formed thereon by using AuGe / Ni / Au metal. However, at the same time, a protective film 16 made of the same metal is formed on the length measuring metal pattern body 13 side, and the protective film 16 covers the length measuring metal pattern body 13.

その後、保護膜16上や電極12,15上などの全面を覆うよ
うに第1図(c)に示すように絶縁膜17を基板11上に形
成する。
After that, an insulating film 17 is formed on the substrate 11 so as to cover the entire surface of the protective film 16 and the electrodes 12 and 15 as shown in FIG.

その後、フッ素系ガスによる反応性イオンエッチングに
よって第1図(d)に示すように絶縁膜17の所定領域を
除去し、開口部18を形成し、前記保護膜16を露出させる
ようにする。この絶縁膜17の除去は、電界効果トランジ
スタの電極12,15上の絶縁膜16に配線形成用のスルーホ
ール19を開ける工程で同時に行われる。勿論、別々でも
よい。この絶縁膜17の除去時、前記フッ素ガスによる反
応性イオンエッチングによれば、ゲート電極金属(測長
用金属パターン体金属)はエッチングされるが、オーミ
ック電極金属(保護膜金属)はエッチングされないの
で、保護膜16で被覆された測長用金属パターン体13はエ
ッチングされず、当初の形状を保つ。
After that, a predetermined region of the insulating film 17 is removed by reactive ion etching using a fluorine-based gas, an opening 18 is formed, and the protective film 16 is exposed. The removal of the insulating film 17 is carried out at the same time as the step of forming a through hole 19 for forming a wiring in the insulating film 16 on the electrodes 12 and 15 of the field effect transistor. Of course, they may be separate. At the time of removing the insulating film 17, the gate electrode metal (metal for measuring length pattern metal) is etched by the reactive ion etching with the fluorine gas, but the ohmic electrode metal (metal for protective film) is not etched. The metal pattern body for length measurement 13 covered with the protective film 16 is not etched and retains its original shape.

しかる後、露出した保護膜16を通して走査電子顕微鏡に
より測長用金属パターン体13の測長(測長方向は第1図
(d)の矢印イ方向)を行い、その結果から、電界効果
トランジスタのゲート電極12の形成具合および形成長を
判断する。
After that, the length of the length-measuring metal pattern body 13 is measured by the scanning electron microscope through the exposed protective film 16 (the length-measuring direction is the direction of arrow A in FIG. 1 (d)). The formation condition and the formation length of the gate electrode 12 are judged.

なお、上記一実施例では、エッチング法として、フッ素
ガスによる反応性イオンエッチを用いたが、保護膜のエ
ッチング速度が充分小さい方法ならば、他のドライエッ
チング方法も使用可能である。
Although the reactive ion etching using fluorine gas is used as the etching method in the above-described embodiment, other dry etching methods can be used as long as the etching rate of the protective film is sufficiently low.

また、保護膜としてオーミック電極金属を用いたが、絶
縁膜とのエッチングの選択比が大きく、かつその下部に
形成されているパターン体の走査電子顕微鏡による観察
が可能な材料ならば他の金属でもよい。
Although the ohmic electrode metal is used as the protective film, other metals may be used as long as they have a large etching selection ratio to the insulating film and can observe the pattern body formed thereunder by a scanning electron microscope. Good.

さらに、上記一実施例は、電界効果トランジスタのゲー
ト電極の形成具合を判別するため、該ゲート電極と同一
の測長用金属パターン体を形成する場合であるが、この
発明はその他の場合にも勿論応用できる。
Further, in the above-mentioned one embodiment, in order to determine the formation condition of the gate electrode of the field effect transistor, the same metal pattern body for length measurement as the gate electrode is formed, but the present invention is also applicable to other cases. Of course it can be applied.

(発明の効果) 以上詳述したように、この発明の方法によれば、基板上
を絶縁膜で覆った上で金属パターン体の測長を行ってい
るので、基板の汚染を防止でき、かつ絶縁膜は金属パタ
ーン体上からは除去しているので走査電子顕微鏡を用い
ることができ、高精度の測長が可能となる。また、金属
パターン体上を保護膜で覆っているので、絶縁膜の除去
時、金属パターン体もエッチングする可能性あるエッチ
ング法、例えば反応性イオンエッチングを用いても金属
パターン体のエッチングを防止でき、金属パターン体の
消失あるいは解像度低下を防止できる。また、その結果
として絶縁膜のエッチング法として上述の反応性イオン
エッチングのようなドライエッチングを使用できるか
ら、ウェットエッチングを用いた時の問題点、すなわち
エッチング液の浸透、それによる配線不良の発生も解決
できる。このように、このは発明の方法によれば、IC作
成に悪影響を与えずに容易に高精度に金属パターン体の
測長が可能となり、ICの高性能化および歩留り向上が期
待できる。
(Effect of the Invention) As described in detail above, according to the method of the present invention, since the length of the metal pattern body is measured after the substrate is covered with the insulating film, contamination of the substrate can be prevented, and Since the insulating film is removed from the metal pattern body, a scanning electron microscope can be used, and highly accurate length measurement is possible. Further, since the metal pattern body is covered with the protective film, it is possible to prevent the metal pattern body from being etched even when using an etching method that may also etch the metal pattern body when removing the insulating film, such as reactive ion etching. It is possible to prevent disappearance of the metal pattern body or reduction of resolution. Further, as a result, since dry etching such as the above-described reactive ion etching can be used as an insulating film etching method, there is a problem when wet etching is used, that is, penetration of an etching solution and occurrence of wiring failure due to it. Solvable. As described above, according to the method of the present invention, it is possible to easily and accurately measure the length of the metal pattern body without adversely affecting the IC fabrication, and it can be expected that the performance and yield of the IC will be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図はこの発明の半導体素子の製造におけるパターン
測長方法の一実施例を示す断面図および平面図、第2図
は従来の金属パターン体の測長方法の一例を示す断面図
である。 11…半導体基板、13…測長用金属パターン体、16…保護
膜、17…絶縁膜、18…開口部。
FIG. 1 is a sectional view and a plan view showing an embodiment of a pattern length measuring method in the production of a semiconductor device of the present invention, and FIG. 2 is a sectional view showing an example of a conventional metal pattern body length measuring method. 11 ... Semiconductor substrate, 13 ... Metal pattern body for length measurement, 16 ... Protective film, 17 ... Insulating film, 18 ... Opening part.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】(a)基板上に第1の金属からなる金属パ
ターン体を形成した後、絶縁膜とのエッチングの選択比
の大きい第2の金属からなる保護膜で前記金属パターン
体を被覆し、 (b)その上を含む前記基板上の全面に絶縁膜を形成し
た後、 (c)該絶縁膜を前記保護膜上を含む所定領域で選択的
に除去し、該保護膜を露出させ、その後、 (d)露出した保護膜を通して前記金属パターン体の測
長を行うことを特徴とする半導体素子の製造におけるパ
ターン測長方法。
1. (a) After forming a metal pattern body made of a first metal on a substrate, the metal pattern body is covered with a protective film made of a second metal having a large etching selectivity with respect to an insulating film. And (b) after forming an insulating film over the entire surface of the substrate including the insulating film, (c) selectively removing the insulating film in a predetermined region including the protective film to expose the protective film. Then, (d) a pattern length measuring method in manufacturing a semiconductor device, wherein the length of the metal pattern body is measured through the exposed protective film.
JP63194471A 1988-08-05 1988-08-05 Pattern length measurement method in semiconductor device manufacturing Expired - Fee Related JPH0758728B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63194471A JPH0758728B2 (en) 1988-08-05 1988-08-05 Pattern length measurement method in semiconductor device manufacturing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63194471A JPH0758728B2 (en) 1988-08-05 1988-08-05 Pattern length measurement method in semiconductor device manufacturing

Publications (2)

Publication Number Publication Date
JPH0244748A JPH0244748A (en) 1990-02-14
JPH0758728B2 true JPH0758728B2 (en) 1995-06-21

Family

ID=16325101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63194471A Expired - Fee Related JPH0758728B2 (en) 1988-08-05 1988-08-05 Pattern length measurement method in semiconductor device manufacturing

Country Status (1)

Country Link
JP (1) JPH0758728B2 (en)

Also Published As

Publication number Publication date
JPH0244748A (en) 1990-02-14

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