JPH075849A - Flat display device - Google Patents

Abstract

PURPOSE:To provide a flat display device which can drive a high definition flat display panel with a display control device having a simple constitution. CONSTITUTION:A clock pulse made high frequency being integral multiple of a transfer clock of display data is supplied to a signal line driver and a scanning line driver which drives a flat display panel, and a display control device which supplies a timing signal and display data required for its operation, data taken in by this clock pulse is spatially separated and display data is supplied to plural signal line drivers. Since the number of operations in the display control device increases by a increment proportional to in creased clock frequency, data of same numbers are partially separated synchronizing with an input data and they can be outputted by plural drivers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat display device, and more particularly to a technique effective when used in a liquid crystal display panel having a TFT (thin film transistor) structure.

[0002]

2. Description of the Related Art Some conventional flat display devices using a TFT liquid crystal panel have a display size of 640 pixels × 480 lines (hereinafter, this is defined as medium definition) mainly for personal computers. As an example of such a medium-definition TFT liquid crystal panel, "TX26D51VC" sold by Hitachi, Ltd. corresponds to this.

In a display device using such a TFT liquid crystal panel, the interface with the host system such as the main body computer is in units of one pixel, that is, each of red (R), green (G) and blue (B). A set of data is transferred in a unit time. The structure of the display device using the TFT liquid crystal panel is as shown in FIG.
Drain (signal line) drivers are arranged above and below D, and the signal lines of the liquid crystal panel TFT-LCD are alternately connected to the drain drivers distributed above and below to drive them.
As such a drain driver, NEC Corporation
"ΜPD16423" and Texas
"TMS572 sold by Instruments"
16 ″ can be used. In this case, since the input width of the drain driver is 3 bits, the display control device receives the display input data from the main body computer twice and outputs it to the upper and lower drain drivers once. This is based on the display control device, while the amount of input data from the main computer is 3 dots,
This is because the amount of output data supplied to the drain driver is 6 dots in total in the vertical direction.

On the other hand, the T for workstations
The FT liquid crystal panel has high definition, for example, 1120 pixels × 780 lines. An example of such a high-definition TFT liquid crystal panel is "TX28D01VC" sold by Hitachi, Ltd. When a high-definition liquid crystal panel is driven as described above, if a frame frequency similar to that of the medium definition is secured, a high-speed clock and data must be processed in the display control device. When the frame frequency is set to 60 Hz on the screen of 1120 pixels × 780 lines as described above, the clock from the main body computer exceeds 60 MHz.

Furthermore, when the frame frequency is set to 80 Hz in order to perform multicolor (multi-gradation) processing by the FRC (frame rate control) system, the clock from the main computer actually exceeds 80 MHz. turn into. In such a display device, downsizing and thinning are difficult due to the problem of noise and the ability of the operating frequency of the semiconductor integrated circuit device. Therefore, in the above high-definition type, an interface of 4 pixels in parallel (4 × R, G, B = 12 dots) is used. As a result, the clock from the main computer can be suppressed to 20 MHz or less.

However, in the same structure as that of the medium definition as shown in FIG. 3, the output data amount of the drain driver is insufficient like 6 bits, and due to the insufficient processing speed on the drain driver side, as shown in FIG. Use a 2-clock configuration. In the display control device, the input data is read in advance and stored in the memory, and when the data is prepared, it is output to the drain driver.

[0007]

With the interface as described above, it is necessary to incorporate a memory in the display control device, and the circuit becomes complicated.
It cannot be configured by a semiconductor integrated circuit device such as a gate array, and must be formed by a complete custom LSI corresponding to the display specifications one-to-one.

An object of the present invention is to provide a flat display device capable of driving a high-definition flat display panel by a display control device having a simple structure. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, for the signal line driver and the scan driver that drive the flat display panel, it is an integral multiple of the display data transfer clock for the display control device that supplies the timing signals and display data necessary for its operation. The generated clock pulse is supplied, the data taken in by the clock pulse is spatially separated, and the display data is supplied to the signal line driver composed of the plurality.

[0010]

According to the above-mentioned means, the number of operations in the display control device increases as the clock frequency is increased.
The same number of data can be spatially separated and output to a plurality of drivers in synchronization with the input data.

[0011]

FIG. 5 shows a schematic block diagram of an embodiment of the liquid crystal display device according to the present invention. Although not particularly limited, the liquid crystal panel TF among the circuit blocks in FIG.
Each circuit block except the T-LCD is configured by a one-chip semiconductor integrated circuit device. Each of these semiconductor integrated circuit devices is formed on one semiconductor substrate such as single crystal silicon by a known MOS integrated circuit manufacturing technique.

Display data consisting of R, G and B and a control signal consisting of a clock, a display timing and a synchronizing signal are inputted to the display control device. This display control device constitutes an interface with the host computer and the main computer. The display control device is a liquid crystal panel TFT-LC.
Display data and a clock are supplied through a data bus provided corresponding to the drain drivers distributed above and below D.

As described above, the drain driver is composed of two parts which are distributed above and below the liquid crystal panel TFT-LCD. That is, the drain driver on the upper side drives the odd-numbered signal line electrodes extending in the vertical direction of the liquid crystal panel TFT-LCD, and the drain driver on the lower side drives the even-numbered signal line electrodes extending in the vertical direction of the liquid crystal panel TFT-LCD. Drive the signal line electrodes.

The gate (scan line) driver forms a selection signal for sequentially selecting scan line electrodes extending in the lateral direction of the liquid crystal panel TFT-LCD. The gate driver takes in a pulse input to the beginning of the frame as a start signal, sequentially shifts it by a shift register to form a selection signal, and outputs a drive signal for the scanning line electrode through an output buffer. In this embodiment, since the high-definition panel as described above has a large number of scanning lines, a plurality of gate drivers are connected in series to form the liquid crystal panel T.
The selection signal for the scanning line of the FT-LCD is formed.

Similarly, since the number of output terminals of the drain driver constituted by one semiconductor integrated circuit device is small with respect to the number of signal line electrodes of the liquid crystal display panel TFT-LCD, the drain drivers distributed vertically are provided. Also, a plurality of drain drivers are provided. These drain drivers are connected in parallel to the data bus, and clocks are also supplied in parallel. For fetching display data, one of the plurality of drain drivers corresponding to the display data is set to a selected state, the display data is sequentially fetched, and a drain driver of the next stage is selected by a fetch end signal. The state is set, and the display data that is subsequently input is taken in.

FIG. 2 is a timing chart for explaining the display data input method according to the present invention. In the same figure, in order to facilitate understanding of the invention, a conventional display data input method is also shown.

In the prior art, when the display timing signal is high level, input data is input in synchronization with the clock. That is, the display data of one unit is input in one cycle t _H of the clock. On the other hand, according to the present invention, the clock supplied from the host system such as the main body computer has a frequency twice as high as the transfer frequency of the input data. That is, in the present invention, one unit of display data is input in two clock cycles t _H.
With this configuration, the display data transfer rate remains the same as before, but the display data is input only once in every two clock cycles t _H , whereas the display control device as an interface does not receive the display data twice. You can take action.

FIG. 1 is a timing chart for explaining the display data fetching operation and the output operation by the interface according to the present invention. The clock, display timing signal, and input data are supplied from the main body computer or the like. The main body computer or the like supplies a clock having a frequency twice as high as the display data transfer rate as described above.

When the display timing signal is set to the high level, the display operation is validated and input to the input data for display in synchronization therewith. When one pixel is composed of 3 bits consisting of R, G, and B in order to enable high-definition driving as described above, this input data is a, b, c and d in one transfer. Four pixels are input.

In the display in which the four pixels are fetched in this way, the pixels a and b are output from the output buses 1 and 2 in synchronization with the fetching of input data of the next four pixels (e to h). Is output. These output buses 1 and 2 are shown in FIG.
It corresponds to the drain driver assigned to the upper side and the drain driver assigned to the lower side. In this way, the signals a and b output from the output bus are taken in by the respective drain drivers in synchronization with the clock. Then, in the latter half of the clock, the pixels c and d are output from the output buses 1 and 2 and taken into the respective drain drivers.

In this embodiment, as described above, the display data consisting of 12 bits is inputted at the same time, and the display data fetched in two times corresponding to the output buses 1 and 2 by a half cycle of the one cycle. Data is divided into 6 bits and processed twice. As a result, the display control device can perform 12-bit output with respect to 12-bit input.
As a result, since the display control device does not need to have a special logic configuration or a built-in memory, it can be configured by a semiconductor integrated circuit device such as a gate array, etc., and the development of a display control device corresponding to various display specifications Time and cost can be significantly reduced. In this way, it is possible to obtain a display control device of a small amount and a large variety of products corresponding to various display specifications at low cost.

By adopting the above configuration, the bus configuration for the drain driver can be a simple bus configuration similar to that shown in FIG. Correspondingly,
Clock processing and signal processing in the display control device can also be simplified.

The operation and effect obtained from the above embodiment are as follows. That is, (1) An integer for the transfer clock of the display data to the display control device that supplies the timing signal and the display data necessary for the operation to the signal line driver and the scan driver that drive the flat display panel. A doubled clock pulse is supplied, the data taken in by this clock pulse is spatially separated, and the display data is supplied to the signal line driver composed of the plurality.
With this configuration, since the number of operations in the display control device increases as the clock frequency increases, the same number of data can be spatially separated and output to multiple drivers in synchronization with the input data. The effect of being able to be obtained is obtained.

(2) According to the above (1), since the display control device does not need to have a special logical configuration or a built-in memory, it can be configured by a semiconductor integrated circuit device such as a gate array, and various display types can be provided. The effect is that the development time and cost of the display control device corresponding to the specifications can be significantly reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, if the timing specifications with the main computer are limited,
The display timing signal can be omitted.

Further, with respect to the transfer frequency of the input data,
If a clock with a triple frequency is used, the display data for 6 pixels is input at one time, and the data is output to the drain driver in three times for each input data. Data for 6 pixels can be processed. As described above, various embodiments can be adopted by combining the configurations of the output bus with respect to the clock frequency drain driver.

The flat display panel used in the flat display device according to the present invention may be a liquid crystal panel TFT-LCD or any other plasma display capable of being driven by a similar driving method. The present invention can be widely used for flat display panels.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for the signal line driver and the scan driver that drive the flat display panel, it is an integral multiple of the display data transfer clock for the display control device that supplies the timing signals and display data necessary for its operation. By supplying the clock pulse generated by the clock pulse and spatially separating the data taken in by the clock pulse and supplying the display data to the signal line driver composed of the plurality of data, the same number of data is synchronized with the input data. Data can be spatially separated and output to multiple drivers.

[Brief description of drawings]

FIG. 1 is a timing chart for explaining a display data fetching operation and an output operation thereof by an interface according to the present invention.

FIG. 2 is a timing diagram for explaining a display data input method according to the present invention.

FIG. 3 is a schematic block diagram showing an example of a conventional medium-definition liquid crystal display device.

FIG. 4 is a schematic block diagram showing an example of a conventional liquid crystal display device.

FIG. 5 is a block diagram showing an embodiment of a liquid crystal display device according to the present invention.

[Explanation of symbols]

 TFT-LCD: Liquid crystal panel.

Claims (2)

[Claims] 1. A flat display panel, a signal line driver configured to supply a drive signal to a signal line of the flat display panel, a scan driver supplying a selection signal to a scan line of the flat display panel, and the signal. For line and scan drivers,
A display control device for supplying a timing signal and display data necessary for the operation is provided, and a clock pulse raised to an integral multiple of the display data transfer clock is supplied to the display control device. A flat display device characterized in that display data is supplied to a plurality of signal line drivers by spatially separating the data taken in by. 2. The flat display panel is a liquid crystal display panel, and a signal line driver is distributed and arranged for odd-numbered signal lines and even-numbered signal lines of the liquid crystal display panel. 2. The flat display device according to claim 1, wherein the data and clock pulse are supplied from the host system side with a clock pulse having a frequency twice that of the display data transfer rate.