JPH0758314A - Charge coupled element - Google Patents

Abstract

PURPOSE:To improve detection sensitivity by reducing capacitance due to a floated diffused layer to detect charges. CONSTITUTION:In a charge coupled element comprising an n type diffused layer 3 which becomes a charge transfer region, a floated diffused layer 4 for detection of charges, a reset drain 5, a transfer electrode 6, an output gate 7 and a reset gate 9, a polycrystalline silicon thin film 8 which becomes a channel region of a MOS transistor having the floated diffused layer 4 as the gate is provided on the floated diffused layer 4. The n<+> type polycrystalline silicon thin films 8a are formed at both ends of the polycrystalline silicon thin film 8. One of the thin film 8a is connected to the power supply VDD, while the other to a load transistor 10 to constitute an source follower circuit.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a charge coupled device,
In particular, the present invention relates to a charge coupled device having a novel charge detection mechanism.

[0002]

2. Description of the Related Art A floating diffusion type (hereinafter referred to as FD type) charge detecting device is known as a charge detecting device for a charge coupled device (US Pat. No. 4,646,119).
Specification). FIG. 5A is a plan view of the charge-coupled device described in the above-mentioned US patent specification, and FIG. 5B is a sectional view taken along the line BB '.

In FIG. 5, 1 is an n-type semiconductor substrate, 2 is a p-type well, 3 is an n-type diffusion layer forming a charge transfer region, and 4 is a transfer layer provided in the n-type diffusion layer 3. The floating diffusion layers 5 for detecting the signal charges that have been received are n ⁺ type diffusion layers, and the reset drain to which the power supply voltage V _DD is applied, and 6 are the two-phase transfer pulses φ ₁ and φ _2. The applied transfer electrode, 7 has a constant output gate voltage V _OG.
Is applied to the output gate, and 9 is a reset pulse φ
A reset gate for resetting the floating diffusion layer 4 to the potential of the reset drain 5 to which _R is applied, 10
Is a load side MOS transistor of the source follower, 19
Is an active side MOS transistor of the source follower, 20
Is an Al wiring connecting the floating diffusion layer 4 and the active transistor 19.

Next, the operation of the conventional example shown in FIG. 5 will be described with reference to FIG. At time T1, the transfer pulse φ ₁ becomes L and φ ₂ becomes H, the signal charge Q1 is transferred below the transfer electrode 6 to which φ ₂ is applied, and the signal charge Q2 is injected into the floating diffusion layer 4. At time T2, reset pulse φ _R
Becomes H, the floating diffusion layer 6 and the reset drain 5 are electrically connected, the signal charge Q2 is extracted by the reset drain 5, and the potential of the floating diffusion layer is raised to the potential V _{DD of the} reset drain. Then, reset pulse φ
_{When R} becomes L, the floating diffusion layer 4 is separated from the reset drain 5 and the reset operation is completed. At time T3, the transfer pulse φ ₁ becomes H and the transfer pulse φ ₂ becomes L, and the signal charge Q1 is transferred below the transfer electrode to which φ ₁ is applied. Then, at time T4, the transfer pulse φ ₁
Becomes L and φ ₂ becomes H, and the signal charge Q under the final transfer electrode
1 is transferred to the floating diffusion layer 4. The state at this time is similar to that at time T1. Hereinafter, the same operation is repeated.

The amount of signal charge is detected by observing the potential change of the floating diffusion layer when the state at time T3 shifts to the state at time T4 (T1). That is, the potential of the floating diffusion layer 4 fluctuates due to the transfer of the signal charge, but this potential change is proportional to the transfer charge amount as shown by the following equation. The transfer charge can be detected by observing with the connected source follower. V = Q / (C1 + C2) where V is the potential change of the floating diffusion layer, Q is the transfer charge amount,
C1 is the electrostatic capacitance of the floating diffusion layer, and C2 is the sum of the wiring capacitance up to the transistor connected to the floating diffusion layer and the gate capacitance of the transistor. These values are approximately C1 = C2 = 0.001 pF in the conventional manufacturing technology.

[0006]

In order to increase the charge detection efficiency and improve the sensitivity in the FD type charge detection element described above, it is necessary to reduce the charge detection capacitances C1 and C2 shown in the above equation. is there. Conventionally, a method of reducing the area of the floating diffusion layer has been used to reduce C1. However, in the conventional technique, it is necessary to provide a contact hole for connecting the floating diffusion layer and the wiring, and it has already reached its limit to reduce the size of the floating diffusion layer. In addition, in order to reduce C2, shorten the wiring length,
Although it is necessary to reduce the gate capacitance of the MOS type transistor, various wirings are laid near the output section, so it is difficult to avoid these and form the transistor closer to it. As the transistor size decreases, noise increases, and it is impossible to reduce the size with the current technology. Therefore, an object of the present invention is to provide a charge-coupled device with a reduced charge detection capacity, and thus to provide a more sensitive charge-coupled device or a smaller-sized charge-coupled device. It is about trying to be able to provide.

[0007]

In order to solve the above problems, according to the present invention, a charge transfer region (3) provided in the surface region of a semiconductor substrate and an insulating film on the charge transfer region are interposed. And a floating diffusion layer (4) provided in the surface region of the semiconductor substrate adjacent to the tip end of the charge transfer region in the charge transfer direction. And a reset drain (5) provided in the surface region of the semiconductor substrate adjacent to the floating diffusion layer.
And a reset gate (9) formed on the semiconductor substrate between the floating diffusion layer and the reset drain via an insulating film, and the source, drain and channel layers are provided on the floating diffusion layer. And a semiconductor thin film (8, 8a) for sensing the potential of the floating diffusion layer is formed via an insulating film.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 (a) is a plan view showing a first embodiment of the present invention, and FIGS. 1 (b) and 1 (c) are sectional views taken along the lines BB 'and CC', respectively. is there. Figure 1
In (a) and (b), 1 is an n-type semiconductor substrate, 2 is p
The type well 3 is an n-type diffusion layer forming a charge transfer region,
Reference numeral 4 denotes a floating diffusion layer for detecting the transferred signal charges, which constitutes the gate of a charge detection transistor (active side transistor of the source follower). 5
Is a reset drain to which a power supply voltage V _DD is applied and which is composed of an n ⁺ type diffusion layer, 6 is a two-phase transfer pulse φ ₁ ,
Φ ₂ is applied to the transfer electrode, 7 is an output gate to which a constant output gate voltage V _OG is applied, and 8 is a polycrystalline silicon thin film that serves as a channel region of a MOS transistor having the floating diffusion layer 4 as a gate. , 8a are formed by heavily doping impurities at both ends of the polycrystalline silicon thin film 8.
^{A +} -type polycrystalline silicon thin film, 9 is a reset gate to which the reset pulse φ _R is applied, for resetting the floating diffusion layer 4 to the potential of the reset drain 5, and 10 is polycrystalline with the floating diffusion layer 4 as a gate. The MOS transistor serves as a load of a MOS transistor (hereinafter, appropriately referred to as a semi-thin film transistor) using the silicon thin film 8 as a channel region.

In FIG. 1C, 11 is a field oxide film formed so as to surround the n-type diffusion layer 3, the floating diffusion layer 4 and the reset drain 5 to separate these regions from other regions. , 12 are field oxide films 11
A p ⁺ type channel stopper formed below, 13 is a gate oxide film, 14 is an interlayer insulating film, and 15 and 16 are n through contact holes formed in the interlayer insulating film 14, respectively.
^The drain electrode and the source electrode are in contact with the ⁺ type polycrystalline silicon thin film 8a. 1 (a) and 1 (b), the interlayer insulating film 14 and the source.
It is shown with the drain electrode removed.

FIG. 2 shows a MOS in which the floating diffusion layer 4 is used as a gate and the polycrystalline silicon thin film 8 is used as a channel region.
It is a graph which shows the qualitative voltage-current characteristic of a transistor, ie, a semi-thin film transistor. As shown in FIG. 1 (a), this transistor has its drain at V _DD.
The source is connected to the MOS transistor 10, which is a load transistor, and the source serves as an active side transistor of the source follower. And in this transistor,
When the voltage of the diffusion layer serving as the gate changes, the amount of current flowing in the polycrystalline silicon thin film changes as shown in FIG.
That is, the higher the gate voltage, the higher the current, and the lower the gate voltage, the lower the current, and as a result, the source voltage changes. In the charge coupled device of the present invention, it is not necessary to form a contact in the floating diffusion layer. Therefore, the area of this diffusion layer can be formed to be small, and the electrostatic capacitance thereof can be suppressed low. Moreover, since the wiring is not connected to the floating diffusion layer 4, the parasitic capacitance is reduced accordingly.

Next, with reference to FIGS. 3A to 3F, a method of manufacturing the half thin film transistor in this embodiment will be described. First, a p-type well 2, a floating diffusion layer (n-type diffusion layer) 4, and a thickness of 5000 are formed on an n-type semiconductor substrate (not shown).
A field oxide film 11 having a thickness of about Å and a gate oxide film having a thickness of about 800 Å are formed. Then, a polycrystalline silicon thin film 8A having a film thickness of about 800 Å is formed on the entire surface by a low pressure CVD method [FIG. 3 (a)]. Next, this polycrystalline silicon thin film is made amorphous by ion implantation of silicon to form an amorphous silicon thin film 8B [FIG. 3 (b)]. Next, heat treatment is performed in a nitrogen atmosphere at a low temperature of about 600 ° C. for about 60 hours to solid-phase grow the amorphous thin film,
A polycrystalline silicon thin film 8 having a large crystal grain size is formed [FIG. 3 (c)]. After that, it is processed into a predetermined pattern by photoetching, the surface is covered with an interlayer insulating film 14 made of a silicon oxide film, and contact holes are formed in the portions where the source electrode and the drain electrode are to be formed [FIG.
(D)]. Phosphorus (P) ions are implanted to form n ⁺ -type polycrystalline silicon thin films 8a on both ends of the polycrystalline silicon thin film 8 [FIG. 3 (e)]. Next, aluminum is vapor-deposited and patterned by photoetching to form the drain electrode 15 and the source electrode 16 [FIG.
(F)]. A method for forming such a MOS transistor is known from Japanese Patent Laid-Open No. 122631/1990.

As a method of forming a silicon thin film, a thin film semiconductor layer on an insulating substrate described in JP-A-61-78120 is subjected to heat treatment to homogenize the crystal grain size in advance, and then this thin film semiconductor is formed. For example, a method of irradiating a layer with a laser beam to melt and melt and melt the layer to form a thin film crystal can be adopted.

FIG. 4 is a sectional view showing a second embodiment of the present invention. In the figure, the same reference numerals are given to the portions common to the portions of FIG. First of the second embodiment
The difference from the embodiment is that the gate oxide film 17 and the bias gate electrode 18 are formed on the upper surface of the half thin film transistor. The bias gate electrode is connected to the output terminal of a source follower composed of a half thin film transistor and a constant current source. By configuring in this way,
The modulation efficiency of this half-thin film transistor can be enhanced, and the charge detection efficiency can be enhanced. The method of manufacturing the half-thin film transistor in the second embodiment is similar to that in the first embodiment described above.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made within the scope of the present invention described in the claims. For example, in the embodiment, 2
Although the buried channel type charge coupled device of the phase drive system has been described, it can be changed to a drive system other than the two phase type or a surface channel type. Further, the half thin film transistor can be a p-channel transistor. Moreover, all conductivity types of the embodiments can be reversed.

[0015]

As described above, in the charge coupled device of the present invention, a semiconductor thin film is formed on a floating diffusion layer via a gate insulating film, and this semiconductor thin film directly detects a potential change in the floating diffusion layer. Therefore, according to the present invention, the contact to the floating diffusion layer, which is required in the conventional charge detection method, is unnecessary, and the floating diffusion layer area can be reduced. That is, in the conventional example,
The floating diffusion layer could not be made smaller than about 10 μm × 8 μm, but according to the present invention, it can be reduced to 8 μm × 6.
It can be reduced to about μm. Further, according to the present invention, since the gate wiring is not necessary, the wiring capacitance C2 is only the gate capacitance. As a result, specifically, the electrostatic capacitance C1 of the floating diffusion layer is about 1/3 of the conventional one, the wiring capacitance C2 is about 2/3, and the charge detection sensitivity is about twice that of the conventional example.

Further, since the gate wiring can be omitted, the signal transmission path is shortened, and it is possible to realize a charge-coupled device which hardly picks up noise. And according to the present invention, the detection unit can be configured compactly,
Further, since the sensitivity is improved, it is possible to further reduce the size of an applied device such as a solid-state image sensor.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of the present invention and its BB ′.
The sectional view of the line and CC line.

FIG. 2 is a graph for explaining the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a process sectional view for explaining the manufacturing method of the first embodiment of the present invention.

FIG. 4 is a plan view of a second embodiment of the present invention and its BB ′.
The sectional view of the line and CC line.

FIG. 5 is a plan view of a conventional example and a cross-sectional view taken along the line BB ′ of FIG.

FIG. 6 is a potential distribution diagram and a timing chart for explaining the operation of the conventional example.

[Explanation of symbols]

1 n-type semiconductor substrate 2 p-type well 3 n-type diffusion layer 4 floating diffusion layer 5 reset drain 6 transfer electrode 7 output gate 8 polycrystalline silicon thin film 8A polycrystalline silicon thin film 8B amorphous silicon thin film 8a n ⁺ type polycrystalline silicon Thin film 9 Reset gate 10 Source follower load side MOS transistor 11 Field oxide film 12 p ⁺ type channel stopper 13 Gate oxide film 14 Interlayer insulating film 15 Drain electrode 16 Source electrode 17 Gate oxide film 18 Bias gate electrode 19 Active side of source follower MOS transistor 20 Al wiring

Claims (7)

[Claims] 1. A charge transfer region having a charge transfer region provided in a surface region of a semiconductor substrate and a plurality of transfer electrodes formed on the charge transfer region via an insulating film, and a charge of the charge transfer region. A floating diffusion layer provided in the surface region of the semiconductor substrate adjacent to the tip portion in the transfer direction; a reset drain provided in the surface region of the semiconductor substrate in the vicinity of the floating diffusion layer; A reset gate formed on the semiconductor substrate between the diffusion layer and the reset drain via an insulating film, forming a source, a drain, and a channel layer on the floating diffusion layer; A charge-coupled device characterized in that a semiconductor thin film for sensing the potential of a layer is formed via an insulating film. 2. The charge coupled device according to claim 1, wherein the charge transfer unit is a buried channel type. 3. The charge coupled device according to claim 1, wherein the charge transfer region is a second conductivity type semiconductor region provided in a surface region of the first conductivity type semiconductor substrate. 4. The charge transfer region is a first conductivity type semiconductor region provided in a surface region of a second conductivity type well formed on a first conductivity type semiconductor substrate. 1. The charge coupled device according to 1. 5. The charge coupled device according to claim 1, wherein the semiconductor thin film is a single crystal or polycrystalline silicon thin film. 6. A second semiconductor thin film is formed on the semiconductor thin film via an insulating film, and the second semiconductor thin film is connected to one end of the semiconductor thin film. The charge coupled device according to claim 1. 7. A constant current source is connected to one end of the semiconductor thin film, and a power supply is connected to the other end of the semiconductor thin film, and an output signal is obtained from a connection point with the constant current source. The charge-coupled device according to item 1.