JPH0757477A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To accelerate an access time at a reading time, to shorten a write pulse width at a writing time and to accelerate write recovery. CONSTITUTION:At the time of a read cycle, only transfer gates 1, 2 for read become a conductive state by an output selection part 21. Then, by a memory cell, a sense amplifier not shown in figure is driven through a bit line BIT (BIT<->), the transfer gates 1, 2 for read and a read data line RD (RD<->). Further, at the time of a write cycle, only the transfer gates 3, 4 for write become an interruption state by the output selection part 22, and the data are written in the memory cell through a write data line WD (WD<->), the transfer gates 3, 4 for write and a bit line BIT (BIT<->). Further, at the time of write recovery, a wiring required for pulling up becomes only the bit line BIT (BIT<->) and the read data line RD (RD<->), and the write recovery is accelerated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a static RAM.

[0002]

2. Description of the Related Art A memory, which is a semiconductor memory device, comprises a memory array composed of memory cells, which are a large number of memory elements, and peripheral circuits necessary for input / output. The position (address) of the memory cell to be accessed (read or write) is X address (row address) and Y address.
Designated by an address (column address), writing or reading of data is performed by an input / output control signal. Data transmission to the actual memory cell is
This is performed through the X line (word line) corresponding to the X address and the Y line (bit line) corresponding to the Y address. The bit line is driven by a column switch having a dedicated transfer gate pair for reading and writing and a data line pair.

In a conventional column switch in a memory, as shown in FIG. 7, read transfer gates 1 and 2 and write transfer gates 3 and 4 are used.
Were simultaneously controlled only by the address line ADD, the read / write transfer gates 1,
Bit line BIT, BIT through 2 or 3, 4
The three types of wirings, i.e., the read data lines RD and RD, and the write data lines WD and WD, were simultaneously driven. It should be noted that it is desirable to add an inversion symbol to the upper part of the symbol for the so-called low active line as in the drawing,
Since it is difficult to express the same as the drawing in the specification, BIT
As in ￣, the sign is followed by an inversion sign. The same applies to the other RDs and WDs, and the inverted codes are expressed as RD- and WD-, respectively.

[0004]

By the way, in the above-mentioned conventional semiconductor memory device, the bit lines BIT and BI are
Since three kinds of wirings of T, read data lines RD and RD, and write data lines WD and WD were driven at the same time, the memory cells are bit lines BIT and BIT and read data lines RD and RD during the read cycle. RD
In addition to the write data lines WD that do not need to be driven,
It was driving up to WD and had delayed access time. Further, unnecessary read data lines RD and RD were driven during the write cycle.

Particularly, at the time of write recovery, when reading the data opposite to the written data from the same bit line,
If the wiring is not pulled up after pulling up all the wirings whose potential has dropped to the ground level to the potential level in the steady state of reading, erroneous data will be output. However, in the conventional semiconductor memory device, since all three types of wiring must be pulled up, there are problems that it takes time to pull up and erroneous data is output.

Therefore, an object of the present invention is to provide a semiconductor memory device which can be accessed at high speed and can be recovered at high speed.

[0007]

In order to achieve the above object, a semiconductor memory device according to the present invention according to claim 1 has a memory cell arranged in a matrix, a pair of bit lines connected to the memory cell, and the memory. A word line connected to the cell,
A write-only selection circuit provided between each pair of bit lines and a write-only data bus line, and a read-only selection circuit provided between each pair of bit lines and a read-only data bus line And when writing to the memory cell,
The write-only selection circuit selectively couples the pair of bit lines to only the write-only data bus line, and when reading from the memory cell, the read-only selection circuit selects the pair of bit lines. It is characterized in that it is selectively coupled only to the read-only data bus line.

Further, each of the write-only selection circuit and the read-only selection circuit may be a switch circuit. Further, the write-only selection circuit is composed of a switch circuit,
The read-only selection circuit may be composed of a sense amplifier.

[0009]

In the present invention, when writing to the memory cell,
The write-only selection circuit selectively couples the pair of bit lines only to the write-only data bus line, and the read-only selection circuit selectively reads the pair of bit lines when reading from the memory cell. Coupling only to read-only data bus lines. Then, data transmission to the memory cell is performed via the word line and the bit line.

Therefore, at the time of reading, the write-only data bus line is disconnected from the bit line and the read-only data bus line, and the access time can be shortened. Also,
At the time of writing, the read-only data bus line is disconnected from the bit line and the write-only data bus line, and the write pulse width can be shortened. Further, at the time of write recovery, the wirings that need to be pulled up are only the bit line and the read-only data bus line, and the write recovery can be speeded up.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the semiconductor memory device of the present invention. In the figure, a semiconductor memory device 10 comprises a memory array 11 composed of a large number of memory elements and a peripheral circuit 12 required for input / output. Address buffer 13
Address signals A, A. , A is temporarily held and then output to the row decoder 14. The row decoder 14 receives the address signals A, A. , A is decoded and output to the memory array 11 as an X address (word line).

The address buffer 15 receives the address signals A, A. After temporarily holding A, the column decoder 16
Output to. The column decoder 16 receives the address signals A,
A. ..., A is decoded and output as a Y address to the column switch 17. Further, the control buffer 18 temporarily holds the write control signal WE, the chip selector CE, etc., and then, according to these, the address buffer 1
3, column switch 17, data in buffer 19
And outputs a predetermined control signal to the data out buffer 20. The column switch 17 drives the bit line BIT to specify the position of the memory cell in the memory array 11 according to the Y address (column address) and the write control signal WE, and at the same time, the write data line WD Value is written, or data is read to the read data line RD.

Next, the structure of the above-mentioned column switch 17 will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the column switch 17 in the embodiment of the present invention. In this figure, the same parts as those in FIG. 7 described above are designated by the same reference numerals and the description thereof will be omitted.
In FIG. 2, the column switch 17 is for reading,
Dedicated transfer gates 1 to 4 and data line pairs (RD and RD, WD and WD) for writing
It has and. Read data lines RD, RD shown
Is connected to a data out buffer 20 which is an output buffer through a sense amplifier (not shown), and write data lines WD and WD are connected to the data in buffer 1.
It is driven by the input data supplied via 9.

The read output selection section 21 and the write output selection section 22 are each provided with an address line A.
Address data is supplied via DD and a write control signal is supplied via a write line WE. One of the read output selection sections 21 activates the output only when the address data is active, and the other write output signal. The output selection section 22 of FIG. 6 activates its output when both the address data and the write control signal are active. The address is a signal decoded by the column decoder, and the write control signal corresponds to the write control signal of the control buffer.

Next, the operations during the read cycle, the write cycle and the write recovery by the above-mentioned structure will be described below. [During read cycle] In the read cycle, only the address data is selected and the write control signal is not selected, so that the output selection section 21 makes only the transfer gates 1 and 2 for reading conductive. Therefore, the memory cell drives the sense amplifier (not shown) through the bit lines BIT and BIT, the read transfer gates 1 and 2, and the read data lines RD and RD. On the other hand, transfer gates 3 and 4 for writing
Does not need to be driven because it is in the cutoff state.

[Write Cycle] In the write cycle, since the address data and the write control signal are both selected, the output select section 22 brings the write transfer gates 3 and 4 into a conductive state, and the write driver writes the data. Data lines WD, WD, write transfer gates 3, 4, bit lines BIT, B
Write data to the memory cell through IT. on the other hand,
Since the read transfer gates 1 and 2 are in the cutoff state, they do not have to be driven.

[At the time of write recovery] For example, a case will be described in which after writing "0", one data is read by the change of the write data line WD. At the time of writing "0", the write transfer gates 3 and 4 are in the conductive state, and the read transfer gates 1 and 2 are in the cutoff state. Therefore, the write data lines WD,
WD and bit lines BIT and BIT are pulled down to the ground level, and data "0" is written in the memory cell. Next, in the read cycle, the transfer gates 3 and 4 for writing are turned off, and the transfer gates 1 and 2 for reading are turned on. Bit lines BIT and B whose ground level is lowered
IT-is pulled up to a steady potential level at the time of reading by a pull-up circuit. Then, the bit line BIT is pulled down by the memory cell, and the sense amplifier outputs 1 data. Incidentally, in the conventional circuit, in addition to the bit line BIT, two nodes of the write data line WD and the read data line RD had to be pulled up, so that there was a drawback that the recovery time was long.

Next, a specific circuit configuration and operation of the above-mentioned column switch will be described with reference to FIGS. 3 to 6. FIG. 3 shows a first embodiment of the present invention.
In the figure, transfer gates 1 and 2 for reading
The gate circuits 31 and 32 of PMOS are used, and the gate circuits 33 and 34 of NMOS are used for the transfer gates 3 and 4 for writing. In addition, the output selection units 21, 2
2, a NAND circuit 23, a NOR circuit 24, and a negation circuit 25 are used. The address line ADD- is connected to one ends of the NOT circuit 25 and the NOR circuit 24. The write control line WE_ is connected to one end of the NAND circuit 23 and the other end of the NOR circuit 24. NAN
The D circuit 23 takes the logical product of the address data supplied through the NOT circuit 25 and the write control signal supplied through the write control line WE_ and outputs the output from the gate circuits 31 and 32 for reading. Supply to. On the other hand, NO
The R circuit 24 takes the logical sum of the address data supplied via the address line ADD and the write control signal supplied via the write control line WE, and outputs the result as an N-channel transistor for writing. Supply to 33 and 34.

Next, in the first embodiment shown in FIG.
The operation during the read cycle, the write cycle, and the write recovery will be described below. [During read cycle] During the read cycle, the address line ADD_ goes low and the write control line W
E becomes high level. The NAND circuit 23 takes the logical product of "1" inverted by the NOT circuit 25 and "1" of the write control signal. As a result, the NAND circuit 2
The output of 3 becomes "0". Therefore, P for reading
The channel transistors 31 and 32 become conductive. On the other hand, the NOR circuit 24 outputs the write control signal “1”,
The logical sum of the address data and "0" is calculated. As a result,
The output of the NOR circuit 24 becomes "0". Therefore, the writing N-channel transistors 33 and 34 are turned off. The memory cell drives the sense amplifier through the bit line BIT, the read P-channel transistors 31 and 32, and the read data line RD. N for writing
Since the channel transistors 33 and 34 are in the cutoff state, they do not have to be driven.

[During Write Cycle] During the write cycle, both the address line ADD and the write control line WE are at the low level, so that the write N-channel transistors 33 and 34 become conductive, and the write data is written by the write driver. Line WD (WD), bit line BI of write N-channel transistors 33 and 34
Write data to the memory cell through T (BIT). Since the P channel transistors 31 and 32 for reading are in the cutoff state, they do not have to be driven.

[At the time of write recovery] For example, at the time of writing "0", the write N-channel transistors 33 and 34 are in the conductive state and the read P-channel transistors 31 and 32 are in the cut-off state. WD and the bit line BIT are pulled down to the ground level, and "0" data is written in the memory cell. In the read cycle, the write P-channel transistors 33 and 34 are turned off and the read P-channel transistors 31 and 32 are turned on. Bit line BIT whose ground level is lowered
Is pulled up to the steady potential level at the time of reading by the pull-up circuit. Then, the bit line BIT is pulled down by the memory cell, and the sense amplifier outputs 1 data.

As described above, according to the first embodiment, the write transfer gates 3 and 4 are turned off during the read cycle, and the bit line BIT (BIT).
), The write data line WD (WD) is separated from the read data line RD (RD), and the access time can be shortened. Also, during the write cycle, the read transfer gates 1 and 2 are cut off,
Bit line BIT (BIT), write data line WD
The read data line RD (RD) is separated from (WD), and the write pulse width can be shortened. The wiring that needs to be pulled up at the time of write recovery is the bit line BIT (BIT) and the read data line RD (RD).
Only ￣) is available, which enables faster write recovery.

Next, FIG. 4 shows a second embodiment of the present invention. Since the column switch 17 usually has a severe layout condition, many elements cannot be arranged, and the column switch 17 described above does not have the first structure.
It is difficult to control both the read / write transfer gates by the write control signal WE-, as in the embodiment of FIG. Therefore, in the second embodiment, only the write transfer gates 3 and 4 are connected to the write control line W.
It is controlled by E. That is, the read P channel transistors 31 and 32 are controlled by the address line ADD, and the NOR circuit 26 takes the logical sum of the address line ADD and the write control line WE, thereby writing the N channel transistor 33. , 34 are controlled.

In the second embodiment, first, at the time of reading, only the address line ADD is at a low level, so that the read P-channel transistors 31 and 32 are in a conductive state and the write N-channel transistor 33 ,.
Since 34 is in the cutoff state, the operation is basically the same as that of the first embodiment. On the other hand, at the time of writing, the P channel transistors 31 and 32 for reading do not become in the cutoff state, so the read data line RD (RD) is pulled down. Therefore, during write recovery,
The bit line BIT and the read data line RD must be pulled up. As a result, the write recovery becomes slower than that of the first embodiment, but it is superior to the conventional circuit.

Next, FIG. 5 shows a third embodiment of the present invention. In the third embodiment, the address line ADD controls the N channel transistors 33 and 34 for writing,
The NAND circuit 27 takes the logical product of the write control line WE and the address line ADD, and thereby controls the P channel transistors 31 and 32 for reading.

At the time of reading, the address line ADD becomes high level and the write control line WE_ becomes high level. Therefore, the output of the NAND circuit 27 becomes low level, and the P channel transistors 31 and 32 for reading are turned on. Further, since the address line ADD becomes high level, the writing N-channel transistor 3
Since 3 and 34 are also in the conductive state, the write data line WD is driven in addition to the bit line BIT and the read data line RD.

At the time of writing, the address line ADD becomes high level and the write control line WE_ becomes low level. Therefore, the output of the NAND circuit 27 becomes high level, and the P channel transistors 31 and 32 for reading are turned off. On the other hand, since the address line ADD is at the high level, the writing N-channel transistor 3
3, 34 become conductive. In this way, the read P
Since the channel transistors 31 and 32 are cut off, only the write data line WD and the bit line BIT need be driven. For writing recovery,
Since both transfer gates for reading are conductive, the bit line BIT, the read data line RD, and the write data line WD are pulled up.

Next, FIG. 6 shows a fourth modification of the present invention. In the fourth embodiment, the output selection section 21 for reading is used.
An NMOS transfer gate 40 is used for the output, and a sense amplifier 41 is used for the output selection unit 22 for writing. The write control line WE is connected to the N-channel transistors 35 and 36, and the write control line WE_ is connected to the N-channel transistor 37 of the sense amplifier 41. Also,
The write data lines WD and WD are respectively connected to the bit line BI through the N-channel transistors 35 and 36.
It is connected to T and BIT. On the other hand, the read data lines RD and RD are connected to N-channel transistors 38 and 39 which form a sense amplifier 41.

In the above structure, at the time of writing, the write control line WE is at the high level and the write control line WE
Becomes low level. Therefore, the transfer gate 40 becomes conductive and the sense amplifier 41 becomes inactive. Therefore, the data on the write data lines WD and WD_ is output to the bit lines BIT and BIT_. On the other hand, at the time of reading, the write control line WE becomes low level and the write control line WE- becomes high level. Therefore, the transfer gate 40 is turned off, and the N-channel transistor 37 of the sense amplifier 41 is pulled down to the ground level. As a result, the data in the memory cell is stored in the bit line BI.
Read data lines RD and RD through T and BIT
Is output to.

[0030]

According to the present invention, memory cells arranged in rows and columns, a pair of bit lines connected to the memory cells, a word line connected to the memory cells, and each pair of bit lines. A write-only selection circuit provided between the write-only data bus line and a read-only data bus line, and a read-only selection circuit provided between the read-only data bus line for each of the pair of bit lines. When writing to a cell, the write-only selection circuit selectively couples the pair of bit lines to only a write-only data bus line, and when reading from the memory cell, the read-only selection circuit: Since the pair of bit lines are selectively coupled only to the read-only data bus line, the write-only data bus line is disconnected from the bit line and the read-only data bus line during reading. Is, the access time can be made faster. Also, at the time of writing, the read-only data bus line is disconnected from the bit line and the write-only data bus line,
The write pulse width can be short. Further, at the time of write recovery, the wirings that need to be pulled up are only the bit line and the read-only data bus line, and the write recovery can be speeded up.

[Brief description of drawings]

FIG. 1 is a block diagram showing an entire memory configuration of a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a column switch in the same embodiment.

FIG. 3 is a circuit diagram showing a specific configuration of the first exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram showing a specific configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific configuration of a third exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific configuration of a fourth exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a column switch in a conventional semiconductor memory device.

[Explanation of symbols]

1, 2 Transfer Gate for Read (Read-Only Select Circuit) 3, 4 Transfer Gate for Write (Write-Only Select Circuit) 11 Memory Array (Memory Cell) 21 Output Selector for Read 22 Output for Write Selector 23,27 NAND circuit 24,26 NOR circuit 25 Negative circuit 31,32 P-channel transistor for reading 33,34 N-channel transistor for writing 35-39 N-channel transistor 40 Transfer gate 41 Sense amplifier BIT (BIT) Pair of bit lines WD (WD) Write data line (write-only data bus line) RD (RD-) Read data line (read-only data bus line)

Claims (3)

[Claims] 1. A memory cell arranged in a matrix, a pair of bit lines connected to the memory cell, a word line connected to the memory cell, and a write-only data bus for each of the pair of bit lines. A write-only selection circuit provided between the memory cell and a read-only selection circuit provided between each of the pair of bit lines and a read-only data bus line. The write-only selection circuit selectively couples the pair of bit lines to only the write-only data bus line, and when reading from the memory cell, the read-only selection circuit selects the pair of bit lines. A semiconductor memory device characterized by being selectively coupled only to a read-only data bus line. 2. The semiconductor memory device according to claim 1, wherein each of the write-only selection circuit and the read-only selection circuit comprises a switch circuit. 3. The semiconductor memory device according to claim 1, wherein the write-only selection circuit comprises a switch circuit, and the read-only selection circuit comprises a sense amplifier.