JPH0756947B2 - Spreading code acquisition circuit - Google Patents

Description

The present invention relates to a spread code acquisition circuit in a spread spectrum communication system.

[Conventional technology]

FIG. 3 is a diagram showing a spread code acquisition circuit in conventional spread spectrum communication, in which 1 is a receiving PN-BPSK.
Signal, 2 is a local signal generator, 3 is a mixer that multiplies the received PN-BPSK signal 1 and the output of the local signal generator 2, 4 is a 90 ° phase shifter, 5 is a low-pass filter, 6 is an analog-digital converter, 7 is a digital matched filter, 8 is a squarer that squares the output of the digital matched filter 7, 9a and 9b are adders, 10 is a delay device that delays the output of the adder 9b by the spreading code length, and 11 is a correlation A maximum value determiner 12 is a reference spread code generator.

Next, the operation will be described.

The received PN-BPSK signal 1 is converted into a baseband signal by the local signal 2, then passes through the low-pass filter 5, and is converted into digital data by the analog-digital converter 6. Then, using the digital matched filter 7, the correlation value of the input spread spectrum signal with the output from the reference spread code generator 12 is obtained. Next, the digital matched filter 7 is added by the squaring unit 8 and the adder 9a.
The sum of squares of the correlation value of the output of is obtained, and this is synchronously added by the adder 9b and the delay device 10, and the maximum correlation value is determined by the maximum correlation value determination unit 11 to detect the phase of the spreading code. Capture the spreading code.

[Problems to be Solved by the Invention]

In the conventional spread code acquisition circuit, the maximum value of the correlation is obtained by synchronously adding the square sums of the correlation values. Therefore, the dynamic range of the correlation values after the sum of squares is widened, the number of bits of data to be handled increases. Therefore, there is a problem that the synchronous addition unit and the maximum value determination unit become large.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a spreading code acquisition circuit that can reduce the synchronous addition of correlation values and the maximum value determination unit.

[Means for Solving the Problems]

A spread code acquisition circuit according to the present invention is a spread code acquisition circuit in a spread spectrum communication system, in which a code phase is detected from spread spectrum signals of first and second channels having a predetermined phase difference. And second digital matched filters, first and second squaring circuits for squaring the outputs of the first and second digital matched filters, and outputs from the first and second squaring circuits. An adder circuit for adding, a square root circuit for obtaining the square root of the sum of squares, a synchronous adder circuit for synchronously adding the square roots, and a correlation maximum value judging device for judging the maximum value of the correlation from the output of the synchronous adding circuit. It was prepared.

[Action]

According to the present invention, the dynamic range (the number of bits) of the data to be handled is halved due to the above configuration, and the hardware scale of the synchronous addition unit and the maximum value determination unit is reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a received PN-BPSK signal, 2 is a local signal generator, 3 is a mixer for multiplying the received PN-BPSK signal 1 and the output of the local signal generator 2, 4 is a 90 ° phaser,
5 is a low-pass filter, 6 is an analog-to-digital converter, 7 is a digital matched filter, 8 is a squarer that squares the output of the digital mated filter 7, 9a and 9b are adders, and 10 is an output of the adder 9b. Is a delay unit for delaying the spreading code length, 11 is a correlation maximum value judging unit for judging the maximum value of the correlation, 12 is a spreading code generator for generating a reference spreading code, and 13 is a square root circuit for obtaining a square root.

The received PN-BPSK signal 1 is converted into a baseband signal by the local signal 2 and then the low-pass filter 5
Is converted into digital data by the analog-digital converter 6. Then, using the digital matched filter 7, the correlation value of the input spread spectrum signal with the output from the reference spread code generator 12 is obtained. Next, the square root of the sum of squares of the correlation value of the output of the digital mud filter 7 is obtained by the squarer 8, the adder 9a, and the square root circuit 13, and this is added synchronously by the adder 9b and the delay device 10 to obtain the maximum correlation value. The judging device 11 judges the maximum value of the correlation value, detects the phase of the spreading code, and captures the spreading code.

As described above, in the above embodiment, since the square root of the sum of squares of the correlation value of the output of the digital matched filter is obtained, the number of bits of data handled by the synchronous addition unit and the maximum value determination unit is halved. , It is possible to reduce the scale of these circuits by half. Furthermore, the delay unit that constitutes this synchronous adder is composed of a memory, and the square root generator is ROM.
With the above configuration, the circuit scale can be further reduced, and the circuit scale can be reduced as a whole even if the increase in the circuit scale due to the addition of the square root generator is taken into consideration.

This means that if the input of the square root generator 13 is, for example, 8 bits, the ROM address of the square root generator 13 is 256, and 4 bits of square root data are required for each address, so a capacity of 1024 bits is required. And, the input of the delay device 10 is 6 bits when the number of synchronous additions is 4, for example,
If the spreading code length is 2047, the address is 2047.
Therefore, since the capacity of 12282 bits is required, the capacity of the square root generator 13 and the delay device 10 is required to be 13306 bits, whereas the input of the delay device is 10 bits and its address is conventionally. It is clear from 2047 that the capacity of 20470 bits is required.

In the above embodiment, the squaring unit 8, the adder 9a, and the circuit 13 for obtaining the square root are separately configured. However, as shown in another embodiment of the present invention in FIG. If the ROM 14 in which the value obtained by taking the square root is written is used, the square root of the sum of squares can be obtained by one ROM, so that the device can be further downsized.

〔The invention's effect〕

As described above, according to the spread code acquisition circuit of the present invention, in the spread code acquisition circuit in the spread spectrum communication system, the spread code signals of the first and second channels which have a predetermined phase difference from each other are encoded. Of the first and second digital matched filters, the first and second square circuits for squaring the outputs of the first and second digital matched filters, and the first and second digital matched filters. An adder circuit for adding outputs from the squaring circuit, a square root circuit for obtaining a square root of the sum of squares, a synchronous adding circuit for synchronously adding the square roots, and a maximum correlation value determined from outputs of the synchronous adding circuit. Since it is equipped with a correlation maximum value determiner, the number of bits of data handled by the synchronous adder and maximum value determiner is halved, and the scale of these circuits can be reduced by half. Becomes ability, there is an effect that the apparatus can be downsized.

[Brief description of drawings]

FIG. 1 is a diagram showing a spread code capturing circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing another embodiment of the present invention, and FIG. 3 is a diagram showing a conventional spread code capturing circuit. 1 is a PN-BPSK signal, 2 is a local signal, 3 is a mixer, 4
Is a 90 ° phaser, 5 is a low-pass filter, and 6 is analog-
Digital converter, 7 is a digital matched filter, 8
Is a squarer, 9 is an adder, 10 is a delay device, 11 is a maximum value judgment device, 12 is a spreading code generator, 13 is a square root generator, and 14 is RO.
It is M. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A spread code capturing circuit in a spread spectrum communication system, wherein first and second digital signals detect a phase of a code from spread spectrum signals of first and second channels having a predetermined phase difference from each other. A matched filter; first and second squaring circuits for squaring the outputs of the first and second digital matched filters; and an adder circuit for summing the outputs from the first and second squaring circuits. A square root circuit for obtaining the square root of the sum of squares, a synchronous adder circuit for synchronously adding the square roots, and a correlation maximum value judging device for judging the maximum value of the correlation from the output of the synchronous adding circuit. Spreading code acquisition circuit.