JP2718298B2 - PN code capture circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PN code acquisition circuit for use in a receiver for spread spectrum communication for acquiring a bit string having a fixed pattern.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional PN code acquisition circuit disclosed in Japanese Patent Publication No. 2-196660. In FIG. 2, 1 is a reception signal input terminal, 2 is a reference carrier oscillator, 3a and 3b are mixers, 4 is a phase shifter for shifting the output of the reference carrier oscillator 2 by π / 2 [rad], 5
a and 5b are low-pass filters (hereinafter referred to as LPFs), 6
a and 6b are analog / digital converters (hereinafter A / D converters) for converting the outputs of the LPFs 5a and 5b into digital signals.
Converters), 7a and 7b are digital matched filters (hereinafter referred to as DMF) for correlating outputs of the A / D converters 6a and 6b with PN codes to be received, 8a and 8b are squarers, and 9 is An adder 10 for adding the outputs of the two squarers 8a and 8b; a comparator 11 for comparing the output of the adder 9 with a preset threshold level;
Is an output terminal for outputting the result of the comparator 10.

FIG. 3 shows a circuit configuration of the DMF 7a and DMF 7b. In the drawing, 12 is a delay element for storing a received signal, 13 is a delay element for storing a PN code to be received, 14 is a multiplier for multiplying the outputs of the delay elements 12 and 13, and 15 is the multiplier 1
4 is an adder for adding all the outputs of the four.

Next, the operation will be described. The received signal input to the input terminal 1 is split into two. The branched first signal is multiplied by the output of the reference carrier oscillator 2 by the mixer 3a, and then converted into a baseband signal by the LPF 5a.

[0005] The baseband signal is converted into a digital signal by an A / D converter 6a and input to a DMF 7a. After being correlated with the prepared PN code in the DMF 7a, it is squared by the squarer 8a.

On the other hand, the second signal input to the input terminal 1 and branched is multiplied by the output of the phase shifter 4 by the mixer 3b to prepare the same code pattern as the LPF 5b, A / D converter 6b, and DMF 7a. After passing
It is squared by the squarer 8b.

[0007] The outputs of the respective squarers 8a and 8b are added by an adder 9, and then compared with a threshold level by a comparator 10. When the output of the adder 9 exceeds this threshold level, a pulse is output from the output terminal 11 and the capture is completed.

The P prepared by the DMF 7a and DMF 7b
If the N code and the PN code of the input signal match, DM
The sum of the products of the PN codes stored in the delay elements of F increases, and a signal having a large peak is output from each of the DMFs 7a and 7b.

As a result, the output of the adder 9 exceeds the threshold level of the comparator 10. If the PN codes do not match, the sum of the products of the PN codes has no peak and the DMF 7
a, the output of the DMF 7b is merely noise, and therefore does not exceed the threshold level of the comparator 10.

[0010]

Since the conventional PN code capturing circuit is configured as described above, when the noise level of the received signal is large, the outputs of the DMFs 7a and 7b become PN.
Since the difference between the correlation peak of the code and the portion other than the peak is small, it is difficult to detect the correlation peak. As a result, the judgment in the comparator 10 is likely to be erroneous.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a PN code capturing circuit with less malfunction.

[0012]

A PN code acquisition circuit according to the present invention has the same input terminal as a first digital matched filter for correlating a PN code based on a signal from a first mixer, and has a first input terminal. A second digital matched filter for preparing a PN code pattern different from that of the first digital matched filter, first and second squarers for squaring the outputs of the first and second digital matched filters, respectively, A first subtractor for subtracting the output of the second squarer from the output of the squarer, and the same code pattern as the first digital matched filter are prepared, and the PN code is correlated based on the signal from the second mixer. A third digital matched filter having the same input terminal as the third digital matched filter; 4 to prepare the same code pattern as
, A third and fourth squarer for squaring the output of each of the third and fourth digital matched filters, and a second subtraction for subtracting the fourth squarer output from the third squarer output And a vessel.

[0013]

The PN code capturing circuit according to the present invention squares the outputs of the first and second digital matched filters having different PN codes by the first and second squarers, respectively, to generate the first and second digital matched filters.
By subtracting the output of the second squarer with the first subtractor, the noise component is canceled, and the output of the third digital matched filter and the same code pattern as that of the second digital matched filter are prepared. The outputs of the digital matched filter are respectively squared by the third and fourth squarers, and the outputs of the third and fourth squarers are subtracted by the second subtractor, thereby canceling out noise components. In addition, even when the noise level of the received signal is high, the detection of the correlation peak becomes easy, and the comparator operates so as not to make an erroneous determination.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the PN code capturing circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the embodiment. 1, the same reference numerals as those in FIGS. 2 and 3 denote the same or corresponding parts.

In FIG. 1, reference numerals 7c and 7d denote DMFs having the same code pattern.
The code pattern is different from that of the DMF 7b.

The outputs of these DMFs 7c and 7d are DMF
Like the outputs of 7a and 7b, the squares are made by the squarers 8c and 8d. Outputs of the squarers 8a and 8c are subtracted by a subtractor 16a.

Similarly, the outputs of the squarers 8b and 8d are subtracted by a subtractor 16b. The outputs of these subtracters 16a and 16b are added by an adder 9. Other configurations are the same as those in FIG. 2, and a description of the same components as those in FIG.

Next, the operation will be described. In the description of this operation, the same parts as those in FIG.
The features of the embodiment are mainly described.

In FIG. 1, A / D converter 6a
Are branched, and the respective signals are divided into DMF7a and DMF7.
The correlation is taken at c. The PN code in the received SS signal is DM
In the same case as that prepared in F7a, a signal having a peak is output from the DMF 7a, but a signal including only noise without a peak is output from the DMF 7c.

The outputs of the DMFs 7a and 7b are input to squarers 8a and 8c, respectively, where they are squared and then input to a subtractor 16a. This subtracter 16a uses DMF7
By subtracting the square of the output of the DMF 7c from the square of the output a, the noise components of the outputs of the DMF 7a and DMF 7c cancel each other, and only the correlation peak remains.

In exactly the same way, the output of the A / D converter 6b is input to the DMFs 7b and 7d for correlation, and the outputs of the DMFs 7b and 7d are squared by the squarers 8b and 8d, respectively, and then are subtracted by the subtractor 16b. Is subtracted, DMF7
The noise components of the outputs b and 7d are canceled.

The outputs of the subtracters 16a and 16b are added by an adder 9, and the addition result is compared with a threshold level by a comparator. When the addition result exceeds the threshold level, a pulse is output from an output terminal 11. hand,
Capture is complete. When the threshold level and the addition result are compared by the comparator 10, since a noise component has been removed from the addition result, the peak can be easily determined by comparison.
Misjudgment is eliminated.

[0023]

As described above, according to the present invention, the first
A second DM that prepares a code pattern different from the DMF of
F, the noise component is canceled by taking the square difference of these outputs, and the same code pattern as the first DMF is used.
After subtracting the square of the output of the fourth DMF that prepares the same code pattern as the third DMF that prepares the turn and the second DMF to cancel the noise component, the two subtraction results are added by the adder. Therefore, even when the noise level of the received signal is high, the detection of the correlation peak becomes easy, so that the malfunction does not occur.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PN code acquisition circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional PN code acquisition circuit.

FIG. 3 is a block diagram showing details of a DMF in a conventional PN code acquisition circuit.

[Explanation of symbols]

 Reference Signs List 1 received signal input terminal 2 reference carrier oscillator 3 mixer 4 phase shifter 7a digital matched filter 7b digital matched filter 7c digital matched filter 7d digital matched filter 8a squarer 8b squarer 8c squarer 8d squarer 9 adder 10 comparator 16 Subtractor

Claims (1)

(57) [Claims] A first mixer for multiplying a received signal by a reference carrier; a phase shifter for shifting the phase of the reference carrier; a second mixer for multiplying an output of the phase shifter by the received signal; A first digital matched filter for correlating the PN code based on the signal from the first mixer; and a PN code pattern having the same input terminal as the first digital matched filter and different from the first digital matched filter. A second digital matched filter to be prepared, a first squarer and a second squarer for squaring the first and second digital matched filter outputs, and a second square from the first squarer output A first subtracter for reducing the output of the first digital matched filter and the same code pattern as that of the first digital matched filter are prepared based on the signal from the second mixer. A third digital matched filter for correlating the PN code, a fourth digital matched filter having the same input terminal as the third digital matched filter and preparing the same code pattern as the second digital matched filter, A third squarer and a fourth squarer for squaring the outputs of the third and fourth digital matched filters, and a second subtraction for subtracting the output of the fourth squarer from the output of the third squarer 1. A PN code acquisition circuit comprising: an adder, an adder for adding an output of the first subtractor and an output of the second subtractor, and a comparator for comparing the output of the adder with a set threshold level.