JPH0211034A - Spread spectrum communication receiver - Google Patents

Abstract

PURPOSE:To detect a synchronizing condition in a wide range even when the threshold of a comparator is set higher than the voltage value of a noise component by converting a signal to add the output of two detectors of a delay lock loop with an adder to binary with a comparator and making it into a synchronizing detecting signal. CONSTITUTION:The output of two detectors 12 and 13 of a delay lock loop is added and connected through a comparator 19 to a code pickup circuit 2. Thus, even when the noise is superimposed to an input signal and the threshold is set higher in order to prevent the erroneous detection due to the noise, the synchronization detection is executed in the wide range in which the synchronization is held, and therefore, it is eliminated that a code pickup circuit 2 is started during the synchronization and the demodulation of data are temporarily interrupted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization detection circuit for a receiver for spread spectrum communication.

[Conventional technology]

FIG. 2 is a diagram showing a conventional direct-sequence type spread spectrum communication receiver. In FIG. 2, 1 is a modulation signal input terminal, 2 is a code acquisition circuit, 3 is a PN code generator, and 4 is a first 5 is a demodulation circuit, 6 is a baseband data output terminal, 7 is a synchronization holding circuit, 8 is a second correlator, 9 is a third correlator, 10 is a first bandpass filter, 11
is the second bandpass filter, 12 is the first detector, 1
3 is a second detector, 14 is a subtracter, 15 is a loop filter, 16 is a voltage controlled oscillator, 17 is a third bandpass filter, 18 is a third detector, and 19 is a comparator.

Next, the operation will be explained.

In the spread spectrum communication receiving device configured as described above, the transmitted spread spectrum signal that has been subjected to secondary modulation using a spreading code sequence is inputted from the modulation signal input terminal 1 and is divided into three parts. 1 correlator 4. Second correlator8. The signal is sent to the third correlator 9.

The code acquisition circuit 2 detects the synchronization timing of the received spreading code sequence. When synchronization timing is detected, a timing signal is sent to the PN code generator 3,
Based on this timing signal, the PN code generator 3 generates a reference PN code sequence synchronized with the spreading code sequence added to the received signal, and sends it to the first correlator 4. In the first correlator 4, the input spread spectrum signal is multiplied by the above code sequence to solve the spread code (this is called despreading).
This becomes an IF signal modulated with only the transmission data.

This IF signal is sent to the demodulation circuit 5, where the baseband data is demodulated and output from the baseband data output terminal 6.

Further, a synchronization holding circuit 7 is provided in order to maintain the synchronization state between the spreading code sequence of the input signal and the reference PN code sequence from the PN code generator 3 and always perform despreading.

The above-mentioned PN code generator 3 generates a reference PN code sequence as well as a 1/2 chip timing earlier (+TC/2) P
Slow N code and 1/2 chip timing (-Tc/2)
The PN code is generated simultaneously, and the PN signal sequence with early 1/2 chip timing is sent to the second correlator 8 of the synchronization holding circuit 7.
The PN code sequence with a slow 1/2 chip timing is sent to the third correlator 9.

Second. In the third correlator 8.9, the input spread spectrum signal and the above-mentioned PN code sequence are multiplied, and after the noise components are reduced in the first bandpass filter 10 and the second bandpass filter 11, the first Detector 12. Second
The respective PN code sequences input to the second and third correlators by envelope detection by the detector 13 of
A DC component of the correlation value between the input spread spectrum signal wave and the spread code sequence is obtained.

Figure 3(a) shows the output waveform of the first detector 12 in response to timing changes in the PN code sequence of the input spread spectrum signal.
The output waveform of the second detector 13 is shown in the same figure). The DC components of these correlation values are subtracted by the first subtractor 14 and smoothed by the loop filter 15. The voltage controlled oscillator 16 is controlled by the output voltage of the loop filter 15, generates a clock signal synchronized with the timing of the input spreading code sequence, and sends it to the PN code generator 3.

FIG. 3(C) shows the control voltage waveform of the voltage controlled oscillator with respect to timing changes of the input PN code sequence.

The above circuit is called a delay lock loop, and is commonly used as a synchronization holding circuit in a DC spread spectrum communication receiver.

When this device is used in satellite communications where the input C/N ratio (input signal-to-noise ratio) is very poor, synchronization may be lost due to the input of noise that exceeds the control range of the synchronization holding circuit. If synchronization is lost, the code acquisition circuit 2 must be started again.

Synchronous detection is performed using the following circuit.

When the input spreading code sequence and the code sequence from the PN code generator 3 are synchronized, the output of the first correlator 4 is despread as described above, and a part of this signal is transmitted to the third bandpass. After the noise component is reduced by the filter 17, the third detector 18 performs envelope detection to obtain a synchronous detection output.

FIG. 3(d) shows the above-mentioned synchronous detection output waveform with respect to timing changes of the input PN code sequence.

This detection output is “1” or “0” at comparator 19.
When synchronization is detected, "1" is sent to the code acquisition circuit 2, and "0" is sent to the code acquisition circuit 2 when synchronization is lost.
In this case, the code acquisition circuit 2 is controlled to start up again.

[Problem to be solved by the invention]

The conventional spread spectrum communication receiver is configured as described above, and synchronization detection is determined by the output value of the comparator 19. Since noise components that cannot be removed are superimposed, the threshold value of the comparator is set to a high value as shown in FIG. 3(d) to prevent erroneous synchronization detection due to noise when synchronization is lost.

Therefore, with respect to the timing change of the input PN spreading code sequence, the difference from -3T c / 2 to +3 shown in FIG. 3(C)
Even though it is possible to maintain synchronization in the range of Tc/2, -3Tc/2 to -Tc/2.

When it is in the range of +Tc/2 to +3Tc/2, comparator 1.9 considers it to be out of synchronization, and signal acquisition circuit 2
There was a problem in that data demodulation was interrupted from the time the system started until synchronization detection was established again.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a receiving apparatus for spread spectrum communication that can accurately detect a synchronization state with respect to an input PN spreading code.

[Means to solve the problem]

A receiver for spread spectrum communication according to the present invention is such that the outputs of two detectors of a delay lock loop are added together by an adder and connected to a code acquisition circuit via a comparator.

[Effect]

In this invention, a signal obtained by adding the outputs of two detectors of a delay lock loop using an adder is combined with a comparator.
Since the IJtJi detection signal is converted into two values, ``'' and ``O,'' even if the threshold of the comparator is set higher than the voltage value of the noise component, the synchronization state can be maintained within a wide range that can be maintained by the synchronization holding circuit. can be detected.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, numerals 1 to 16.19 are exactly the same as the conventional circuit described above. 20 is an adder.

In the spread spectrum receiver configured as described above, code acquisition, data demodulation, and synchronization maintenance are performed in the same manner as in conventional devices.

A part of the outputs of the first detector 12 and the second detector 13 are taken out separately from the synchronization holding circuit 7 and added in an adder 20. The output waveform of the adder 20 in response to changes in the input PN spreading code sequence is shown in Fig. 3 (a).
) A composite waveform of the waveform shown in (b) is obtained. Adder 20
The output is converted into a binary value of "l" or "0" by the comparator 19, and when synchronization is detected, "11" is sent, and when synchronization is out, "0" is sent to the code acquisition circuit 2, and "O" is sent. In this case, the code acquisition circuit 2 is controlled to start up again.

In the above embodiment, the adder 20 is provided at the output of the first detector 12 and the second detector 13 to extract the synchronization detection signal, but the same effect can be obtained even if an A/D converter is provided. You can get the following functions.

Another embodiment of the present invention having such a configuration is shown in FIG.

In FIG. 4, numerals 1 to 13 and 15 to 16 have the same or equivalent functions as those of the conventional example and the above embodiment.

21 is a first A/D converter, 22 is a second A/D converter, 23 is an arithmetic circuit, and 24 is a D/A converter.

The output signals of the first detector 12 and the second detector 13 are converted into digital signals by a first A/D converter 21 and a second A/D converter 22, respectively. The arithmetic circuit 23 adds and subtracts the output of the first A/D converter 21 and the output of the second A/D converter 22, and the subtraction result is shown in FIG. 3 (0) as in the conventional example. However, since the signal is converted into a digital value, the loop filter 15 is also configured with a digital filter, and the D/A converter 24 converts the signal back to an analog signal to control the voltage controlled oscillator 16.

The addition result is compared with the threshold value set in the arithmetic circuit 23, and if synchronization is detected, "1" is sent to the code acquisition circuit 2, and if synchronization is out, "O" is sent to the code acquisition circuit 2, and if it is "0", "0" is sent to the code acquisition circuit 2. controls the code acquisition circuit 2 to start up again.

Furthermore, in the above embodiment, the case where the synchronization holding circuit is a delay lock loop has been described, but the synchronization holding circuit may be a time division code tracking loop system (Time 5hared code track
ing 1oop), the same effect as in the above embodiment is achieved.

FIG. 5 shows still another embodiment in which the present invention is applied to a time-division code tracking loop system.

25 is a switch changeover signal generator, 26 is a switch, 27
is a correlator of the synchronization holding circuit, 28 is a bandpass filter,
29 is a detector, 30 is a dither wipe-off circuit (dith
er wipe off) and 1 to 7.15 to 1
6.19 indicates the same or equivalent part as the conventional device, and code acquisition and data demodulation are the same as in the conventional device.

The operation of the time-division code tracking loop is described in the document “Japan
K. Holmes; Coherent Spread Spectrum Systems, J.J., Holmes, C0
HI! RENT 5PREAD SPIICTRUM
SYSTHMS” 1982John Wiley
&5ons, Inc.,” J.

In the time-division code tracking loop, the switch switching signal generator 2
The correlator 27 is used in a time-division manner by switching at high speed the signal from the PN code generator 3 sent to the correlator 27 by the switch 26 controlled by the alternating signal from the bandpass filter 28. Through the detector 29
The waveform after being detected is equal to that shown in FIG. 3(f).

Further, after passing through the dither wipe-off circuit 30, the state shown in FIG. 3 (C
) will have a similar waveform.

Therefore, synchronization detection and synchronization maintenance can be performed in the same manner as in the first embodiment of the present invention.

In this embodiment in which the present invention is applied to the time division code tracking loop, not only can the same effects as the first embodiment and other embodiments described above be obtained, but also only one comparator is added to the synchronization holding circuit. Since synchronous detection can be performed, the circuit configuration can be significantly simplified.

〔Effect of the invention〕

As described above, according to the present invention, since the synchronization detection signal is obtained by adding the outputs of the two detectors of the synchronization holding circuit, noise is superimposed on the input signal, and in order to prevent false detection due to noise. As shown in Figure 3(f), synchronization detection is performed over a wide range where synchronization is maintained even if the threshold is set high as shown in Figure 3(f), so the code acquisition circuit starts during synchronization and temporarily demodulates the data. This has the effect that it will no longer be cut off.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a receiving device for spread spectrum communication according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional receiving device for spread spectrum communication, and FIG. 3 is for supplementing the explanation of synchronization detection. FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a block diagram showing still another embodiment in which the present invention is applied to another synchronization holding circuit. . 1 is a variable lil signal input terminal, 2 is a code acquisition circuit, 3 is a PN code generator, 4 is a first correlator, 5 is a demodulation circuit, 6
is the baseband data output terminal, 7 is the synchronization holding circuit, 8
is the second correlator, 9 is the third correlator, 10 is the first bandpass filter, 11 is the second bandpass filter, 1
2 is a first detector, 13 is a second detector, 14 is a subtracter, 15 is a loop filter, 16 is a voltage controlled oscillator, 17
is the third bandpass filter, 18 is the third detector, 1
9 is a comparator, and 20 is an adder. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] A code capture circuit that detects reception synchronization timing from a spread spectrum signal subjected to secondary modulation using a spreading code sequence; A PN code generator that generates a code sequence that is equal to the input spread spectrum signal; a first correlator that despreads a received signal using a reference PN code from the PN code generator; a demodulation circuit that demodulates information data from the output of the first correlator; 1 from the standard PN code
second and third correlators that multiply input spread spectrum signals by a PN code with an early /2 chip timing and a PN code with a slow 1/2 chip timing, respectively; output signals of the second and third correlators; first and second bandpass filters that remove noise; first and second detectors that perform envelope detection on the output signals of the first and second bandpass filters and send out correlation value detection signals; a subtracter that subtracts the output signal of the second detector from the output signal of the first detector; a loop filter that removes noise from the correlation detection signal output from the subtracter; and an output of the loop filter. A receiving device for spread spectrum communication comprising: a voltage controlled oscillator controlled by a signal; and a synchronization holding circuit that maintains synchronization of a signal sent out from the PN code generator using a clock signal from the voltage controlled oscillator. an adder that adds the output signals of the first detector and the second detector; and a comparator that converts the output voltage of the adder into a digital signal, and the synchronization holding circuit maintains synchronization by the signal from the comparator. 1. A receiving device for spread spectrum communication, characterized in that a state is detected and a start timing of the code acquisition circuit is determined.