KR950011080B1 - The asynchronic digital receving system of spread-spectrum communication method - Google Patents

Abstract

The device prevents the malfunction of the system owing to the noise and it provides easy system optimization method by digitally processing the spread spectrum and the baseband signal. The device contains: a PN code generator which generates reference PN code according to the control signal; an intermediate frequency(IF) generator which generates IF frequency for the intermediate converted signal; a 90 degree phase shifter which shifts the IF frequency by 90 degrees; an in-phase converter which mixes the converted IF signal of the receiver, eliminates the IF components, and extracts in-phase components; an in-phase rate loop which detects an envelop by using the digital signal of the in-phase converter.

Description

Spread Spectrum Asynchronous Digital Reception System

1 is a block diagram of a conventional analog receiving system.

2 is a block diagram of an asynchronous digital receiving system according to the present invention.

The present invention relates to a spread spectrum communication system, and more particularly, to a system for demodulating original data by digital signal processing and non-coherent detection of spread spectrum received signals.

In general, a spread spectrum communication receiving system is configured as shown in FIG. 1 to demodulate original data by analog signal processing and synchronous detection of a spread signal.

In FIG. 1, the signal received by the antenna passes through an amplifier 102 and a band pass filter (hereinafter referred to as BPF) 104 and from a mixer 108 to a carrier signal of the carrier generator 106. After the intermediate frequency is changed by being mixed with the carrier, the early PN code PN _E generated by the PN code generator 142, the punctual PN code PN _P , and the rate ) PN codes are multiplied by PN _L and mixers 110, 112 and 114, respectively. The output signals of the mixers 110, 112, and 114 are cumulatively added for one period of the PN code sequence in the integrators 122, 124, and 126, respectively, via the BPFs 116, 118, and 120, and then the multiplier Each envelope is detected by being squared at 128, 130 and 132, respectively. The output signal of the multiplier 128 is compared with a threshold value THR set in the comparator 134, and the two output signals of the multipliers 130 and 132 are subtracted by the subtractor 136 to detect a difference between the two signals. .

In this state, the initial synchronization is first adjusted using the output of the comparator 134 of the punctual loop 146. If the magnitude of the signal squared in the power generator 128 is smaller than a threshold value THR, the initial synchronization is determined to be incomplete and the reference PN code PN _P is shifted by one chip. Repeat. That is, the PN code generator 142 shifts the early PN code PN _E , the reference PN code PN _P , and the rate PN code PN _L by one chip by the output signal of the comparator 130.

When the output signal of the comparator 134 is larger than the threshold THR by the above operation, it is determined that the time difference between the transmission signal and the reception signal is within 1 chip, and the initial synchronization operation is completed. Do this. Looking at the synchronous tracking operation, the difference signal between the early-rate detected by the subtractor 136 is applied to a voltage controlled oscillator (VCO) 140 through the loop filter 138. The VCO 140 is controlled in proportion to the magnitude of the signal. Accordingly, the reference PN code PN _P generated by the PN code generator 142 is kept synchronized with the received signal.

While performing the above synchronization tracking, the synchronization demodulator 144 performs synchronization detection to restore the original data. At this time, the synchronous demodulator 144 demodulates the data by synchronous detection that must synchronize the intermediate frequency.

As described above, the conventional spread spectrum communication system has a problem in that malfunctions due to noise may occur because the entire reception system processes signals in an analog manner, and it is difficult to miniaturize the system. In addition, there is a problem that it is difficult to implement technically by demodulating the data by synchronous detection.

Accordingly, an object of the present invention is to provide a spread spectrum communication system receiving system capable of easily miniaturizing a system by preventing spread signals and base band signals in a digital manner and preventing malfunction due to noise. have.

Another object of the present invention is to provide a spread spectrum communication system that can be easily implemented by demodulating data as an asynchronous detection that does not require synchronization of an intermediate frequency signal at a transmitter and an intermediate frequency signal at a receiver.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an asynchronous digital receiving system according to the present invention, in which a PN code generator 306, an amplifier 204, a carrier generator 206, and a mixer 208 generate a reference PN code by predetermined control. And a BPF 210, the reception unit 202 for removing intermediate carriers from the received signal and performing intermediate frequency conversion, and the intermediate frequency oscillator 212 for generating an intermediate frequency signal for the intermediate frequency converted signal output from the reception unit 202. ), A π / 2 phase shifter 214 for shifting the phase of the intermediate frequency signal by π / 2, and a mixer 218 and a low pass filter (hereinafter referred to as LPF) 220 And A / D (Analog-to-Digital) converter 222 to mix the output signal of the receiver 202 with the intermediate frequency signal to remove the intermediate frequency component and extract the in-phase component digital The in-phase conversion unit 216, multiplier 226, accumulator 228 and a multiplier 230 to convert the statue And common rate-loop 224 that accumulated during one period PN code column a digital signal of the affected part 216 is multiplied by the reference PN code as a statue rate signal ID _L detects an envelope by the square, the retarder 234 and the multipliers (236 ), The accumulator 238 and the multiplier 240 delay the digital signal of the in-phase conversion unit 216 for 1/2 chip and multiply by the reference PN code as the in-phase reference signal ID _p to accumulate for one cycle of the PN code string. And an in-phase reference loop 232 for detecting an envelope, and a retarder 244, a booster 246, an accumulator 248, and a power-supply 250. The two-phase delayed signal is delayed by one-half chip and multiplied by the reference PN code as the in-phase early signal ID _E to accumulate and multiply for one period of the PN code string and square to detect the envelope, and the mixer 256 and the mixer 256. LPF 258 and the A / D converter 260 to output the output signal of the receiver 202 an orthogonal transform unit 254 for digitally transforming the intermediate frequency component by removing the intermediate frequency component and extracting quadrature-phase components by multiplying by? / 2 or more, a multiplier 264 and an accumulator 266; An orthogonal rate loop 262 configured to multiply the digital signal of the quadrature transform unit 254 by the orthogonal rate signal ODL as a quadrature rate signal ODL to accumulate for one period of the PN code sequence and square to detect the envelope. And a delay unit 272, a multiplier 274, an accumulator 276, and a multiplier 278 to delay the digital signal of the quadrature-transformer 254 for one-half chip as a quadrature reference signal QD. By orthogonal reference loop 270 that accumulates and multiplies for one period of the PN code string by multiplying by the reference PN code, and detects an envelope, a delay 282, a multiplier 284, an accumulator 286, and a multiplier 288. When the delayed signal is delayed by 1/2 chip by the quadrature reference loop 270 Multiply by the reference PN code as an orthogonal early signal QD _E to accumulate and square for one period of the PN code sequence to detect an envelope, and use an orthogonal early loop 280, the in-phase reference loop 232, and an orthogonal reference loop 270. An adder 292 that adds the detected signal of < RTI ID = 0.0 >), a comparator 294 that compares the magnitude of the output signal of the adder 292 < / RTI > An adder 296 that adds the detected signal of the loop 280, an adder 298 that adds the detected signals of the in-phase rate loop 224 and the orthogonal rate loop 262, and the adder 296. A subtractor 300 that detects a difference between the output signal of the and adder 298 and an initial synchronizer that detects the loss of the synchronization and the establishment of the initial synchronization by the outputs of the comparator 294 and the subtractor 300. Detection and synchronization tracking loss detector 302, the adder 300 and initial synchronous detection A clock controller 304 for controlling the PN code generator 306 according to the output signal of the synchronous tracking loss detector 302, and for one period of the PN code sequence of the in-phase reference loop 232 and the quadrature reference loop 270. And a demodulator 308 that asynchronously detects the accumulated signal and demodulates the original data.

In the configuration of FIG. 2, the in-phase conversion unit 216, the in-phase late loop 224, the in-phase reference loop 232, and the in-phase early loop 242 form an in-phase loop 252, and orthogonal-conversion unit 254. The orthogonal late loop 262, the orthogonal reference loop 270, and the orthogonal annular loop 280 form an orthogonal loop 290. In addition, the initial synchronization detection and synchronization tracking loss detector 302 and the clock controller 304 form a PN code synchronization means.

Hereinafter, an operation example of FIG. 2 according to the present invention will be described in detail.

The signal received at the antenna is amplified by the amplifier 204 and mixed with the carrier signal generated by the carrier generator 206 by the mixer 208 to remove the carrier and intermediate frequency conversion, and then passes through the BPF 210. The output signal of the BPF 210 is separated into an in-phase loop 252 and an orthogonal loop 290 so as to perform asynchronous detection, and the in-phase loop 252 has a mixer 218 of an in-phase conversion unit 216. ) Is applied to the mixer 256 of the quadrature converter 254 to the quadrature loop 290.

At this time, the intermediate frequency oscillator 212 generates an intermediate frequency signal with respect to the intermediate frequency converted signal output from the BPF 210. The intermediate frequency signal generated from the intermediate frequency oscillator 212 is applied to the mixer 218 of the in-phase conversion unit 216 and is equal to or more than π / 2 by the π / 2 phase shifter 214, so that Is applied to the mixer 256.

Accordingly, the signal applied from the BPF 210 to the mixer 218 of the in-phase conversion unit 216 is mixed with the intermediate frequency signal generated from the intermediate frequency oscillator 212 to remove the intermediate frequency component and extract only the in-phase component. The extracted in-phase component is converted into a digital signal by the A / D converter 222 after passing through the LPF 220. The spreading signal of the in-phase component converted from the A / D converter 222 into a digital signal is applied as it is, that is, undelayed to the multiplier 226, delayed by one and a half chips by the delay unit 234, and multiplier 236 Is applied. In addition, the signal delayed 1/2 of the chip by the delayer 234 is delayed 1/2 of the chip by the delayer 244 and applied to the multiplier 246. As described above, each of the signals delayed, delayed by 1/2 chip, and delayed by 1 chip becomes the in-phase rate signal DI _L , the in-phase reference signal ID _P , and the in-phase early signal ID _E. Each signal is then multiplied at the same time with a reference PN code generated from PN code generator 306 in multipliers 226, 236 and 246. The multiplied signals are accumulated in the accumulators 228, 238, and 248 for one period of the PN code sequence, and then squared by the power supplies 230, 240, and 250, respectively, to detect the envelope.

In addition, the signal applied from the BPF 210 to the mixer 256 of the quadrature transform unit 254 is mixed with the intermediate frequency signal equal to or more than π / 2 by the π / 2 phase shifter 214, thereby removing the intermediate frequency component and performing orthogonality. Only the phase component is extracted. After passing through the extracted quadrature component LPE 258, the A / D converter 260 converts the digital signal into digital signals. The spreading signal of the quadrature component transformed into the digital signal by the A / D converter 260 is applied as it is, without delay, to the multiplier 264, and is delayed by one and a half chips by the delay unit 272. 274). In addition, the signal delayed 1/2 of the delay by the delayer 272 is again applied by the delayer 282 to the multiplier 284. In this manner, each of the delayed, half-chip delayed, and one-chip delayed signals becomes orthogonal rate signal QD _L , orthogonal reference signal QD _P , and orthogonal early signal QD _E. Each signal is then multiplied at the same time with a reference PN code generated from PN code generator 306 in multipliers 264, 274 and 284. The multiplied signals are accumulated in the accumulators 226, 276, and 288 for one period of the PN code sequence, and then squared by the squares 268, 278, and 288, respectively, to detect the envelope.

The output signals of the in-phase reference loop 232 and the orthogonal reference loop 270 are summed in the adder 292, and the output signals of the in-phase early loop 242 and the orthogonal early loop 280 are added in the adder 296. The output signals of the in-phase late loop 224 and the quadrature late loop 262 are summed in the adder 298.

At this time, the signal related to the initial synchronization is the output of the comparator 294, and if the output of the adder 292 is less than the threshold value THR, the initial synchronization detection and synchronization tracking loss detector 302 detects that it is smaller than the threshold value THR. The clock controller 304 adjusts the PN code by one chip to repeat the initial synchronization process for synchronization of the spread signal and the PN code. If the adder 292 output is greater than the threshold THR, the initial sync detection and sync trace loss detector 302 detects this and assumes that the initial sync has been made and starts the sync tracking and data demodulation process.

On the other hand, demodulation of the data is performed in the demodulator 308. The demodulator 308 demodulates using the output of the accumulator 238 of the in-phase reference loop 232 and the output of the accumulator 276 of the orthogonal reference loop 270. Is done. At this time, demodulation is performed as asynchronous detection. Unlike the conventional method, since the output signals of the accumulators 238 and 276 are baseband signals, demodulation is facilitated. The demodulator 308 also extracts and outputs a data synchronization clock signal to latch the demodulated original data together.

On the other hand, the synchronization tracking uses the difference between the sum of the early loops detected by the subtractor 300 and the sum of the rate loops. The initial synchronization detection and the sum and rate of the early loops through the synchronization tracking loss detector 302 and the clock controller 304 are performed. Slowly or quickly adjusting the clock of the PN code to be proportional to the difference in the sum of the loops so that the synchronization of the received spread signal with the reference PN code generated from the PN code generator 306 is well maintained. At this time, the initial synchronous detection and the synchronous tracking loss detector 302 monitors whether the synchronous tracking is good at the time of the synchronization tracking. If the synchronization is out of order, the initial synchronization circuit is immediately activated to start the synchronization process again. Looking at the synchronous tracking process in more detail, the result of the subtractor 300 is, for example, the loop filter in the clock controller 304 composed of the loop filter 138 VCO 140 of FIG. The clock of the PN code in the PN code generator 306 is adjusted to be proportional to the amount corresponding to the difference between the 296 and the adder 298 to maintain synchronization.

As described above, the present invention enables miniaturization of the system by processing all signals after the carrier and the intermediate frequencies are removed, and improves reliability by preventing malfunction due to noise, and synchronizes the intermediate frequency signals at the transmitter and the receiver. As an asynchronous detection that does not require, there is an advantage that can be easily implemented by demodulating the data.

Claims (2)

A spread spectrum communication system comprising a receiving means for removing intermediate carriers from a received signal and performing intermediate frequency conversion, comprising: PN code generating means for generating a reference PN code under predetermined control, and the intermediate output from the receiving means. An intermediate frequency oscillating means for generating an intermediate frequency signal with respect to the frequency converted signal, a π / 2 or more means for increasing the phase of the intermediate frequency signal by? / 2, and an intermediate frequency converted signal of the receiving means In-phase conversion means for removing intermediate frequency components by mixing with the frequency signal, extracting in-phase components, and digitally converting the in-phase components; In-phase rate loop means for detecting an envelope by square and accumulating and accumulating the digital signal of the in-phase conversion means for 1/2 chip Delaying the digital signal of the in-phase conversion means and the in-phase conversion means for detecting the envelope for 1/2 chip, multiplying the reference PN code as the in-phase reference signal, accumulating for one period of the PN code string, and squared to detect the envelope. Delaying the signal delayed by 1/2 chip by the in-phase reference loop means and the in-phase reference loop means again by 1/2 chip to multiply the reference PN code as an in-phase early signal to accumulate and square for one period of the PN code string to detect the envelope. And orthogonal phase shifting means for mixing the intermediate frequency converted signal with the intermediate frequency signal equal to or more than π / 2 to remove intermediate frequency components, extracting quadrature components, and performing digital transformation; The digital signal of the phase conversion means is multiplied as the quadrature rate signal, and accumulated and squared for one period of the PN code sequence to detect the envelope. Orthogonal late-loop means and the digital signal of the orthogonal transform means are delayed for 1/2 chip and multiplied by the reference PN code as an orthogonal reference signal to accumulate for one period of the PN code string and squared to detect an envelope. The phase reference loop means and the signal delayed by 1/2 chip by the orthogonal reference loop means are further delayed by 1/2 chip to multiply by the reference PN code as an orthogonal early signal to accumulate and multiply for one period of the PN code string by an envelope. Quadrature early-loop means for detecting a; and comparison means for adding an envelope of the in-phase and quadrature reference signals and comparing it with a preset threshold; sum of the envelopes of the in-phase and quadrature early signals and the in-phase and quadrature Early-rate difference detection means for detecting a difference between the sum of the envelopes of the image rate signals, and outputs of the comparison means and the early-rate difference detection means. The PN code synchronizing means controls the PN code generating means to establish and synchronize the initial synchronization, and asynchronously detects the accumulated signal during one period of the PN code strings of the in-phase reference loop means and the orthogonal reference loop means. And a demodulating means for demodulating the asynchronous digital reception system. In a spread spectrum communication system having a receiving unit 202 for removing a carrier wave from a received signal and performing a center frequency conversion, a PN code generator 306 for generating a reference PN code under predetermined control, and the receiving unit 202 An intermediate frequency oscillator 212 for generating an intermediate frequency signal with respect to the intermediate frequency converted signal outputted from the subfield, a π / 2 phase shifter 214 for generating a phase of the frequency frequency signal by π / 2 or more, and the receiver The in-phase conversion unit 216 for removing the intermediate frequency components, extracting the in-phase components by mixing the intermediate frequency-converted signal of 202 with the generated intermediate frequency signal, and digitally converting the in-phase components, and the digital of the in-phase conversion unit 216 The in-phase rate loop 224 which multiplies the signal by the in-phase rate signal as the reference PN code, accumulates for one period of the PN code sequence, and squares to detect the envelope, and the digital signal of the in-phase conversion unit 216 for 1/2 chip. G The in-phase reference loop 232 for multiplying the reference PN code as an in-phase reference signal, accumulating for one period of the PN code sequence, and squared to detect an envelope, and a signal delayed by a half chip by the in-phase reference loop 232 In addition, the in-phase early loop 242 for accumulating and multiplying the reference PN code as the in-phase early signal and accumulating and squared for one period of the PN code sequence to detect the envelope is repeated as the in-phase early signal. Orthogonal transform unit 254 for removing intermediate frequencies, extracting orthogonal components, and digitally transforming the intermediate frequency signal, and the digital signals of the quadrature transforming unit 254 as quadrature rate signals. A quadrature late loop 262 that accumulates and multiplies for one period of the PN code sequence by multiplying with the PN code, and detects the envelope, and delays the digital signal of the quadrature conversion unit 254 for 1/2 of the quadrature. A quadrature reference loop 270 that multiplies with the reference pseudo-job code as a reference signal, accumulates for one period of the PN code sequence, and squares to detect an envelope, and a signal delayed by one-half chip by the quadrature reference loop 270. Orthogonal early loop 280 that is delayed by 1/2 chip and multiplies with the reference PN code as an orthogonal early signal, accumulates for one period of the PN code string, and squares to detect an envelope, and orthogonal to the in-phase reference loop 232. An adder 292 for adding the detected signal of the phase reference loop 270, a comparator 294 for comparing a magnitude of an output signal of the adder 292 with a preset threshold value, and the in-phase loop 242. An adder 296 for adding the detected signals of the orthogonal early loop 280, an adder 298 for adding the detected signals of the in-phase rate loop 224 and the orthogonal rate loop 262, and the adder A difference between the output signal of the 296 and the adder 298 The initial synchronous detection and synchronization tracking loss detector 302 which detects the loss of the establishment of the initial synchronization and the synchronization tracking by the output of the subtractor 300, the comparator 294 and the subtractor 300, and the subtractor ( A clock controller 304 for controlling the PN code generator 306 by an output signal of the initial synchronization detection and synchronization tracking loss detector 302, the in-phase reference loop 232, and a quadrature reference loop 270. And a demodulator (308) for demodulating the original data by asynchronously detecting the accumulated signal for one period of the PN code string of the "